Simulate Translate Test

Vector Translation Power

VTRAN® is a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and ATE. A powerful link between CAE and Test.


Simulation Results Verification

VCAP® is a comprehensive simulation data comparison and analysis program. When performing data comparisons, it provides powerful features for normalizing simulation data to adjust for differences in format, timing, and print mode. Timing analysis on a simulation results file includes reporting output pin delays and transitions, input pin timing behaviour, and a resource summary for checking tester compatibility.

Stimulus Pattern Generation

VGEN® is a stimulus generation language which reduces the time required to create, modify, document, and maintain simulation stimulus files by up to 80%. VGEN® is a generic language which supports numerous simulators and provides a powerful high-level language interface for the pattern generation task.

STIL, WGL and VCD/EVCD Graphical Display and Validation Tool

DFTView™ is a powerful interface tool which connects high-level test languages WGL and STIL to popular graphical waveform display tools, enabling users to see, edit and validate the actual waveforms described in the test languages. In addition, it can be used to validate VTRAN-generated ATE test programs for popular testers.

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