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Customer Quotes

"VTRAN is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with SourceIII has been positive and their support is extremely responsive and timely."

Khris Kofford

ON Semiconductor
Customer Quotes

"We currently use Vtran for translating wgl, evcd and vcd vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases."

Stuart Go

Staff Engineer
Open-Silicon, Inc.
Customer Quotes

"We use VTRAN to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly."

Wolfgang Schoell

Product/Test Engineer
Texas Instruments
Customer Quotes

"Source III VTRAN tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion."

Padma Penmatsa

Product Development Engineer
Marvell Semiconductors, Folsom
The Source III Promise

The success of our products is measured by your success with them. Source III will partner with you to make sure that our products are effective in meeting your needs.

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VTRAN™ is a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and ATE. A powerful link between CAE and Test.
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VCAP™ is a comprehensive simulation data comparison and analysis program. When performing data comparisons, it provides powerful features for normalizing simulation data to adjust for differences in format, timing, and print mode. Timing analysis on a simulation results file includes reporting output pin delays and transitions, input pin timing behaviour, and a resource summary for checking tester compatibility.
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VGEN™ is a stimulus generation language which reduces the time required to create, modify, document, and maintain simulation stimulus files by up to 80%. VGEN™ is a generic language which supports numerous simulators and provides a powerful high-level language interface for the pattern generation task.
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STIL-PRO™'s proven module provides reading, writing, and interpretation of STIL files, customized to work with OEM products. STIL-PRO™ is a linkable library module that provides an API between applications and STIL files.