The interoperability flow between Synopsys' TetraMAX and Source III's vtran with optional test interfaces allow for quick and easy translation of ATPG-generated test vector data to many popular device test program formats, as well as simulation testbench formats. Translations support signal timing and scan data mapping. In addition to this flow for translating TetraMAX WGL & STIL files to test programs, vtran's new Read-Back canned readers provide for a way to verify the test programs directly be translating them back to a Verilog or VHDL testbench for re-simulation prior to loading on a tester.
Translating TetraMAX Vector Files Using VTRAN
For a typical TetraMAX run, the result is a large WGL or STIL file often containing one or more scan chains and potentially several timing sets. These files may contain thousands, or millions, of vectors with many scan chain data load/unload operations. Translating these vector files into a test program for one of the popular device testers can be a formidable task. Vtran has been developed to specifically deal with this problem and makes the translation process very simple and straightforward.
When creating a WGL file under TetraMAX, the following parameter settings are recommended if vtran is to be used to translate the file to one of the supported tester (or testbench) formats:
set wgl -bidi_map -x -x set wgl -bidi_map z- z- set wgl -bidi_map 0x 0x set wgl -bidi_map 1x 1x set wgl -bidi_map xx xx set wgl -bidi_map z0 z0 set wgl -bidi_map z1 z1 set wgl -bidi_map zx zx set wgl -bidi_map zz zz set wgl -chain_list shift set wgl -group_bidis set wgl -inversion_reference master set wgl -last_scan set wgl -nomacro set wgl -nopad set wgl -pre_measured set wgl -scan_map dash
These settings are applicable to TetraMAX version 2.02 and later. They result in a WGL file that is consistent with the WGL syntax specification, which vtran requires. Also, refer to the On-Line Help facility of TetraMAX concerning vtran settings.
For information and examples of vtran command files that can be used to translate WGL and STIL files produced by TetraMAX to various testers and simulation testbenches, please also see the Application Notes page.
Source III's Simulation and Test Data Management tools focus on the creation, translation and analysis for vector data used or generated by logic simulators, ATPG and ATE. Our premier product, VTRAN, links simulation/ATPG vector data to ATE and other CAE tools. VGEN provides a high-level language for quick and easy creation of simulation vector data, and VCAP performs verification/analysis of simulation data files. All Source III products are supported on Sun Solaris SPARC, Solaris X86 and Linux platforms (32 and 64-bit).
- VTRAN - a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and ATE. A powerful link between CAE and Test.
- VCAP - comprehensive simulation data comparison and analysis program.
- VGEN - a stimulus generation language which reduces the time required to create, modify, document, and maintain simulation stimulus files by up to 80%.
- DFTView - a powerful interface tool which connects high-level test languages WGL and STIL to popular graphical waveform display tools, enabling users to see, edit and validate the actual waveforms described in the test languages.