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Why Use VGEN®?

Why Use VGEN<sup>®</sup>?

Design engineers today involved with ASIC or system-level design have become increasingly dependent upon CAE/CAD tools for the successful realization of their projects. Accuracy, completeness and timeliness are all important factors in achieving success. While many of the tools used today derive much of their effectiveness through the high-level of abstraction by which they allow the designer to work, the tools for stimulus generation remain primitive.

The situation is analogous to requiring software developers to write code in machine language (1's & 0's) or at best in assembly language. VGEN® is a high-level language stimulus COMPILER which elevates the designer's interface to the stimulus creation task and provides benefits for the designer similar to those that a high-level language gives a software developer.

About VGEN®

VGEN® is a popular product for stimulus generation for simulation. It uses a generic language to cut the time used to create, modify, or compare simulation stimulus files by as much as 80%, while also providing a very powerful, high level language option that makes performing tedious stimulus generation tasks more efficient.

VGEN® saves companies thousands while reducing error through a variety of tools and capabilities. VGEN® is able to:

  • Interface with over 30 popular test simulators and user definable output formats.
  • Read external data files and create new data tables.
  • Make signal grouping/vectorizing much easier.
  • Provide pattern looping and conditional testing.
  • Create logical, shift, and arithmetic operations for algorithmically generating patterns.

VGEN® also has a variety of easy to use, programmable items that include timing steps, pin timing, time scaling, pin types (NRZ, RZ, RO, RC, SBC, RX) and more.

As more and more excellent logic simulators are created, it’s important to take advantage of those capabilities as best you can. VGEN® enables you to ensure that you’re able to take advantage of the many different logic and timing simulation tools out there,

Additional Advantages Include:

  • Provides program framework for hierarchical, modular development of test vectors.
  • Provides facilities for algorithmic generation of test vectors.
  • Provides very powerful facilities for defining and modifying pin timing.
  • Provides facilities for dealing with asynchronous events and "parallel synchronous" circuits.
  • Provides excellent documentation on vector set organization and flow.
  • Interfaces to all popular simulators.
  • Substantially reduced development time for simulation stimulus vectors.
  • Dramatically improved documentation of vectors which aids in modification, maintenance and translation to optimal test programs.
  • Creation of vector sets which accurately emulate system timing resulting in more accurate and realistic simulation data.
  • A single, powerful vector generation language can be learned and used to meet all of your stimulus vector creation needs - independent of logic simulator used.

The VGEN® compiler was developed with a primary goal of portability between platforms, operating systems and logic simulators. It is currently running on Sun SPARC and HPUX platforms under UNIX operating systems. Building pattern files initially in an intermediate format results in the ability to cleanly interface to multiple simulators.

Each of the more than 30 interfaces currently available is a separate, independent module, with new interfaces and interface options constantly being added.

If you’d like to learn more about VGEN®, give us a call today, or fill out the form for a free quote.