Simulate Translate Test

VTRAN® Datasheet

VTRAN<sup>®</sup> Datasheet

VTRAN® is a vector translation program which reads the state/time information from simulation or ATPG data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and testers. The program deals with the general class of problems involving simulation stimulus/results re-formatting encountered by designers who must deal with more than one logic simulation environment. A collection of TEST options for VTRAN® also provide interfaces to many popular device testers, offering a direct path from logic simulation/ATPG vectors to test programs.

 

Applications

  • Re-formatting existing simulation data files which were generated by one simulator into files compatible with another simulator.
  • Translating state data files from logic analyzers, test programs or other data sources into stimulus files compatible with logic simulators. This includes the incorporation of pin timing.
  • Modifying simulation data files including changing pin lists, pin order, bus radixes, time offsets, pin timing and time scaling.
  • Translating simulation/ATPG output vector data or test programs into testbench data files for Verilog/VHDL resimulation and verification.
  • Vector translation from simulation or ATPG-generated vectors into functional test vectors for physical device testers.
  • Act as a front-end to graphical waveform tools enabling them to read and display nearly any vector data file.

VTRAN® is able to handle a wide range of input data formats by essentially letting the user describe the format. This is done in one of two ways. The first way is with the User-Programmable Reader using a single, or a collection of format descriptors which the user customizes to describe the input data format. The input format parameters which can be specified by the user include:

  • Pin names & order.
  • Whitespace characters.
  • Type & location of time tag, absolute or delta time.
  • Location of state data & bus radixes used.
  • Selection of TABULAR, SCRIPT or WAVE format.

In addition to this User-Programmable Reader, VTRAN® also provides a comprehensive collection of "canned" readers for popular simulator, ATPG and tester formats. Check the latest release for a current list of these "canned" readers.

At invocation, a command file is specified which contains the VTRAN® commands and descriptors. This file is composed of three major blocks; the OVF_BLOCK which specifies the format of the input data file, the PROC_BLOCK which defines any processing to be done on the data, and the TVF_BLOCK which defines the format of the output file and the target simulator.

The frustration of dealing with dissimilar simulator data formats is eliminated with VTRAN®. Files can easily be translated between most of the popular simulators in use today, with virtually any data manipulation desired. In support of vector translations from logic simulators or ATPG programs to physical device testers, VTRAN® is unmatched for its speed, user friendliness and low cost. The new collection of Read-Back canned reader modules also provide a way to verify VTRAN®-generated test programs thru testbench re-simulation prior to loading on a tester.

Data Readers

VTRAN® reads data files from simulators, or other sources, using one of two methods. For some of those more popular simulators, VTRAN® has canned readers which know how to read the time/state information of those files. Canned readers are currently available for the following file formats:

  • Verilog VCD (and EVCD) files
  • Toshiba TSTL2 files
  • Mentor LOG files and FORCE files
  • WGL and TSSI TDS ascii files
  • Valid Tabular I/O files
  • Fujitsu FTDL files
  • Synopses VSS WIF files
  • IMS Test MEM format files
  • TDL_91 format files
  • Quickturn CBC and QUEST files
  • STIL (1450.1999 IEEE Standard Test Interface Language) files
  • HP-3070 PCF files
  • VTRAN®-generated Teradyne Catalyst files
  • VTRAN®-generated Teradyne J750 files
  • VTRAN®-generated Teradyne J973 files
  • VTRAN®-generated Teradyne FLEX files
  • VTRAN®-generated Credence SWAV files
  • VTRAN®-generated Agilent (HP)93000 files

Additional canned readers are released periodically.

Data formats for which a canned reader is not available can be read by VTRAN® using its User-Programmable Reader Technology. Here, the user describes the format of data to be read using one or more "format strings" and VTRAN® then uses these strings to extract the time/state information from the file. This method can be used with any tabular or script file format - whether created from a simulator, tester or logic analyzer.

Data Processing

When translating time/logic data from one simulation/ATPG/tester format to another, it is often necessary to modify this data to clarify its intent, support debugging methodologies and conform to the target simulator/tester parameters and constraints. VTRAN® can perform an array of mapping and translation operations on the vector data it has read. These include:

  • State Mapping
  • Adding/removing pins
  • Modifying timing (scaling, offsetting, shifting edges)
  • Collapsing print-on-change data to cycle-data (cyclizing of vector data)
  • Imbedding timing into cycle-data
  • Separation of I/O data on bi-directional pins
  • Merging of bi-directional data
  • Masking vector data based on time windows, logic equations or state transition
  • Defining strobe windows for outputs
  • Pin name aliases
  • Extract Repeats or Loops in vector data

All of these operations are under complete user control so that the data in the output (translated) file can be customized for specific needs.

Output Processing

Once a set of simulation data has been read, and optionally processed, the output file format can be selected from any of the following currently available simulator interfaces (not a complete list):

ABLE, CUPL, EPIC/nanosim, FSIM, FTDL, HILO, LASAR, LSIM, MAXPLUS, MENTOR, ORCAD, QUEST, QSIM, SILOS, SPICE, STIL, SUSIE, TDL_91, TDS(TSSI), TSTL2, VERILOG Testbench, VERILOG VCD/EVCD, VHDL Testbench, VIEWSIM, VTI, WAVES, WGL

In additional to these standard formats, a UDF (User Defined Format) is also available for defining a custom output format. New formats are being added constantly and custom formats can also be made available. With the TEST options, VTRAN® can output vectors for physical device testers including:

Teradyne Catalyst, Teradyne J750, Teradyne J971/973, Teradyne FLEX, Credence SWAV, Agilent(HP)83000/93000, Advantest T66xx/T33xx, HP-3070, ITS9000 and IMS.

VTRAN® Command File

There are two command blocks required in every VTRAN® command file, and a third optional command block. The first of these is the OVF_BLOCK, which contains commands describing the format of data in the Original Vector File.

The second required command block is the TVF_BLOCK, which contains commands that essentially tell VTRAN® how to format the vectors for the Target Vector File.

The third (optional) command block is the process block (PROC_BLOCK) which must occur between the OVF_BLOCK and TVF_BLOCK in the file and is used to specify further processing to be done on the data prior to output formatting.

The VTRAN® command file structure can be summarized as follows:

OVF_BLOCK

BEGIN
OVF_BLOCK_COMMANDS
END

PROC_BLOCK {Optional}

BEGIN
PROC_BLOCK_COMMANDS
END

TVF_BLOCK

BEGIN
TVF_BLOCK_COMMANDS
END

END

Statement text in the VTRAN® command file is not case sensitive. However, the case of pin names is preserved in the TVF file. Pin names can be composed of printable ASCII characters with the exception of the following: space, comma, semicolon, <, >, [, ], {, }, (, ), =, \, &, | and @.

OVF_BLOCK COMMAND SUMMARY

AUX_FILE [=]"filename";

Used to specify an auxiliary file for some canned readers.

BEGIN_LINE [=] n;

Used by the User-Programmed Reader to define the line number in the OVF file at which VTRAN® should begin processing vectors.

BEGIN_STRING [=] "string";

Used by the User-Programmed Reader to define a unique text string in the OVF file after which VTRAN® should begin processing vectors.

BIDIRECTS [=] pin_list;

Defines the names and order of pins in the OVF file which are bidirectional.

BUSFORMAT radix; or BUSFORMAT pin_list = radix;

Specifies the radix of busses in the OVF file. (User-Programmed Reader)

CASE_SENSITIVE;

Allows there to be more than one signal with the same name spelling but differing only in case of letters in the name.

COMMENTS [ON | OFF];

Enables/Disables the passing of comments from the OVF to the TVF.

GROUP n [=] pin_list;

Together with the $gstatesn keyword, it tells VTRAN® how the pin states are organized. (User-Programmed Reader)

INPUTS [=] pin_list;

Defines the names and order of input pins in OVF file.

MAX_UNMATCHED [=] n [verbose]:

Specifies the number of, and information contained in, warnings for lines in the OVF which don't match a format_string. (User-Programmed Reader)

MERGE_FILE,  INPUTS/OUTPUTS/BIDIRECTS, orig_file, time_offset, .. end_Merge statements;

Used to merge or concatenate more than one input vector file.

ORIG_FILE [=] "filename";

Used to specify the OVF file name to be translated.

OUTPUTS [=] pin_list;

Defines the names and order of output pins in OVF file.

SCRIPT_FORMAT [=] "format#1" [, . ."format#n"] ;

Format descriptors for User-Programmed reader. For canned readers, un-quoted reader module name is specified instead of descriptors.

TABULAR _FORMAT [=] "format #1" [, . . "format#n"] ;

Format descriptors for User-Programmed reader. For canned readers, un-quoted reader module name is specified instead of descriptors.

TERMINATE TIME [=] n;

TERMINATE LINE [=] m;

TERMINATE STRING [=] "string";

Defines where in the OVF to stop processing, at a certain time (n) , line number (m) or when a "string" is reached. This is used only by the User-Programmed Reader.

WAVE_FORMAT [=] "format #1" [, . . "format#n"] ;

Format descriptors for User-Programmed reader.

WHITESPACE [=] 'a','b', 'c', . . ,'n';

Defines characters in the OVF file that are to be treated as though they are space, (they are ignored - User-Programmed Reader).

PROC_BLOCK COMMAND SUMMARY

ADD_PIN pinname = state1 [WHEN expr=state2, OTHERWISE state3];

Tells VTRAN® to add a new pin to the TVF, and allows you to define the state of this pin.

ALIGN_TO_CYCLE [-warnings] cycle pin_list @ time, . . . ,pin_list @ time ;

Print-on-change vectors can be mapped to a set of cycle data, the state of each pin in a given cycle is determined by its state at a specified strobe time in the OVF.

ALIGN_TO_SIGNAL [-novector] ref A->B SAMPLE=pinlist @ offset;

Print-on-change vectors are mapped to cycle-based vectors, with each cycle boundary determined by a reference signal transition, and the state of each pin in a given vector determined at the specified strobe time from the start of a cycle.

ALIGN_TO_STEP [-warnings] step [offset];

Forces a minimum time resolution in the TVF.

AUTO_ALIGN [-warnings] cycle;

Collapses print-on-change data in the OVF to cycle data by computing strobe points from information given in the PINTYPE commands.

BIDIRECT_CONTROL pin_list = dir WHEN expr = state ;

Separates input data from output data on bidirects under control of a pin state or logical combination of pin states.

BIDIRECT_CONTROL pin_list = direction @ time ;

Separates input data from output data on bidirects based upon when the state transitions occur.

BIDIRECT_STATES INPUT state_list, OUTPUT state_list ;

Separates input data from output data on bidirects where unique state characters identify pin direction.

CHECK_WINDOW pinlist @ start1, end1 [start2, end2];

For translating print-on-change data to event output formats, specifies window(s) during which output data is checked in target file; output data is masked to don't care outside of window(s).

CYCLE [=] n;

Used to specify the time step between vectors in the OVF when the format of the vectors does not include a time stamp.

CYCLE_SHIFT [fill_character=c] pinlist @ n;

Causes the states on specified signals in all vectors to be shifter either forward or backwards in time by (+/-)n vectors.

DISABLE_VECTOR_FILTER;

Can be used to disable filtering of redundant vectors.

DONT_CARE 'X';

Defines the character state to which output pins should be set outside of their check windows.

EDGE_ALIGN pinlist @ rtime [,ftime] [xtime];

Can modify pin transition times by snapping them to predefined positions within each cycle.

EDGE_SHIFT pinlist @ rtime [,ftime] [,xtime];

Can modify pin transition times by shifting them by fixed amounts.

MASK_PINS [mask_character ='X'] [pin_list] @ t1, t2 [-CYCLE];

MASK_PINS [mask_character ='X'] [pin_list] @ CONDITION logic_expr ;

MASK_PINS [mask_character="X"] [pinlist] @ TRANSITION A->B [,-1] [, +n];

MASK_PINS [mask_character="X"] [pinlist] @ CONTROL_TRANSITION ctl_pin A->B [,start] [, end];

MASK_PINS pinlist @ SEQUENCE "input_sequence", "output_sequence";

Masks the state of specified pins to the mask_character within the time range between t1 and t2, when a specified logic conditions exists on other pins, for a number of cycles surrounding the pin's transitions, or for a number of transitions surrounding a control pin transition. The SEQUENCE option replaces specified state sequence with new one.

PINTYPE pintypepin_list @ start1 end1 [start2, end2] ;

Defines the behavior and timing to be applied to input and/or output pins during translation.

POIC;

Specifies that vectors in the OVF file should be translated to the TVF only when at least 1 input pin has changed in the vector (used only with CBC format).

SCALE [=] nn;

Used to linearly expand or reduce the time line of the OVF. Happens prior to any timing modifications. Use only with print-on-change input formats.

SEPARATE_TIMING;

Tells VTRAN® not to incorporate pin timing and behavior into the vectors themselves.

STATE_TRANS [dir] 'from1'->'to1', . . ;

Defines a mapping from pin states in the OVF file to states in the TVF file. [dir] can be ALL_INPUTS, ALL_OUTPUTS, BIDIR_INPUTS, BIDIR_OUTPUTS, PURE_INPUTS, PURE_OUTPUTS.

STATE_TRANS_GROUP pin_list = 'from1'->'to1', . . ;

Supplements the STATE_TRANS command by providing state translations on an individual pin or group basis.

TEMPLATE_CYCLIZATION [params] ;

Used with TIMESET blocks to invoke cyclization of print-on-change data with multiple timesets.

TIMESET name ... ENDTIMESET;

Defines timeset block of CYCLE, PINTYPE and IDENTIFIER statements (used with TEMPLATE_CYCLIZATION).

TIME_OFFSET [=] n ;

When reading the vectors from the OVF, the time stamp can be offset by an arbitrary amount.

TVF_BLOCK COMMAND SUMMARY

ADD_VTB_TEXT = "text", Before|After, Location ;

Mechanism for adding text (statements or comments) to Verilog Testbench files.

ALIAS ovf_name = tvf_name, . . . ;

ALIAS "ovf_string" = "tvf_string";

Provides a way to change the names of pins listed in the OVF, for listing in the TVF. The first form changes individual pin names, thesecond form does global string replacement in all pin names.

ALIAS_TSET ovf_tsetname = tvf_tsetname;

Provides a way to change the names of timesets found in the OVF, for listing in the TVF.

BIDIRECTS [=] pin_list;

Defines the names and order of pins to be listed in the TVF file which are bidirectional.

BUSFORMAT radix;

BUSFORMAT pin_list = radix;

Specifies the radix of busses in the TVF file.

COMMAND_FILE [=] "filename";

Allows the user to specify the name of a separate output command file for the target simulator, in addition to the vector data file.

DEFINE_HEADER [=] "text string";

Allows you to inhibit the automatic generation of headers and replace it with a custom text string. For tester formats this inserts text at the top of the test program.

DELETE_PINS pinlist;

Removes the listed pins from the output (TVF) file.

FORCE_SEQUENTIAL_BUSSES [+|-];

Forces busses with non-sequential indexes to be sequential.  For Verilog Testbench format, busses must have sequential indexes.

HEADER [=] n;

Causes a vertical list of the pin names to appear as comments in the TVF every n vector lines.

INPUTS [=] pin_list ;

Defines the names and order of pins to be listed in the TVF file which are inputs.

INPUTS_ONLY;

Causes only input and the input versions of bidirectional pins to be listed in the TVF.

LOWERCASE;

Forces all pin names in the TVF to use lower-case letters.

MERGE_BIDIRECTS state_list ;

MERGE_BIDIRECTS rules = n ;

Merges the input and output state information of a bidirectional pin to a single pin after it has been split and processed.

OUTPUTS [=] pin_list ;

Defines the names and order of pins to be listed in the TVF file which are outputs.

OUTPUTS_ONLY;

Causes only output and the output versions of bidirectional pins to be listed in the TVF.

PIN_INFO_FILE = filename, "file_format";

Specifies file containing signal name aliases and tester channel information.

RENAME_BUS_PINS [buslist =] format;

Provides a way of globally modifying all bus names [or a specified list of them] in the TVF to scalar names.

RESOLUTION [=] n;

Specifies the resolution of time stamps in the output vector file (n = 1.0, 0.1, 0.01, 0.001. 0.0001, 0.00001 or 0.000001).

SCALE [=] nn ;

Linearly scales all times to TVF. Used with event-based output formats.

SIMULATOR [=] name [param_list];

Defines the target vector file format to be compatible with the simulator named.

STOBE_WIDTH [=] n;

Used with several of the simulator interfaces to define the width of an output strobe window.

SYSTEM_CALL ". . .text . . . ";

Upon completion of translating vectors from the OVF to the TVF, VTRAN® sends this text string to the system just prior to termination.

TARGET_FILE [=] "filename";

Specifies the name of the output Target Vector File.

TESTER_FORMAT [=] testername [param_list];

Defines the target tester for which the output file should be formatted.

TITLE [=] "title";

Specifies a special character string to be placed in the header of certain simulator vector files.

UPPERCASE;

Forces all pin names in the TVF to be listed with upper-case letters.