Simulate Translate Test

VTRAN® Conversions

VTRAN® was designed to fit into several vector translation flows. Converting STIL or WGL files from ATPG tools into test programs, or going directly from simulation VCD dump files to ATE, VTRAN® can handle the task simply and cost-effectively. It also is able to validate these test programs via a playback or VirtualTest ReadBack translation prior to loading onto your tester. The following VTRAN® conversion flow charts highlight several common applications where VTRAN® can be employed.

For more information on using VTRAN® for any fo the flows below, see the Tester Specific App Notes at:

Also for more general information on VTRAN® including the Vtran User's Guide, visit:

VTRAN® Product Page

Convert ATPG-Generated WGL & STIL files to ATE

VTRAN® greatly simplifies the translation of ATPG-generated WGL or STIL files to a wide variety of Test Equipment. These translations include support for multiple timesets and scan data syntax. Optional processing that can be performed by VTRAN® are scaling of timing, delete signals, add signals with complex state equations, mask signals, compression with repeats or loops, expansion of scan, expansion of repeats or loops, file merging and concatenation, insertion of comments or new statements, changing signal names, and many other options.

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Convert WGL, STIL and Test Programs to VERILOG or VHDL Testbench

Translating WGL, STIL or previously VTRAN-generated Test Programs to a Verilog or VHDL testbench is often a time and cost saving step. Before loading the Test Programs onto a physical device tester, or before using the WGL or STIL files in down-stream flows, it is very advantageous to validate them by first translating them to a Validation Testbench for simulation. VTRAN® provides this capability for both Verilog and VHDL environments.

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VTRAN® greatly simplifies the translation of Verilog or VHDL Simulation-generated VCD or EVCD files to a wide variety of Test Equipment. These translations include support for multiple timesets and involve the cyclization of the print-on-change vectors into cycle-based vectors for ATE. Optional processing that can be performed by VTRAN® are scaling of timing, delete signals, add signals with complex state equations, mask signals, compression with repeats or loops, file merging and concatenation, insertion of comments or new statements, changing signal names, and many other options. The VTRAN® ReadBack (playback) flow provides a means of validating the Test programs prior to loading it onto a tester.

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Product Support

Customer Quotes

  • We currently use Vtran for translating wgl, evcd and vcd vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with SourceIII has been positive and their support is extremely responsive and timely.
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
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