Simulate Translate Test

VGEN® Data Sheet

VGEN<sup>®</sup> Data Sheet

VGEN® is a stimulus generation language which reduces the time required to create, modify, document and maintain simulation stimulus files by up to 80%" VGEN® provides a powerful high-level language interface for the pattern generation task and runs on a variety of hardware platforms including SUN Solaris and HPUX.

With VGEN®, a designer can define and document simulation stimulus patterns using powerful high-level language constructs which are tailored to the particular needs of simulators and testers. VGEN® also allows substantial flexibility for modifying parameters that are important to simulators and testers. Principle features of VGEN® include:

  • Signal grouping (vectorizing)
  • Subroutines with parameter passing
  • Logical, arithmetic & shift operations for algorithmically generating patterns
  • Pattern looping & conditional tests
  • Reading data from external data files
  • Data Tables
  • Commenting for improved documentation & debugging
  • Programmable Timing step, pin timing & time scaling
  • Programmable Pin Types - NRZ, RZ, RO, RC, SBC, RX....
  • Multiple time lines for parallel synchronous designs
  • Method for defining expected results on output pins with link to VCAP
  • Interfaces to over 30 popular simulators + user-definable output formats

Today's logic simulators offer substantial capability for doing comprehensive, accurate logic and timing simulation. VGEN® is a tool which enables the designer to take full advantage of this capability. VGEN® can also be used to specify expected state data for output pins which can then be used by VCAP® to verify simulation results data.