Software Products

VTRAN is a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators including Verilog and VHDL testbenches, as well as numerous device testers. The program deals with the general class of problems involving simulation stimulus/results re-formatting and editing encountered by designers who must deal with more than one CAE tool environment. The test options for VTRAN provide interfaces to many popular device testers. With these options, popular simulation and ATPG formats like WGL, VCD and STIL can be automatically translated into Credence, Teradyne, Agilent and other test programs.

VGEN is a stimulus generation language which reduces the time required to create, modify, document and maintain simulation stimulus files by up to 80%. VGEN is a generic language which supports numerous simulators and provides a powerful high-level language interface for the pattern generation task.

VCAP is a comprehensive simulation data comparison and analysis program. When performing data comparisons, it provides powerful features for normalizing simulation data to adjust for differences in format, timing and print mode. Timing analysis on a simulation results file includes reporting output pin delays and transitions, input pin timing behavior, and a resource summary for checking tester compatibility.

STIL-Pro proven module provides reading, writing and interpretation of STIL files, customized to work with OEM products. STIL-Pro is a linkable library module that provides an API between applciations and STIL files.

VECTOR TRANSLATION SERVICES

Source III provides vector file translation services involving the translation of logic simulation data files to vector formats either for physical device testers or for other logic simulators and analysis tools. We support translations between more than 30 formats. More...