10/17/08 (Also see INTERFACES/README file) RELEASE 8.2 ----------- 1) This release of Vtran includes a new Register feature. This supports the concept of a memory, or register, element that can be used in a compound logic expression. The basic idea is to provide a means whereby the occurance of an event (logic condition or time) can be remembered and used as part of a logic expression for other vtran statements. This element is specified using the Register statement in the PROC_BLOCK with the following syntax: Register name [init=1], set @ CONDITION logic_expr | @ TIME time_set : clear @ CONDITION logic_expr | @ TIME time_clear ; A Register element can have only the values of 1 or 0. It defaults to an initial value of 0 and can be set (to 1) and cleared (set to 0) by the logic_expr or absolute time specified as part of the statement. The set and clear portions of the statement are optional but at least one of them should normally be present. As with all logic_exprs, the states of signals used in the expressions are those states directly from the input file (prior to any STATE_TRANS). There are no restrictions on the number of Register elements specified or the number of times they get set and cleared during the vector translation. Register elements can in turn be used as part of a logic_expr for any of the existing statements that use logic_expr's (ADD_PIN, BIDIRECT_CONTROL, INSERT_REPEAT, INSERT_STATEMENT, and MASK_PINS). The Register elements are intended for use with cycle-based output formats. During vector processing, any Register elements defined are evaluated before any of the signal state processing occurs. An example of its use would be: Register r_sample set @ CONDITION (pin1=1)&(pin2=1) : clear @ CONDITION reset=1 ; . . . MASK_PINS bluepin @ CONDITION (r_sample=1)&(alu_start=1)&(alu_start(-1)=0) ; In this example, the signal bluepin will be masked to an X during a cycle whenever pin1 and pin2 are both a logic 1 in the current vector, or were both a logic 1 sometime prior with no reset=1 having occurred, and alu_start makes a 0->1 transition. The main function of the Register element is to provide a memory element that can remember that some event or time has occurred prior to the current vector. This can then be used as part of a logic_expr for the VTRAN statements which use them. Both the set and clear controls for all Registers are evaluated for each vector. If both the set and clear controls for a given Register are met, a Warning message is generated and the Register value (0 or 1) is left unchanged. Some of the other Vtran statements that are controlled by a CONDITION clause or a TIME clause provide third control type, TRANSITION. Since the signal transition control is already provided with the compound logic expression, it is not supported in the Register statement. The state of a Register in a previous or future vector cannot be used in a control expression. In other words, for a Register Reg1, the syntax: CONDITION (Reg1(-1)=0) is not valid. The Register feature cannot be used in ADD_PIN or BIDIRECT_CONTROL statements when a User-Defined Reader is used in the Vtran translation. It is best not to use an added pin's state in the definition of a Register that is used to control the state of another added pin. The results are order-dependent and unpredictable Below are examples of Register definitions and of Register references in each of the Vtran statements that use them. Example: Register Reg1 init = 0, set @ CONDITION bidir1 = 1 : clear @ TIME 4000; Register Reg2 init = 0, set @ CONDITION bidir1.O = 0 : clear @ CONDITION sin = 1; INSERT_REPEAT 5 @ CONDITION (ctl1 = 1) & (Reg1=1); ADD_PIN newPin LINK_TIMING ctl2 = 0 WHEN Reg2 = 1 : = 1 WHEN Reg2 = 0 : = X OTHERWISE; Example: Register Reg1 init = 0, set @ TIME 2000 : clear @ CONDITION ctl1 = 0; Register Reg2 init = 0, set @ TIME 3000 : clear @ TIME 6500; INSERT_STATEMENT "/* This is an inserted statement */" @ CONDITION (ctl2 = 1) & (Reg1=1); INSERT_STATEMENT "/* This is another inserted statement */" @ CONDITION (ctl1 = 1) & (Reg2=1); Example: Register Reg1 init = 0, set @ TIME 2000; Register Reg2 init = 1, clear @ TIME 6500; MASK_PINS son @ CONDITION (ctl1 = 1) & (Reg2); Example: Register Reg1 init = 0, set @ TIME 2000 ; BIDIRECT_CONTROL bidir1 = output WHEN (ctl2 = 1) & (Reg1=1); 2) Fixed a bug in Verigy 93K writer. Previously was missing '-' on scan outs which are bidirect signals on set-up vector for scan. 3) Changed behavior of FLEX writer so that when a scan operation is taking place and scan data for some of the scan signals is not specified in the input file, vtran will now still generate scan data for those signals by using the last vector state for input scans and X for scan outputs. In other words, for all scan operations, all scan signals will have scan data specified regardless of whether or not scan data was specified in the input file for all scan signals. In order to change back to the previous behavior, the following flag can be added to the TESTER_FORMAT command: -INHIBIT_UNUSED_SCAN 4) Added support for MAX_REPEAT_COUNT in the Verigy 93K writer. 5) Previously, Repeats were supported on the FLEX writer when in single mode. Support has now been added for Repeats in Dual, Quad and Octal mode also. 6) Fixed a bug in Verigy 93K writer concerning missing SQPG PADDING statement when nested loops with repeats. RELEASE 8.1.6 ------------- 1) Fixed bug in placement of end_loop statement for Teradyne J750 testers. 2) Enhanced vtran to automatically look for single vector loops and convert them to Repeat statements for Teradyne testers. RELEASE 8.1.5 ------------- 1) Added a new feature that allows the user to specify arbitrary statements to be inserted into the Target Vector File. This is accomplished with the PROC_BLOCK INSERT_STATEMENT command, using the following syntax: INSERT_STATEMENT "statement" @ CONDITION [-before|after,] [-count n,] compound_logic_expr; or INSERT_STATEMENT "statement" @ TRANSITION [-before|after,] [-count n,] signal_name a->b ; or INSERT_STATEMENT "statement" @ TIME [-before|after,] t1; The intention of this feature is to allow arbitrary tester or simulation statements, like subroutine or macro calls, to be placed at specific locations in a test pattern or testbench. This feature could also be used to insert comments for documentation. For cycle-based output formats (testers, WGL, STIL, etc..) the -before flag (the default) causes the statement text to be placed just prior to the vector where the CONDITION, TRANSITION or TIME occurs. For event-based outputs, such as a testbench, the statement text is inserted within the same event time that the CONDITION, TRANSITION or TIME occurs. If the TIME control is used, and there is no vector or event at the specified time, the following rules apply: With the -before flag, the statement will be inserted before the vector or event that precedes the specified time. With the -after flag, the statement will be inserted before the first vector or event that follows the specified time. Example: For a specified time of 450ns, and vectors at 400ns and 500ns, the -before statement will be before the vector at 400ns. Example: For a specified time of 650ns, and vectors at 600ns and 700ns, the -after statement will be before the vector at 700ns. The -count n option indicates that the replacement is to apply to the first n occurences of the CONDITION or TRANSITION. An example would be: INSERT_STATEMENT "call subr_set ;" @ CONDITION -count 1, (pin1(-4)=1) & (pin2(+8)=0) ; This would insert the test "call subr_set;" just before the vector where the pin1 signal was a 1 four vectors prior and pin2 is a 0 8 vectors after. It will do this only the first time this condition occurs. The CONDITION and TRANSITION controls are evaluated before any state transitions are applied, so any states specified should be states from the Original Vector File. To include a multiple-line "statement", include a newline inside the quotes; don't use the backslash escape (\\n). When INSERT_STATEMENT is used in conjunction with RepeatThreshold or LoopThreshold, the inserted statements are treated like timeset references: if inserted statements for vectors being compared don't match, the repeat or loop is terminated. 2) This version of Vtran includes a new, optional IMPORT_NAMES command for the Teradyne Writer. The INSERT_STATEMENT feature allows the user to insert subroutine calls in the Target Vector File (this is just one possible application). For the Teradyne J750 and Flex models, the names of these subroutines need to be declared in an IMPORT statement. The IMPORT_NAMES command is part of the TESTER_FORMAT command for Teradyne: TESTER_FORMAT teradyne, -FLEX+, IMPORT_NAMES = "text", ... ; The text between the double-quotes is included in the output file in an IMPORT statement of the form: IMPORT text; Typically, for this application, the text consists of one or more comma-separated names. 3) Enhanced vtran's support for the SCALE command. Previously, this process was applicable only to print-on-change output formats. In this release, the SCALE statement can be used in the PROC_BLOCK when translating cycle-based input vectors to cycle-based output vector formats (WGL, STIL, all tester formats). The syntax of the command remains unchanged: SCALE = ; The default value is 1.0. When used with cycle-based Original Vector Files, the timeset values from the OVF will be scaled, as well as the timestamps on the vectors. The SCALE command in the TVF_BLOCK still is applicable only to print-on-change files. If the SCALE command is used both in the PROC_BLOCK and the TVF_BLOCK, an error message will be generated and Vtran will terminate. 4) A new parameter flag has been added to the STIL formatter in order to generate STIL files which are compatible with the Credence Diamond tester. The syntax would be: tester_format STIL, -Diamond, ...... ; The STIL syntax generated is still valid 1450-1999 syntax, but it uses some specific conventions to maintain compatability with the Diamond tester. 5) This version of Vtran includes an enhancement to the PROC_BLOCK MASK_PINS command. The TRANSITION and CONTROL_TRANSITION control types define when pin masking is to occur, based on state transitions on the masked pin or a separate control pin. They have optional "start" and "end" fields, to specify a range of cycles where masking is to be applied. These cycles are defined relative to the cycle in which the transition occurs. Previously, if the controlling transition occurred again while the pin was being masked within a range of cycles, the masking would terminate at the end of the range. Effectively, this controlling transition would be ignored. The enhancement allows the masking to be "retriggered" in this situation: the presence of a controlling transition within the range of masked cycles would adjust the end of masking. The new end cycle is calculated as though the new transition marks the beginning of masking. This retriggering can happen multiple times following an initial transition. The syntax for the new feature is: MASK_PINS [MASK_CHARACTER=X] pinlist @ [NOT] TRANSITION a->b, start, end , -RETRIGGER; or MASK_PINS [MASK_CHARACTER=X] pinlist @ [NOT] CONTROL_TRANSITION ctl_pin a->b, start, end, -RETRIGGER; The default is the previous behavior. The masking will retrigger only if the -RETRIGGER flag is present. It is selectable on a per-command basis. Within a given Vtran command file, some MASK_PINS commands can be retriggerable, while others are not. 6) New options have been added to the Verilog_tb_readmem output formatter in order to provide more information on signal failures and expected values in the file (and it's resulting VCD file). The first option causes one fail signal to be added to the tesstbench for every output signal. These fail signals have the same name as their corresponding output signal but with a __f suffix added. At any time that an output fails during a check, this fail signal goes to a logic 1. The syntax for this optinal falg is: SIMULATOR Verilog_tb_readmem, -ADD_MISMATCH_PINS, . . . ; The fail signal will stay a logic 1 for a default time of 2ns, but this time (the width of the logic) can be changed using the optional parameter MISMATCH_PINS_WIDTH, with a syntax as follows: SIMULATOR Verilog_tb_readmem, -ADD_MISMATCH_PINS, MISMATCH_PINS_WIDTH = "nn", . . . . ; where nn is any positive number of nanoseconds. In addition, the new parameter -ADD_EXPECT_PINS will cause vtran to also add a set of wires to the testbench which contain the expect value for each output signal and input signal. These wires are named the same as each output/input signal with a __E and __I suffix respectively appended. The optional parameter syntax is: SIMULATOR Verilog_tb_readmem, -ADD_MISMATCH_PINS, -ADD_EXPECT_PINS, MISMATCH_PINS_WIDTH = "nn", . . . . ; 7) This release of Vtran adds Quad and Octal Mode support to the Teradyne FLEX Writer. By default, the FLEX Writer generates Single mode. The user can select Quad or Octal mode with the tester parameter -QUAD_MODE or -OCTAL_MODE: TESTER_FORMAT teradyne -FLEX+, -QUAD_MODE, or TESTER_FORMAT teradyne -FLEX+, -OCTAL_MODE, In Quad mode, vectors are grouped in multiples of 4. In Octal mode, vectors are grouped in multiples of 8. If there are single-row repeated vectors in the OVF, the Vtran Reader must be invoked with the "-expand_reps" switch to flatten the repeats. Because the vectors are grouped in sets, there must be a multiple of 4 or 8 vectors in the FLEX file. If a wrong number of vectors is generated from the OVF, extra "pad" vector(s) will be appended at the end. There must be a multiple of 4 or 8 parallel vectors between Scan vectors. If necessary, the FLEX Writer will insert "pad" vector(s) before the scan_setup vector, to enforce this constraint. There must be a multiple of 4 or 8 scan cycles in a Scan vector. If necessary, the FLEX Writer will add "pad" cycle(s) to enforce this constraint. For a scan-in pin, the SCANIN_DEFAULT state will be used for the first scan cycle. For a scan-out pin, an 'X' state will be used for the last scan cycle. For the "pad" vector(s) at the end of the file or between Scan vectors, the following rules are used by default: - All pure-input signals which are not clocks will maintain their last state in the vector just prior to the padding vector. - All pure-outputs will be forced to X. - All clocks (RZ or RO) will be forced to their inactive states (0 for RZ and 1 for RO). - All bidirects will be forced to their last state in the vector just prior to the padding vector if it was an input; otherwise they will be forced to X. The user can override these default states with an optional padding file. The file name is specified with the tester parameter DUAL_MODE_PADDING_FILE, which was added when Dual Mode support was added: TESTER_FORMAT teradyne -FLEX+, -QUAD_MODE, DUAL_MODE_PADDING_FILE="myStates.pad", The padding file can be used to override the pad states for any or all pins in any or all timesets. The format of the file is described in Appendix D of the Vtran User's Guide, under the section heading "XMODE PADDING FILE". 8) Added option to vtran which accumulates and reports statistics on the the states or state transitions of output (or input) signals during a set of vectors. When generating test programs or testbench files, especially when the user must specify sample points and when MASK_PINS is being used, it is useful to know to what extent output signals are being checked in the target file. The syntax for this in the TVF_BLOCK is: CREATE_STATISTICS "filename" pinlist [=] [logic0 state_list] [logic1 state_list] [start nn] [end mm] ; where "filename" is the name of the output file which will contain the statistics report. The pinlist is a space- or comma-separated list of signals to be monitored and reported. The states in the state_lists must be separated with space. If both logic0 and logic1 states are defined, the first state_list must be terminated with a comma. The optional start and end parameters are the event or cycle times of the first and last vectors for which statistics should be recorded. By default, statistics will be recorded for all vectors. Examples of the syntax are shown in the last section of this document. If a DELETE_PINS statement is included in the TVF_BLOCK, the CREATE_STATISTICS statement must be placed before the DELETE_PINS statement. The report will have the following format, following a header: logic 1 logic 0 Signal Name (first compare) (first compare) ----------- --------------- --------------- Out_1 2344 (1000ns) 44 (4000ns) Bidir_1.O 6 (100ns) 1988 (2000ns) transitions to logic 1 transitions to logic 0 Signal Name (first transition) (first transition) ----------- ---------------------- ---------------------- In_1 2344 (2500ns) 44 (100ns) Bidir_1 6 (200ns) 1988 (600ns) transitions to input transitions to output Signal Name (first transition) (first transition) ----------- -------------------- --------------------- Bidir_1 45 (250ns) 44 (1000ns) This feature is applicable both to cycle-based and to print-on-change Target Vector File formats. The statistics are collected after any signal masking has been done (MASK_PINS statements) and after state transitions (STATE_TRANS command) have been applied but before bidirectional signals are merged. The user can select input, output, and bidirectional signals for the pinlist. Pre-defined groups (ALL_INPUTS, ALL_OUTPUTS, PURE_INPUTS, PURE_OUTPUTS, BIDIR_INPUTS, BIDIR_OUTPUTS) can be included in the pinlist. For output signals (including the output data for bidirectional signals), the following statistics are generated: - number of compares to logic-0 state - number of compares to logic-1 state - first cycle with logic-0 state - first cycle with logic-1 state If the TVF is print-on-change, consecutive vectors with a logic-0 or logic-1 state will be counted as a single compare. If the TVF is cycle-based, each vector will count as a single compare. For input signals (including the input data for bidirectional signals), the following statistics are generated: - transition to logic-0 - transition to logic-1 - first cycle with transition to logic-0 - first cycle with transition to logic-1 For both print-on-change and cycle-based TVF, only transitions from a logic-0 state to/from a logic-1 state will be counted. A transition from intermediate "other" states (e.g., Z, X) to logic-0/logic-1 will be included in the statistics only if the preceding state was logic-1/logic-0. For bidirectional signals, the following statistics are generated: - transition from input state to output state, ignoring X and Z states - transition from output state to input state, ignoring X and Z states - first cycle with transition from input state to output state - first cycle with transition from output state to input state Statistics are collected before bidirectional signals are merged onto a single pin. Vectors in which both the input and the output part of the signal have a Z or X state are ignored when counting transitions. If the input part of the signal is not Z or X, and the output part of the signal is Z or X, the signal is considered to have an input state. If the input part of the signal is Z or X, and the output part of the signal is not Z or X, the signal is considered to have an output state. If this state is different from the last vector that has an input or output state, the vector is counted as a transition. This is true both for print-on-change and cycle-based TVF formats. The state at time zero is the initial state of the signal; there is no transition at time zero (from an undefined state). For Scan vectors, the parallel vector data is used for collecting the statistics. For a repeated vector, the counts of compare to logic-0 and compare to logic-1 are incremented by the repeat count. Transitions in a repeated vector are only counted as one. For loops, statistics are counted on a vector basis, with a single pass through the loop, not on a cycle basis with loop-count passes through the loop. The user optionally can define the logic-1 and/or logic-0 states. Since the CREATE_STATISTICS command is in the TVF_BLOCK of the Vtran command file, the states are those used in the Target Vector File (the right-hand side of states defined in a STATE_TRANS command). The default values for logic-1 are: 1, U, H. The default values for logic-0 are: 0, D, L. The user optionally can define a time range for statistics gathering. Only transitions from the start through the end of the time range, inclusively, will be counted. The default is to collect statistics for the entire Target Vector File. Some examples of this statement's use are: CREATE_STATISTICS "F1stats.txt", DIN,DOUT,ISET; CREATE_STATISTICS "stats.txt", InSig1, InSig2, InSig3, InSig4, OutSig1,OutSig2; CREATE_STATISTICS "stats1.txt", InSig1 InSig2 OutSig1 OutSig2 BidirSig[3]; CREATE_STATISTICS "stats2.txt" InSig OutSig BidirSig[15] = logic0 S 0 L Z, logic 1 M 1 H ; 9) Added support for structural loops in the Verigy (HP/Agilent) 93000 output format. In previous versions, loops in the Original Vector File (OVF) had to be flattened if the Target Vector File (TVF) format was the 93k. In this release, these "structural" loops are supported. By default now, structural loops are enabled when the TVF format is 93K. To override this, the user can use the -expand_loops switch to flatten OVF loops. As with other TVF formats, the user can include structural loops in the TVF, or use the LoopThreshold feature. If one is selected, the other must be disabled. To use structural loops in the 93K vectors, the user just needs to not define the LOOP_THRESHOLD and LOOP_VECTOR_COUNT TVF_BLOCK parameters. To use the LoopThreshold feature, the user needs to define these parameters in the TVF_BLOCK and also include the -expand_loops switch in the OVF_BLOCK. To include structural loops in the 93K vectors, Vtran must count the number of vectors in each loop. This is required for the 93K SQPG command that defines the start of a loop. Vtran has a default buffer size of 80 for this count. If the OVF has structural loops with a larger number of vectors, there is a new TVF_BLOCK MAX_LOOP_VECTOR_COUNT command to increase the buffer size. Example: TVF_BLOCK BEGIN; tester_format HP93000 -auto_group DVC_FILE="strloops.dvc"; target_file "strloops.agk"; MAX_LOOP_VECTOR_COUNT = "100"; END; If Vtran encounters a structural loop with more vectors than its buffer size, it will generate an error message and terminate. 10) Added new parameter to Teradyne FLEX+ formatter which replaces the vm_vector header with a vector header. The flag is: TESTER_FORMAT Teradyne, -FLEX, -no_vm, . . . . ; 11) Added feature to TDL_91 writer that automatically maps numeric names to S_ prefix'ed name. For example, 12 would become S_12. RELEASE 8.1.2 ------------- 1) This release of Vtran supports different rise and fall edge times for NRZ signals. An NRZ signal can have two edge times defined, one for transitions to 0 or 1, and one for "other" transitions. This new feature allows for separate edge times to be specified for transitions to 0 and transitions to 1. In the PROC_BLOCK of the Vtran command file, the PINTYPE statement has been enhanced to add a new format, NRZ2. The statement syntax is: PINTYPE NRZ2 @ []; The rise and fall times are mandatory for this format. If the "other" time is not specified, it defaults to the same value as the rise time. The AUTO_ALIGN and TEMPLATE_CYCLIZATION features are affected, because they use the PINTYPE statement to calculate where to sample the state for a pin in a cycle. For the new NRZ2 format, they use the larger of the rise or fall edge times. Translations of print-on-change OVF formats that use the PINTYPE statement and translations to print-on-change TVF formats support this new feature. Two cycle-based OVF and TVF formats support this new feature: STIL and 93000. If a signal in an Original Vector File has NRZ2 waveforms, but the NRZ2 format is not supported by the Target Vector File, a warning message is generated, and the signal will be assigned NRZ format. The NRZ signal uses the rise time of the NRZ2 signal for its rise and fall edge time. RELEASE 8.1.1 ------------- 1) Enhanced VCD canned reader to greatly speed-up reading of VCD/EVCD files which contain a very large number of nodes. Also better handles some non-standard names. 2) This Vtran release includes a new, extended header for output files. The header is optional and generates a standard set of fields for Vtran Target Vector Files. To select the extended header, include the -EXTENDED_HEADER flag in the SIMULATOR or TESTER_FORMAT statement in the TVF_BLOCK of the Vtran command file. For example, simulator verilog_tb -EXTENDED_HEADER ; or tester_format Teradyne , -catalyst -auto_group, -EXTENDED_HEADER, SCANIN_DEFAULT = "0", PATTERN_NAME = "cam_runbist", MAX_LINE_LENGTH = "300" , TIME_STAMPS = "ON" , WR_TIMESET_FILE = "x.tim", TERMINATE = "halt" ; The extended header includes the following fields: - EnvInfo [optional] - Vtran Version # - Date and timestamp - Vtran command file name - Source file(s) - Output file(s) - File type [for some Tester Interfaces] - Design Name [for some Simulator Interfaces] - USER_INFO [optional] The user provides the optional USER_INFO data in the same SIMULATOR or TESTER_FORMAT statement with the -EXTENDED_HEADER flag. This field has the format: USER_INFO = "string with user information" The string inside the quotes may include newline characters: USER_INFO = "This is a multi-line string.\nThis is the second line." In this case, each line of the USER_INFO will be enclosed in the appropriate comment delimiters for the output format. This feature is supported by the following Simulator and Tester Interfaces: FTDL SPICE STIL TDL91 Toshiba TSTL2 TSSI TDS User-Defined Format Verilog Testbenches Verilog VCD/EVCD VHDL Testbenches WGL 93000 94000 Credence SWAV IMS ITS9K PCF LTX Teradyne Trillium 3) Fixed bug in Novas FSDB reader pertaining to large time values and performance improved. 4) Added an enhancement to the Template Cyclization feature. For cases where the user knows the exact times where a particular timeset or timesets should be selected, this information can be used by vtran to make the selection. The cyclization process then can be made more efficient by using time ranges in which a specific timeset should be selected. One example of a case where this feature can greatly improve efficiency is when the TIMESET blocks used with Template Cyclization have cycle lengths that differ from each other by orders of magnitude. The new feature adds a SELECT_RANGE statement to the TIMESET block. The format of this statement is: SELECT_RANGE start_time end_time; For example: SELECT_RANGE 200.0 10000.0; The start time value of the SELECT_RANGE statement is included in the time sequence in which the timeset should be selected. The end time of the SELECT_RANGE statement is excluded; it is the time at which normal template cyclization should resume, or at which a different SELECT_RANGE statement may start. The SELECT_RANGE statement is optional. A TIMESET block may have multiple SELECT_RANGE statements. Select ranges may be defined for multiple timesets, but must not overlap. Once a TIMESET is selected for a cycle based on the SELECT_RANGE statement criteria, the normal template cyclization checks of PRIMARY signals and IDENTIFIERs for all TIMESETs are skipped, i.e the SELECT_RANGE criteria, when met, overrides any other selection criteria. Here is an example of its use; timeset WFT2 cycle 1000; pintype nrz * @ 0; pintype stb * @ 500, 1000; pintype rz Sclk @ 0, 5; select_range 130000, 144000; select_range 144250, 169000; endtimeset RELEASE 8.1 ----------- 1) Added new Adventest canned readers for ReadBack of vtran-generated Advantest T3300 and T6600 tester files. The new Advantest Reader includes the following features: a. The Reader optionally will generate cycle-based timing and vectors. To select this feature, include the flag "-cycle" with the tabular_format command in the OVF_BLOCK of the Vtran command file. b. The Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that cycle-based output must be selected to enable the Scan option. c. The Reader, by default, will not flatten loops and repeated vectors if cycle-based output is selected. To disable this feature, include the flag "-expand_loops" and/or "-expand_reps" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that if cycle-based output is not selected, loops and repeated vectors will be flattened. The Reader supports the T3300 and T6600 tester models. To specify the T3300, include "T3300" after the tabular_format keyword in the OVF_BLOCK. To specify the T6600, use "T6600" instead. The orig_file statement in the OVF_BLOCK is the name of the Advantest vector file. If Scan vectors are included, the file name suffix is "asc"; if not, the file name suffix is "lpat". The aux_file statement in the OVF_BLOCK is used as a base name for the T3300 signals (.sock) and timing (.prog) files, or for the T6600 signals and timing file (.tdl). Example 1: ovf_block begin; orig_file "exp1.lpat"; {#### INPUT VECTOR FILE ####} aux_file "exp1"; {#### AUX TIMING FILE ####} tabular_format T3300 -cycle; {#### INPUT FORMAT ####} end; In this case, Vtran will read the Advantest T3300 source files, exp1.lpat, exp1.prog, and exp1.sock, and create cycle-based data for the Target files. Loops and repeated vectors will be available for inclusion in the Target files. Example 2: ovf_block begin; orig_file "exp1.asc"; {#### INPUT VECTOR FILE ####} aux_file "exp1"; {#### AUX TIMING FILE ####} tabular_format T6600 -cycle -scan -expand_loops; {#### INPUT FORMAT ####} end; In this case, Vtran will read the Advantest T6600 source files, exp1.asc and exp1.tdl, and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files, as will repeated vectors. Loops will be flattened. Example 3: ovf_block begin; orig_file "exp1.asc"; {#### INPUT VECTOR FILE ####} aux_file "exp1"; {#### AUX TIMING FILE ####} tabular_format T3300 -cycle -scan -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; In this case, Vtran will read the Advantest T3300 source files, exp1.asc, exp1.prog, and exp1.sock, and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files. Loops and repeated vectors will be flattened. 2) Added new interface to Q-Star QD-1011, QD-1011Hc24 and QD-1011HCLite IDDQ monitor product families which consists of monitors that easily support standard as well as advanced IDDQ test strategies as well as ISSQ test strategies. These monitors are integrated onto the loadboard and function in parallel with the normal DUT electronics. Vtran inserts special test vectors into WGL files that have been generated for IDDQ testing. The Q-Star interface is invoked using a special Q-Star block in the ovf_block of the vtran command file. The suntax is ([] means optional parameter): Q-Star Product = "QD1011 | QD1011HC24 | QD1011HCLite", [Keyword = "IDDQ_keyword",] { default is measureIDDQ } [Comtest = "Y | N",] [SF = "Y | N"], [Mode = "1 | 2",] [Sample = "1 | 4 | 16 | 256 | 1024",] [GRef = "N|S|D, value_1, [value_2]",] [VRef = "N|Y, [vec#, value_1 [,vec#, value_2]]",] [NoM = "N|Y, value",] [Readout = "N|A|S, [SV|DV,] [1,2,...N]",] [MemRead = "N|Y, [value]"] ; See the vtran Q-Star Application note for details. 3) Added new feature to FLEX writer to support "DFF = 1.1" in basic_timing and basic_timing_formula output timing files. Syntax to invoke this optional format is: TESTER_FORMAT Teradyne, -FLEX, DFF = "1.1", . . . ; 4) This Vtran release includes some changes to the LOOP_THRESHOLD and REPEAT_THRESHOLD features. If LOOP_THRESHOLD is enabled, unflattened Scan and structural loops still are not allowed, but structural and inserted repeats are allowed. For most Vtran Writers, REPEAT_THRESHOLD may be enabled when LOOP_THRESHOLD is enabled. The 93000 Writer does not allow both to be enabled. If LOOP_THRESHOLD is disabled, but REPEAT_THRESHOLD is enabled, unflattened Scan and structural (or inserted) repeats are allowed, but structural loops are not allowed. By default, structural repeats are disabled, when LOOP_THRESHOLD and/or REPEAT_THREHOLD is enabled. The user can enable structural repeats by including the -enb_reps flag with the TABULAR_FORMAT command in the OVF_BLOCK. Comments are handled differently in some cases. The new rules for comment placement are: - If a vector is not part of a repeated vector, its comment will appear where it is in the OVF vector file. - All comments that appear between OVF vectors that are collapsed into a repeated vector in the TVF vector file, will appear before the repeated vector. - A comment following the last OVF vector of a repeated vector sequence will appear after the TVF repeated vector. In addition, a new -BREAK_ON_COMMENTS flag has been added to the TESTER_FORMAT statement in the TVF_BLOCK. By default, comments are ignored when comparing OVF vectors for a TVF repeated vector. The timeset selection and the pin states are compared. If the -BREAK_ON_COMMENTS flag is present, a vector with a comment that is different from the previous vector will result in a mismatch, and the sequence of repeated vectors will be terminated. The syntax for this is: TESTER_FORMAT [tester_name], -BREAK_ON_COMMENTS, REPEAT_THRESHOLD = "10", . . . RELEASE 8.0.3 ------------- 1) Both the REPEAT_THRESHOLD and LOOP_THRESHOLD processes will now automatically expand any structural loops or repeats that might exist in the input vecctor file. The intended use of these processes is for compacting flat files (such as VCD files or flat WGL files) and therefore structural repeats and loops should not normally be present. 2) The LOOP_THRESHOLD feature support was added to the Agilent (Verigy) 93K tester. If this feature is enabled, then the REPEAT_THRESHOLD feature is automatically disabled - they cannot both be enabled at the same time on the 93K. This is also true for the Advantest writer. To select the LoopThreshold feature in the Writer, include the loop_threshold and loop_vector_count parameters in the TESTER_FORMAT command. For example: tvf_block begin; tester_format HP93000 loop_threshold="2", loop_vector_count="3", DVC_FILE="loops1.dvc"; {#### OUTPUT FORMAT ####} target_file "loops1.agk"; {#### OUTPUT VECTOR FILE ####} end; The loop_threshold parameter specifies the minimum repeat count for the loop; the loop_vector_count parameter specifies the number of vectors in the loop. Loops also are now supported by the HP93000 Reader; previously, all sequence programming (SQPG) commands were ignored. 3) REPEAT_THRESHOLD support was added to the WGL output formatter as well as unflattened scan support. To select the RepeatThreshold feature, include the repeat_threshold parameter in the SIMULATOR command. For example: tvf_block begin simulator WGL {#### OUTPUT FORMAT ####} REPEAT_THRESHOLD = "2", TARGET_FILE = "rpt2.wgl"; {#### OUTPUT VECTOR FILE ####} end; The repeat_threshold parameter specifies the minimum number of consecutive identical vectors that triggers a repeat. To select unflattened Scan in the WGL Writer, include the -scan flag in the tabular_format command for the Vtran Reader. This is supported only with the -cycle flag (cycle-based Reader output). RELEASE 8.0.2 ------------- 1) Added support for LOOP_THRESHOLD process which provides for discovery of loops in a manner similar to the existing RepeatThreshold feature for single-vector repeats. This feature is supported by the Advantest, Teradyne (excluding Catalyst), STIL, and WGL Writers. There are 2 parameters necessary for this feature; the Loop_Threshold defines the minimum number of times a loop must be repeated in order to be recognized, and the LOOP_VECTOR_COUNT specified the length of the loop (number of vectors in it). Both parameters must be specified. The syntax is: tvf_block begin; tester_format wgl LOOP_THRESHOLD = "2", LOOP_VECTOR_COUNT = "3", AddressElement = "Time" ; target_file "loops1dst.wgl"; {#### OUTPUT VECTOR FILE ####} end; 2) This release of Vtran adds unflattened Scan support to the Teradyne FLEX Writer and Reader. For the Writer to generate Scan constructs, the WGL or STIL reader should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -scan flag tells the readers to maintain the scan data separately, i.e. do not flatten it out. Since the FLEX format supports a scan data structure, you typically would not want the readers to flatten it out. Note that for the STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is to be scan data translated. Also, the number of scan bits specified in a single SHIFT operation in a STIL file should not exceed the length of the scan chain. The FLEX Writer generates data for 3-bit scan chains in Single or Dual mode. The default scan type is x2. If scan type x4, x8, or extended is required, the user can select the non-default value with the tester parameter SCAN_TYPE: TESTER_FORMAT teradyne -FLEX+, SCAN_TYPE = "x2" | "x4" | "x8" | "extended", The existing tester parameters DIGITAL_INST and PINMAP_WORKBOOK are used to specify values for the digital_inst and pinmap_workbook statements in the FLEX file header. DIGITAL_INST defaults to "hsd800". There is no default value for PINMAP_WORKBOOK, so if this parameter is not defined, the statement will not be generated. The FLEX Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. For example: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle -scan; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files with the default timing format, and create cycle-based data for the Target files. Unflattened Scan vectors will be available for inclusion in the Target files. The timing is defined in files exp1.tim_tsets.txt and exp1.tim_esets.txt. Note that cycle-based output must be selected to enable the Scan option. The FLEX Reader will synthesize scan chain information based on the list of names in the "scan_pins" statement. A scan chain name of the form "Chain" will be used, where is an integer, starting with 1. The Reader assumes the scan pins are grouped by scan chain, starting with the input pin for the first scan chain. Thus, the first two scan pins will be the input pin and the output pin for the first scan chain. 3) This release of Vtran adds Dual Mode support to the Teradyne FLEX Writer. By default, the FLEX Writer generates Single mode. The user can select Dual mode with the tester parameter -DUAL_MODE: TESTER_FORMAT teradyne -FLEX+, -DUAL_MODE, In Dual mode, vectors are grouped in pairs, and an opcode applies to both vectors in a pair. If there are single-row repeated vectors in the OVF, the Vtran Reader must be invoked with the "-expand_reps" switch to flatten the repeats. Because the vectors are grouped in pairs, there must be an even number of vectors in the FLEX file. If an odd number of vectors is generated from the OVF, an extra "pad" vector will be appended at the end. There must be an even number of parallel vectors between Scan vectors. If necessary, the FLEX Writer will insert a "pad" vector before the scan_setup vector, to enforce this constraint. There must be an even number of scan cycles in a Scan vector. If necessary, the FLEX Writer will add a "pad" cycle to enforce this constraint. For a scan-in pin, the SCANIN_DEFAULT state will be used for the first scan cycle. For a scan-out pin, an 'X' state will be used for the last scan cycle. For the "pad" vector at the end of the file or between Scan vectors, the following rules are used by default: - All pure-input signals which are not clocks will maintain their last state in the vector just prior to the padding vector. - All pure-outputs will be forced to X. - All clocks (RZ or RO) will be forced to their inactive states (0 for RZ and 1 for RO). - All bidirects will be forced to their last state in the vector just prior to the padding vector if it was an input; otherwise they will be forced to X. The user can override these default states with an optional padding file. The file name is specified with the tester parameter DUAL_MODE_PADDING_FILE: TESTER_FORMAT teradyne -FLEX+, -DUAL_MODE, DUAL_MODE_PADDING_FILE="myStates.pad", The padding file can be used to override the pad states for any or all pins in any or all timesets. The format of the file is described in Appendix D of the Vtran User's Guide, under the section heading "XMODE PADDING FILE". 4) The FLEX Reader was enhanced to support the multi-clock feature as generated by the Vtran Writer. The multi-clock feature is selected on a per-signal basis, and can be specified on a signal or group basis, with groups defined in the pinmap file. In the tsets or basic timing file, a multi-clock signal has an entry in the "Clock Period" field which normally is blank, and the "Setup" field is "clock" rather than "i/o". If the Clock Period is half the Cycle Period, the corresponding signal will be assigned RZ2X or RO2X format for cycle-based target files. If the Cycle Period divided by the Clock Period is a value other than 2, a warning message is generated and the Clock Period will be ignored. For event-based target files, any Cycle Period that is an integer multiple of the Clock Period is supported. 5) This release of Vtran adds Scan support to the WGL Writer. For the Writer to generate Scan constructs, the Vtran Reader should be invoked in the OVF_BLOCK with the -scan flag. For example: tabular_format STIL -cycle, -scan; The -scan flag tells the readers to maintain the scan data separately, i.e. do not flatten it out. Since the WGL format supports a scan data structure, you typically would not want the readers to flatten it out. The -cycle flag is required if the -scan flag is used. Note that for the STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is to be scan data translated. Also, the number of scan bits specified in a single SHIFT operation in a STIL file should not exceed the length of the scan chain. If the OVF format does not include scan cell data, the WGL Writer will synthesize scan cells for the WGL file. These cells have names of the form "cell", where starts with 1. WGL scanstates are synthesized from scan pin values in OVF scan vectors, using scan chain names to identify the cells for a given scanstate. The names of scanstates are of the form "", where pinDir is "I" or "O", and stateNum starts with 1. Scan states in the WGL file are defined in terms of the states in the scan cells, not on the edge pins. 6) Added the RepeatThreshold feature to the WGL Writer. This feature is the same as found in the tester interfaces and enables vtran to compress the WGL vector file when there are repeated vectors in it. For the Writer to generate repeated vectors that are not found in the OVF, the Vtran Writer should be invoked in the TVF_BLOCK with the RepeatThreshold parameter. For example: SIMULATOR WGL REPEAT_THRESHOLD = "nn"; where "nn" is the number of identical vectors that triggers a repeat. The default is for the RepeatThreshold feature to be disabled. 7) Added a new User Defined Format (UDF) parameter to include the timeset name on the vector line. This parameter is specified with the keyword $TSET in the UDF quoted expression. An example of its use would be: simulator UDF "$TSET > $states ; // %at" ; This would result in an output vector line that looked something like: SHK > 010000000000000L ; // 2700 Note the by using the ALIAS_TSET statements, one can map the timeset names to any other name (including numerics). RELEASE 8.0 ----------- 1) A new mode has been added to the Vtran TEMPLATE_CYCLIZATION feature. Initially, TEMPLATE_CYCLIZATION was provided to cyclize print-on-change vector data. The new mode supports the assignment of timesets to cyclized vectors. This new mode is selected with a new parameter, CYCLIZED_VECTORS, with a value of "ON" or "OFF". If this parameter is not specified, the default mode is print-on-change vector data (CYCLIZED_VECTORS = "OFF"; ). In the CYCLIZED_VECTORS mode, each TIMESET other than the DEFAULT must have an IDENTIFIER statement. If a non-default TIMESET does not have an IDENTIFIER statement, an error message is generated and Vtran exits. If no TIMESET is marked as the DEFAULT, the first TIMESET is the DEFAULT timeset; in this case, its IDENTIFIER field is optional. If a signal in a TIMESET has a -PRIMARY flag, a warning message is generated and the flag will be ignored. Only the logic expression in the IDENTIFIER statement is used for timeset matching. The CYCLIZED_VECTORS mode can be used for user-defined tabular formats, and also with Vtran canned readers that support the -cycle flag, including WGL and STIL files and several tester formats. Any timeset or timeplate or WaveformTable assignments in the source data will be replaced with the TIMESETS in the PROC_BLOCK. If a canned reader is used for the OVF, and the CYCLIZED_VECTORS mode is selected, the "-cycle" flag needs to be included in the TABULAR_FORMAT command in the OVF_BLOCK. Scan structures, loops, and repeated vectors need to be flattened. If these constructs are present in the OVF, the "-scan" flag must not be used, and the "-expand_loops" and "-expand_reps" flags must be used with the TABULAR_FORMAT command. Example: TEMPLATE_CYCLIZATION TERMINATE_ON_DEFAULTS = "100", MATCH_REPORT = "match_report.txt", MATCH_TRACE_START = 1, MATCH_TRACE_STOP = 100, CYCLIZED_VECTORS = "ON" ; TIMESET ts1 cycle 25.0; PINTYPE NRZ * @ 5.3; PINTYPE RZ Bclk @ 10.0, 15.5; PINTYPE STB * @ 24.0, 24.5; IDENTIFIER (Bdata[1]=0)&(Bdata[0]=1)&(BCtl=1); ENDTIMESET; TIMESET ts2 cycle 35.0; PINTYPE NRZ * @ 7.3; PINTYPE RZ Bclk @ 15.0, 25.5; PINTYPE STB * @ 34.0, 34.5; IDENTIFIER (Bdata[1]=0)&(Bdata[0]=1)&(BCtl=0); ENDTIMESET; TIMESET ts3 -DEFAULT cycle 45.0; PINTYPE NRZ * @ 7.3; PINTYPE RZ Aclk @ 15.0, 25.5; PINTYPE STB * @ 34.0, 34.5; ENDTIMESET; . . . 2) Added new parameter to tester (& STIL) writers which disables the REPEAT_THRESHOLD function for some initial (specified) time at the beginning of the vector set. The parameter is: DISABLE_REPEATS = "nn", An example of its use would be: SIMULATOR HP93K REPEAT_THRESHOLD = "12", DISABLE_REPEATS = "45000", . . . ; This parameter disables the REPEAT_THRESHOLD function at the beginning of the vector set from time 0 to time 45000 ns. The parameter has no effect if the REPEAT_THRESHOLD process in not enabled. 3) Added a new MASK_PINS mode which replaces (masks) a specified sequence of states on successive vectors of a signal in the input file with a specified sequence of states in the output file. The syntax is as follows: MASK_PINS pinlist @ SEQUENCE "", "" ; An example would be: MASK_PINS outpin7 @ SEQUENCE "000111", "00XX11" ; When translating an input stream of vectors, vtran will replace any sequence (consecutive vectors) of "000111" with the sequence "00XX11" in the output file. A few things to keep in mind when using the feature: - the states specified are pre-state_trans and any state_trans present will siltt be applied to the output sequence states. - if cycle_shift is being used on a signal then a mask_pins will not be effective on that signal - the sequence matching happens incrementally vector-by-vector and replacement of vectors proceeds forward all at once after a match is found. This means that some interesting results can arise - for example: MASK_PINS outpin4 @ SEQUENCE "111111", "111110" ; will result in a continuous sequence of 1's on the signal being replaced by a series of 111110111110111110...etc. 4) This release of Vtran provides a feature in the OVF_BLOCK which will merge multiple input files. This merging/concatenating occurs prior to the processing specified in the PROC_BLOCK. Both flat event-based files and cyclized files can be merged. The syntax for this merging adds a Merge_File block, which contains the optional INPUTS/OUTPUTS/BIDIRECTS statements and the associated input file name(s) for each file to be merged. This block replaces the single set of input file names for the non-merge case. The command file may have a global set of INPUTS/OUTPUTS/BIDIRECTS statements outside any Merge_File block, or it may have these statements in each Merge_File block. The statements are not allowed both places. The Merge_File block looks like: Merge_File [-CONCATENATE] [INPUTS/OUTPUTS/BIDIRECTS statements] orig_file = "fname"; [aux_file = "fname.aux";] [time_offset = nnn; ] end_Merge; For example: OVF_BLOCK begin tabular_format HP93000 ; Merge_file orig_file = "tap1.avc"; aux_file = "tap1.dvc"; end_Merge; Merge_file orig_file = "tap2.avc"; aux_file = "tap2.dvc"; end_Merge; Merge_file orig_file = "tap3.avc"; aux_file = "tap3.dvc"; end_Merge; The files to be merged must all be in the same format, for example one of the tester formats, WGL, STIL, VCD/EVCD, etc.. In addition, if the files have common signals then there must be no conflicts in the states on these signals at any given time. A conflict will result in a warning, with undefined state assigned. For outputs, X and Z states (or equivalent) are always overridden by any other state on the same signal in other files and will not result in a conflict warning. The same applies to input states Z and X (or equivalent). A couple of the older User-Programmed Readers (CADAT, Mentor List) use the state_trans command in the PROC_BLOCK of the Vtran command file. These map two-character states to a single-character state. The merge feature is not supported for input files in these formats. The concatenation of multiple files is supported in three ways. The first mechanism is to define the time_offset field in the Merge_File block, for all but the first file. The time_offset value is the end-of-cycle time of the last cycle in the preceding file. For example, to concatenate three files with a 100ns cycle time, if the last events in the first file are at times 2500ns, 2525ns, and 2575ns, the time_offset value for the second file would be "2600ns". If the last events in the second file are at times 3500ns, 3530ns, and 3560ns, the time_offset value for the third file would be "6200ns" (the last cycle in the second file starts at 3500ns + 2600ns, or 6100ns, and so ends at 6200ns). The second concatenation mechanism is to use the actual timestamps in the input files. For example, if the last event in the first file is at time 2575ns, and the first event in the second file is at time 2600ns or later, the vectors from the second file will follow the vectors from the first file. In this case, the time_offset field of the Merge_File block should not be defined. The third concatenation mechanism is only valid for cyclized vectors. If the -CONCATENATE switch is used, the time offset is calculated automatically for all but the first file, which uses a time offset of zero. The -CONCATENATE switch is only needed on the first Merge_file block. If it is present along with the optional time_offset field, a warning message is generated and the time_offset field is ignored. If the -CONCATENATE switch is used with event-based vectors, an error message is generated and Vtran terminates. When merging files with different signals, there may be time ranges in the final merged file for which some signals do not have a state defined in the original files. A signal that does not have a defined state at time zero will be set to X for the initial vectors, until a state is defined for it. If the final merged file has vectors beyond the last vector in an original file, and a signal is only defined in that original file, an input signal will maintain its last state, while an output signal will be set to X. When merging cyclized input files, the following restrictions apply: 1. A timeset must have the same name and cycle value in all input files. 2. If a signal is defined in more than one input file, its format and timing must be identical in the timesets in all input files. 3. If a vector at a given cycle time is defined in more than one input file, it must have the same timeset active in all input files. 4. Any SCAN, Shift, Loop, or Repeat constructs in the input files must be flattened by the Vtran Reader. 5) Added ReadBack support for the FLEX (and J750+) multi-clock generation (MCG) feature as generated by vtran. The multi-clock feature is selected on a per-signal basis, and can be specified on a signal or group basis, with groups defined in the pinmap file. In the tsets or basic timing file, a multi-clock signal has an entry in the "Clock Period" field which normally is blank, and the "Setup" field is "clock" rather than "i/o". If the Clock Period is half the Cycle Period, the corresponding signal will be assigned RZ2X or RO2X format. If the Cycle Period divided by the Clock Period is a value other than 2, a warning message is generated and the Clock Period will be ignored. 6) Added new output formatter to generate EVCD files. It is invoked as: SIMULATOR Verilog_evcd [params] ; The params supported include: VERSION = "1.6.0.1", TIMESCALE = "1 ns", MODULE = "TITLE", ENV_INFO = "", STATE_STRENGTH = "D->60, U->06, N->66, ... " See the file "evcdwriter.txt" in the download bundle for more information on using this writer. 7) Added MAX_REPEAT_COUNT parameter to STIL, Teradyne, Credence (SWAV) and Advantest tester writers. This parameter will cause a Repeat which exceeds the value to be split into 2 or more Repeats. The following default values for MAX_REPEAT_COUNT are used: Teradyne Catalyst: 32768 Teradyne J750: 65536 Teradyne J971/973: 2**28 - 1 Teradyne FLEX: 65536 Credence (SWAV): 256 Trillium: 128 STIL: no limit The format of the parameter is: MAX_REPEAT_COUNT = "nn" Example: tester_format Teradyne -Catalyst, MAX_REPEAT_COUNT="65000", TIME_STAMPS = "ON" , wr_timeset_file = "xxx.tim", TERMINATE = "halt" ; 8) Enhanced vtran's compound_logic_expression syntax to include the ability to specify a signal's state which is in a vector that is either before or after the current vector. The syntax for this is: Signal(+/-n). Here are some examples of its use: Pin1 & (Pin2(-3)||Pin3) = 1 true if Pin1=1 and (Pin2=1 3 vectors ago or Pin3 = 1) SIGA(+8) & SIGA(-8) = 1 true if SIGA was a 1 8 vectors prior to and after the current vector. Compound_logic_expression's are used in the following vtran statement types: MASK_PIN ADD_PIN BIDIRECTIONAL_CONTROL INSERT_REPEAT 9) Added new feature to all tester, STIL and WGL writers which allows the user to place values of specified environment variables in the header of the output file (as comments). The new paremeter syntax is: ENV_INFO = "env1, env2, env3, ...", This is an optional parameter to the TESTER_FORMAT or SIMULATOR command. The environment variables can be any that exist in the user's environment. An example would be the following: SIMUILATOR STIL, ENV_INFO = "PWD, HOME, MY_NAME, S3_ROOT", . . . ; This would result in a STIL output file which might look like this: // PWD: /home/beattle/temp/test_A // HOME: /home/beattle // MY_NAME: Bob Beattle // S3_ROOT: /home/vtran/linux64 STIL 1.0; . . . 10) Added new beta version of Advantest T3300 writer. This writer is an option to the T6600 and can be invoked with the following parameters: TESTER_FORMAT Advantest, -AUTO_GROUP, -T3300, { default is T6600 } REPEAT_THRESHOLD = "nn", { default is off } MAX_LINE_LENGTH = "nn", { default is 80 } ENV_INFO = "PWD, HOME, MY_NAME, S3_ROOT", { env var values in header } SIGNAL_FILE = "filename", { replace pin definition section with file contents } PATTERN_NAME = "patternname", { default is "DESIGN_PAT" } SCANIN_DEFAULT = "state", { see discussion on page D-2 } TIME_STAMPS = "ON" | "OFF", { default is ON } INPUT_NRZ1, BIDIR_NRZ1, CLOCK_RZX, { override pin formats-T6600 only } See the file "advwriter.txt" in the download bundle for more information on using this writer. 11) Fixed resource assignments on Agilent 93000 for SBC signal behaviors when using XMODE. 12) Fixed bug in several tester writers which arose when reading a STIL file where 2 consecutive WaveformTable statements occurred in the file. 13) The STIL reader had a number of memory and performance enhancements made. In the new implementation, Pattern blocks are not loaded into memory until they are needed by the translator. Thus, if there are multiple Pattern blocks in the file only those used are loaded and only one at a time. This can greatly reduce the memory requirements for translating large STIL files. 14) Added 2 new parameters to the ITS9K interace: PINDEF_TABLE = "pdefname", PATTERN_NAME = "patname", The PINDEF_TABLE parameter allows the user to change the default pindef_table name "Pin_Table" to any desired name. The PATTERN_NAME parameter changes the header in the .m9k vector file from the default: #pattern pat1, "patfilename", to #pattern PATTERN="patname", "patternfilename", RELEASE 7.7.1 ------------- 1) Added INSERT_REPEAT feature with the following syntax: INSERT_REPEAT nn @ CONDITION compound_logic_expr; or INSERT_REPEAT "pinlist" @ CONDITION compound_logic_expr; In the first form, a repeat of nn is added to any vector which satisfies the logic_expr condition. In the second form, the states on the pinlist (this would usually be a bus name), are taken as a binary value repeat count on all vectors for which logic_expr is true. The INSERT_REPEAT feature is intended to be used with print-on-change translations (such as VCD/EVCD) to tester formats, although it can be used with cycle-based vector translations also. There may be some cases where the interraction of REPEAT_THRESHOLD and INSERT_REPEAT result in the insertion being lost. 2) Added ADD_VTB_TEXT feature which allows a user to place custom text within a Verilog testbench file. The syntax is: ADD_VTB_TEXT "text" , Before|After, Module|DUTInst|Initial|Terminate|EndModule ; where one of the keywords separated by | for each of the 2 fields is selected. The text is surrounded by quotes, can be of arbitrary length and include newlines, spaces and tabs. The escape character '\' can also be used within the text string to allow quote characters to be included. Some examples are: ADD_VTB_TEXT "/* bla bla bla */" Before Module ; ADD_VTB_TEXT "/* bla \"bla\" bla */" Before Module ; ADD_VTB_TEXT " always /* system clock process */ #20 v_clk = 1; #10 v_clk = 0; end" before initial ; The text string will be placed either Before or After the testbench item identified. The Terminate location corresponds to the terminate_run parameter in the testbench which defaults to $stop. 3) Enhanced the MASK_PINS and CYCLE_SHIFT commands by removing any restrictions on the vector range to which these processes can be applied. Previously, the range was +/- 100 vectors. Note that these extensions do not include the case where the NOT conditioner is used. 4) Added support for specifying timing (cycle time and edge timing) using parameter names for the FLEX and J750 tester files. The new syntax for identifying parameter names to be associated with timing values is to follow the time value with a quoted name in the vtran command file. For example: CYCLE = 100 "cyc_freq" ; PINTYPE NRZ pin1, pin2, pin3 @ 12 "td_in1" ; PINTYPE RZ clkA @ 22 "ck_rise", 44 "ck_fall" ; These optional parameter names will then appear in the esets/tsets or basic_timing files instead of the constant values only if a -use_timing_params flag is present in the tester_format statement. For example; TESTER_FORMAT Teradyne, -FLEX, -use_timing_params, wr_timeset_file = "base_name", . . . ; The syntax for defining the parameter names in the vtran command file will also be used for other tester formats in the future. Note that currently vtran does not generate an ACSpecs sheet for the FLEX or J750+ test programs. This is left to the user to specify so that he can define the values of these parameter names using any equation he wishes. 5) In conjunction with adding support for timing parameters in the FLEX and J750+ timing files, the FLEX and J750 reader was enhanced to handle reading these timing files with parameter names. As part of this support, the FLEX and J750 readers will also read an ACSpecs file (which must be present id parameter names are used in the timing files). Since the vtran FLEX and J750 writers do not generate this ACSpecs file, it must be supplied by the user. When using the FLEX and J750+ readers, the following syntax is used (this is for a FLEX example with eset/tset timing): ovf_block begin TABULAR_FORMAT FLEX -cycle ; ORIG_FILE "design1.flex"; AUX_FILE "design1" ; end; The reader will use the "design1" base name to look for the following files: design1_tsets.txt design1_esets.txt design1_pinmap.txt design1_acspecs.txt Signal group names defined in the _pinmap.txt file can be used in the other files. If the _tsets.txt and/or the _esets.txt files use any parameter names (in place of canstant numbers), then the _acspecs.txt file must be present also since it defines the values the parameter names. Furthermore, since the ACSpecs file can have multiple categories and selectors in it, the user can optionally specify these also using -specs_category and -specs_selector options as follows: TABULAR_FORMAT FLEX -cycle, -SPECS_CATEGORY=Cat5 -SPECS_SELECTOR=Min ; The value of the -specs_category must be one of the named categories in the ACSpecs file, and the -spec_selector value must be either Min, Typ or Max. If no -spec_category is specified then the first one in the file is used and if no _spec_selector is specified then Typ is used. See the README file in the INTERFACES/TEST_READ_MAIN directory. RELEASE 7.7 ----------- 1) Added new flag which will cause vtran to terminate when serious warnings occur. Normally, Warnings do not cause vtran to terminate. The flag can be set either from the command line as: vtran -terminate_on_warnings . . . . or from inside the vtran command file using the statement: TERMINATE_ON_WARNINGS; which is placed in the OVF_BLOCK. 2) Modified ITS9000 inteface to include support for HEADER and fix timing file. 3) Enhanced the MASK_PINS statement to allow for transition masking start/stop to be applied +/- 100 vectors from the transition event. Currently, transition masking can be applied -1 to +n (n >=0) vectors from the event. The syntax for transition masking is: MASK_PINS [mask_character=c] pinlist @ TRANSITION a->b [,start][,end]; or MASK_PINS [mask_character=c] pinlist @ CONTROL_TRANSITION control_pin a->b [,start][,end]; Where c is any masking state to be aplied, a and b indicate the specific state transition which defines the masking event, start and end are cycle or vector counts from the vector in which the transition event occurs. This enhancement removes the restriction that start can only be -1 or 0 and would allow it to be negative (or positive) by as much as (-)100 indicating that the vector masking would begin up to 100 vectors prior to (or after) the transition event. Likewise for the end value, it can range from -100 to 100 as long as it is >= the start value. Note that multiple MASK_PINS can be sepcified for the same pins if there are multiple transitions to trigger from. Also, either a, b or both can be the * wildcard (any) state so for example 1->*, *->0 or *->* are legal. 4) Added a new feature to cause the states on specific signals for cyclized vectors in the output file (typically this would be testers or WGL/STIL format) to be shifted by n vectors, either forward or backwards, relative to their states in the input vector stream. The limits on n would be +/- 100 vectors for shifting. The syntax is: CYCLE_SHIFT [fill_character=c] pinlist @ n ; Where n can be in the range of +/- 100 cycles. When shifting forward (n > 0), the n vectors starting at vector 1 will have their states set to the fill_character (default is X). When shifting backwards (n < 0), the last n vectors will have their states also set to the fill_character. The CYCLE_SHIFT feature is a global process that will be applied to all signals in the pinlist across all vectors in the file. 5) Added support for MultipleClock Generation (MCG) on FLEX output timing. This is accomplished by using the standard PINTYPE RZ or RO, setting the leading and falling edges as they should be for the multi-clock. And then using the following TESTER_FORMAT parameter: MCG = "signame, cycle [tset]", Multiple MCG parameters can be specified, even for the same signal as long as an optional tset is specified for each one. If no tset is specified then the MCG is applied to all tsets. The cycle parameter specifies the clock period of the clock and must be an integer divisor of the timeset cycle time. For example, if a 4X clock is needed where the basic cycle time is 100 ns, we would use: PROC_BLOCK . . . CYCLE 100 ; PINTYPE RZ clksig @ 20, 25 ; TVF_BLOCK . . . TESTER_FORMAT Teradyne, -FLEX, MCG = "clksig, 25", 6) Added new beta version of Novas FSDB canned reader. This canned reader can read simulation data from an FSDB binary file with VCD or EVCD type data. It is invoked as follows: SCRIPT_FORMAT novas_fsdb [params]; or SCRIPT_FORMAT novas_fsdb_f [params]; (or novas_fsdb_fq) This canned reader is initially available on the Solaris-64, Linux-32 and Linux-64 bit platforms. See the file Vtran User's Guide for more information on using this canned reader. 7) Added new beta version of Advantest T6600 writer. This writer can be invoked with the following parameters: TESTER_FORMAT Advantest, -AUTO_GROUP, REPEAT_THRESHOLD = "nn", { default is off } MAX_LINE_LENGTH = "nn", { default is 80 } SIGNAL_FILE = "filename", { replace pin definition section with file contents } PATTERN_NAME = "patternname", { default is "DESIGN_PAT" } SCANIN_DEFAULT = "state", { see discussion on page D-2 } TIME_STAMPS = "ON" | "OFF", { default is ON } INPUT_NRZ1, BIDIR_NRZ1, CLOCK_RZX, { override pin formats-T6600 only } See the file "advwriter.txt" in the download bundle for more information on using this writer. 3) Added support for SBC pintype format in Agilent 93K writer and reader. PRE-RELEASE 7.6.4 --------------- 1) Made HP93000 and AGILENT93000 (and 83000) equivalent. 2) Fixed bug in FORCE_SEQUENTIAL_BUSSES, default was using only first bus order for all busses instead of each one individually. Note that there are some restrictions on using this command - it cannot be used if DELETE_PINS or INPUTS/OUTPUTS/BIDIRECTS are used in the TVF_BLOCK. 3) Added new parameter option to STIL output formatter: TESTER_FORMAT STIL -ALT_BIDIR_WFM, .... ; The default waveform for bidirectional signals in the STIL file typically looks like: DDRC_B12 { 10ZN { '5ns' U/D/Z/N; } } DDRC_B12 { HLXT { '0ns' X; '72ns' H/L/X/T; } } with this optional flag set, the waveform becomes: DDRC_B12 { 10ZN { '5ns' U/D/Z/N; } } DDRC_B12 { HLXT { '0ns' Z; '0ns' X; '72ns' H/L/X/T; } } This option provides for a more conservative waveform on bidirectional signals and ensures stricter conformance with the semantics of the language. 4) Added new parameter option to STIL output formatter: TESTER_FORMAT STIL -NO_SIGNALGROUPS, .... ; This option forces vtran to only use the signal and bus names for Vector statements, and not to declare any SignalGroups. 5) Added new cycle-based ReadBack options to the following tester ReadBack modules: SWAV CATALYST J750 J750+ FLEX AGILENT93000 Previously, the ReadBack modules always flattened-out the test vectors to an event stream, which could then be used for generating a testbench for verification. With this new option, the vectors generated by vtran for these testers can be read back for cycle-based translations; i.e. to other test formats, WGL or STIL. These also support repeats and loops where appropriate. These new features are invoked using the -cycle, -scan, -enb_reps and -enb_loops flags. For example: TABULAR_FORMAT J750 -cycle -scan ; will read a J750 test program generated by vtran for translation to any cycle-based (tester) format which supports scan. If the -scan flag is removed then the reader will flatten the scan data. 6) Added a new feature to the ADD_PIN statement with the LINK_TIMING flag which allows you to tie the timing of a newly-defined signal to that of another existing signal. The format is: ADD_PIN newpin input LINK_TIMING oldpin = 1; This defines a new signal named newpin with a constant state of 1 and whose timing is the same as oldpin. 7) Added a command line option which performs a verification of the vtran command file for syntax and logical errors without actually doing any vector processing. When processing very large vector files, if there is an error (typo or semantic error) in the PROC_BLOCK or TVF_BLOCK of the vtran command file, it will not detect this error until the entire input file has been read-in. This may waste significant time. The -check flag can be used on the command line to perform a verification run thru the command file without doing any significant vector processing to check for such errors. The syntax is: vtran -check test.cmd 8) When vtran is running, it normally creates a number of temporary files in the local directory as it reads and processes the vector file. In some cases, it may be desirable to have all temporary files be created in an alternate directory. This can now be accomplished with the new command line option -tmpdir. The syntax is: vtran -tmpdir /space/tmp test.cmd Note that one could also use an environment variable here. If S3 was an environment variable set to /space/tmp then one could use: vtran -tmpdir $S3 test.cmd 9) The WGL output format has been enhanced to support structural repeats and loops. To enable this feature, the -enb_reps and/or -enb_loops options must be included in the TABULAR_FORMAT reader invocation. For example: TABULAR_FORMAT STIL -cycle -enb_repeats -enb_loops; . . . SIMULATOR WGL ... ; will structurally translate any repeats or loops in the STIL file to the WGL file. Without those flags, they would be expanded during the translation. 10) The canned reader for TDL_91 format has been enhanced to handle structural repeats and loops. Previously the TDL_91 canned reader would always expand repeats and loops in the TDL_91 file durung translations. These repeats and loops can now be maintained structurally by using the -enb_reps and -enb_loops flags. For example: TABULAR_FORMAT tdl_91 -cycle -enb_reps -enb_loops ; RELEASE 7.6 ------------ 1) Enhanced STIL output formatter by adding 2 new optional parameters: TESTER_FORMAT STIL, .... NAMED_GROUP = "group_name, pin_list", PATTERN_FILE = "file_name", The NAMED_GROUP parameter can be specified multiple times to define different SignalGroups for the STIL output file - the first parameter in the quoted parameter list is the name of the SignalGroup. The pin_list parameter is a space-separated list of pin names. This new optional parameter is intended to replace the INPUT_GROUPS and OUTPUT_GROUPS parameter options. The PATTERN_FILE optional parameter provides a way to direct vtran to place the Pattern block in a separate file from the main STIL file, which contains everything else. If the file_name has a .gz suffix on it then the file write is piped thru the gzip utility. The main STIL file will contain an Include statement which brings the Pattern block file into the main STIL file. 2) Fixed bug in VHDL writer to handle the case when translating vectors having busses where the bus signals are not listed in numeric order. 3) Added support for SCANIN_DEFAULT parameter to WGL output formatter and all testbench formatters (Verilog, VHDL, nanosim, ..). 4) Added a new TVF_BLOCK parameter: FORCE_SEQUENTIAL_BUSSES [+ | -]; This new parameter is intended primarily to handle dealing with input files (WGL files from Cadence Encounter Test in particular) where there are busses defined, but the order of the bit indexes is not sequential. Adding this parameter to the TVF_BLOCK causes vtran to re-order the bits of any busses to match the order indicated. The order indicated is determined as follows: FORCE_SEQUENTIAL_BUSSES ; The bus bit order is determined by checking is the first bit is smaller or larger than the last bit and then enforcing that order. FORCE_SEQUENTIAL_BUSSES - ; Forces all busses to be listed indeces from MSB-to-LSB order. FORCE_SEQUENTIAL_BUSSES + ; Forces all busses to be listed indeces from LSB-to-MSB order. Although the parameter is intended primarily to handle non-sequential bus indeces, it can also be used with either the + or - option to force all busses to a particular ordering. WGL-to-Verilog testbench translations in particular need to have this parameter specified if the bus indexes are not sequential. Note that if the the elements of a bus are not defined contiguously (with no non-bus signals between them) then the only way to solve this problem is to re-list the all signals in the TVF_BLOCK with the bus signals listed together. 5) Upgraded Agilent (HP) 93000 interface to handle PinScale capabilities. New PINSCALE parameter can be used to specify the number of waveforms available. The syntax is: TESTER_FORMAT HP93000, . . . PINSCALE = "nnn" . . . ; where nnn = 64, 96, 128, 160, 192, 224 or 256. 6) Fixed bug in warning messages generated when using the -warnings flag with the ALIGN_TO_CYCLE process. Warnings were incorrectly being generated previously. 7) Modified the Agilent 93000 XMODE dvc file and dvc file generated for PinScale to correctly assign drive/receive resources and to correctly handle changing I/O directions on bidirectional pins. 8) Added 2 new parameters to the Agilent (HP) 93000 interface: -MINIMIZE_AVC { generates a minimized AVC file } -GENERATE_X1_TIMING { generates X1 timing also for XMODE } Also added RO2X and RZ2X support for XMODE timing. 9) Modified handling of large files (>2GB) to fix bug in STIL canned reader. RELEASE 7.5.4 ------------- 1) Compiled 32-bit versions of vtran to handle file sizes > 2GB. 2) Added -ALT_CLK_FORMAT1 parameter option to STIL formatter. For clocks, the default format for WFCs in the WaveformTable is: clk { 10 { '0.0ns' D; '22.0ns' U/D; '44.0ns' D; } } clk { ZN { '0.0ns' ZN; } } if the -ALT_CLK_FORMAT1 flag is present with the SIMULATOR STIL statement then the format becomes: clk { 10ZN { '0.0ns' D; '22.0ns' U/D/Z/N; '44.0ns' D; } } 3) Modified hp93K XMODE to default to NOFNZ for outputs in dvc file. Added parameter -DVC_OUTPUTS_FNZ to add FNZ event back in (this was the old default). 4) Modified TDL_91 output to add "NULL" pin name to the PATH statement when there is only a single scan pin for the chain. For example: PATH SCAN0, VAR=(pin_si, NULL), ... 5) Fixed bug in STIL->Catalyst translation path for case when there are more than one scan chain sharing the same scan pin. 6) Modified VCD/EVCD canned reader to correctly handle an EVCD variant (non-standard) which is apparently generated by ncsim. 7) Modified the TDL_91 canned reader to correctly handle the case of quoted bus names for bidirectional signals. Also fixed bug in handling of multiple scan pins. 8) Fixed bug in WGL reader for case with scanchain having no scan cells in it. 9) Fixed bug in WGL reader for case of multiple timeplates with many vectors and many switches between timesets. In this case an error accumulation was causing failure. 10) Enhanced support for STIL 1450.1 syntax in support of ActiveScanChain statements in STIL file. This particularly impacted STIL->TDL_91 translations where scan chain names are used. 11) The STIL reader was modified to maintain quotes around Timing WaveformTable names and ScanChain names if they are present in the file. In the past, these quotes were removed by the reader. In order to resort to the previous behavior, an optional flag was added: -UNQUOTE_NAMES which can be included in the TABULAR_FORMAT statement. For example: TABULAR_FORMAT STIL -cycle -scan -unquote_names ; Would cause the reader to behave as in previous releases whare all names have the quotes removed. Note that this does not apply to signal names, which always have the quotes removed. 12) J750 Reader was modified to support reading of basic_timing and basic_timing with formulas now generated by vtran. 13) Enhanced J750, Catalyst, and SWAV Readers to optionally generate cycle-based output, unflattened Scan, unflattened loops and repeated vectors. The inclusion of the -cycle flag when invoking these readers (as well as other flags) tells the reader that it should maintain the cycle-based data. Examples of using the canned readers for cycle-based translations with the optional parameters would be: TABULAR_FORMAT J750 -cycle ; TABULAR_FORMAT J750 -cycle -scan -expand_loops ; TABULAR_FORMAT SWAV -cycle -scan -expand_reps; For details and examples in the README file contained in the directory INTERFACES/TEST_READ_MAIN. RELEASE 7.5.1 ------------- 1) Added RX2x and RO2x support for Agilent 93000 DVC file. 2) Added parameters to WGL reader: -LOOP1V2REP translates 1 vector loops to repeat MAX_REPEAT_COUNT="nn" sets maximum repeat count (splits it into multiple repeats if too large). Example of usage: TABULAR_FORMAT WGL. -cycle, -scan, -loop1v2rep, max_repeat_count = "32768" ; 3) Added new MASK_PINS option: MASK_PINS pinlist @ last_vector; Example of usage: MASK_PINS all_outputs @ last_vector; 4) Fixed Agilent 93000 handling of scan chains where either the scanin or scanout is a Pseudo (internal node). 5) Fixed bug in Agilent 93000: mapping 'C' and 'S' to 'c' occurs only if -ENABLE_CAPTURE flag is set. 6) Added new optional parameters to Agilent 93000 format: SCAN_TEMPLATE_NAME = "name" SCAN_FRAME_NAME = "name" The SCAN_FRAME names will have scan# appended for each one. 7) Enhanced the TIME_STAMPS parameter for Teradyne tester interfaces to include a new option: TIME_STAMPS = "ON" | "OFF" | "ON_VC" ; The "ON_VC" option adds V:# and C:# vector and cycle numbers as comments to the end of the timestamp. 8) Fixed a bug in Catalyst header so signal name columns now align with vector data columns. 9) Added -NOSPACE flag option to Teradyne tester output formats. Usage: TESTER_FORMAT teradyne, -J750, -nospace, ... ; 10) Enhanced the J750+ timing file to include the timing file format options: -BASIC_TIMING and -BASIC_TIMING_FORMULAS Specifying one of these flags with the J750+ format will generate a timing file in a format identical to what the options generate for the FLEX+ tester. RELEASE 7.5 ----------- 1) Added several optional parameters to Teradyne FLEX+ output option: TIMESET_BASE_NAME = "prefix", { pre-pends prefix to timeset names } -BASIC_TIMING, { causes a single timing file to be created (bascic_ts.txt) which contains all timing information from tsets.txt and esets.txt files } -BASIC_TIMING_FORMULAS, { same as -BASIC_TIMING except that all edge timing numbers are expressed as formulas } Note that the RESOLUTION statement can be used to increase the significant decimal places in the timing numbers. 2) Fixed bug in SWAV output format - added cyN identifier along with tsN on each vector whenever a new timeset has a period different than the last one. 3) Added support for multiple timesets and scan data in TDL_91 canned reader. When using this canned reader for cycle-based translations, specify: TABULAR_FORMAT tdl_91 -cycle, -scan ; 4) Fixed alignment of signal name comments in J750 & J750+ formats so they correspond with the signal data columns. 5) Fixed time stamp problem related to nested loops in STIL files and also to loops which have changing timesets within them. 6) Added -ONE_LOOP_LEVEL flag for reading STIL & WGL files. This flag will limit to one level loops it finds in STIL/WGL files - any inner loops get expanded. The syntax is: TABULAR_FORMAT STIL -cycle -scan -one_loop_level ; or TABULAR_FORMAT WGL -cycle -scan -one_loop_level ; 7) STIL Reader: fixed handling of Loops with a count of 1 in STIL files. Also enhanced to handle spaces in WFC lists. 8) Added option to specify TDL_VERSION parameter for TI TDL_91 output format. The syntax is: SIMULATOR TDL_91 . . . TDL_VERSION = "ASIC_TDL_91 6.1", . . . ; 9) Modofied UDF output formatter to print long and double time stamps. 10) Modified STIL reader to correctly handle the Default DefaultState for input and output signals. Previously, this was set to the '?' event character. The correct behavior (per 1450-1999) is 'Z' for inputs and 'X' for outputs which it now follows. NOTE that this may require some modifications to STATE_TRANS mappings used previously. 11) Fixed bug in Verilog_tb_readmem output format for handling a single output signal. 12) In STIL reader, added support for multiple PatternExecs with PATTERNEXEC parameter used to select which one to translate. The syntax is: TABULAR_FORMAT stil -cycle, -scan, PATTERNEXEC="XYZ" ; If no PatternExec is specified in a STIL file which has multiple Patternexecs, the one (if any) which has no name will be used or if they all have names, then the last one in the file willl be used in the translation. 13) Some bug fixes and enhancements to the Agilent 93000 XMODE support were made. The following parameter was added: -DVC_OUTPUTS_NOFNZ which inhibits pure outputs from getting the d1:FNZ as first event. 14) Modified the handling of undefined WaveformCharacters used in assignment statements (Vector, Constant) in STIL files. In the past, an undefined WFC assigned to a Signal was simply used directly (with no mapping) as the new state character for the Signal. No error was generated. Under the new behavior, this will generated an error and processing will terminate, as it should since this is a syntax error. A flag ( -Allow_Undef_WFC) can, however, override this new behavior if present in the TABULAR_FORMAT stil... statement: TABULAR_FORMAT stil -cycle, -scan, -Allow_Undef_WFC ; 15) Fixed bug in PCF canned reader when large number of signals. RELEASE 7.1.6 ------------- 1) Fixed bug in Catalyst timing files - clocks on bidirectional signals were not being handled correctly in all cases. 2) Enhanced cycle-matching of TEMPLATE_CYCLIZATION for NRZ signals; these can now be used as -PRIMARY @ 0 . 3) Increased number of MASK_PINS allowed to 2048 in a vtran command file. 4) Added TESTER_FORMAT Teradyne -J750+ ... ; This is similar to the -J750 except that the timing files have been updated. 5) Fixed some bugs in Agilent 93000 XMODE files - timing and DDC. RELEASE 7.1.3 ------------- 1) Added -bidir_format1 flag for WGL output format which removes the return to the Z state on bidirectional signals in the WGL timeplates. Format: SIMULATOR wgl -bidir_format1, ... ; 2) Added basic support for Trillium testers (Arraymaster/Deltamaster). This is a pre-release version which does not support generation of timing information. It creates a single vector file with the HEADER, FORMAT and DATA_PATTERN sections. This output vector file should be named with a .pat suffix in the command file. The interface does support Repeat vectors, but not loops (automatically flattens these out) or scan data (have vtran flatten them out when translating WGL or STIL files by not including the -scan flag). The following syntax is used to specify this output format, along with the supported parameters: TESTER_FORMAT trillium, -auto_group, repeat_threshold = "nn", { default is off } max_line_length = "nn", { default is 1024 } pattern_name = "patternname", { default is "design" } dpm_start = "mm", { DPM start address } time_stamps = "OFF", { default is ON } ; 3) Added basic support for Teradyne FLEX+ tester format. This version supports repeat structures, but not loop structures or scan data. When translating from a WGL or STIL file, do not specify the -scan flag so the vtran reader will flatten any scan data. Also, this version supports only single mode for the FLEX+ tester. The following files are generated by this interface: filename.atp the vector pattern file filename_esets.txt the esets (edge sets) filename_tsets.txt the tsets (timing sets) filename_pinmap.txt the pinmap file The following syntax is used to invoke this formatter, and the listed parameters are supported: SIMULATOR teradyne -FLEX+, -auto_group, repeat_threshold = "nn", { default is off } max_line_length = "nn", { default is 1024 } pattern_name = "patternname", { default is empty } wr_timeset_file = "filename", { used for esets, tsets & pinmap } digital_inst = "name", { default = "hsd800" } pinmap_workbook = "name", { default - none } ; 4) Added new MASK_PINS option which causes the mask to be applied everywhere EXCEPT the region defined by the CONDITION or TRANSITION. This is exactly opposite to the masking behavior for the normal MASK_PINS. The syntax for the various forms of MASK_PINS is: MASK_PINS [mask_character=C] pinlist @ NOT t1, t2 [-CYCLE]; MASK_PINS [mask_character=C] pinlist @ NOT CONDITION logic_expr; MASK_PINS [mask_character=C] pinlist @ NOT TRANSITION a->b [n1, [n2]]; MASK_PINS [mask_character=C] pinlist @ NOT CONTROL_TRANSITION ctlpin, a->b [n1, [n2]]; This form of masking is very useful for situations where it is easier to define the vector regions or conditions where you do not want masking to take place, rather than where you do want to mask. 5) Fixed bug in .dvc files for Agilent 93000 XMODE. 6) Fixed bug in STIL reader when handling quoted Macro & Procedure names which have bus subscripts as part of name. RELEASE 7.1 ----------- 1) Modified RESOLUTION statement to extend allowable resolutions of .0001, .00001 and .000001 - this gets resolution down to FS. 2) Added -SEPARATE_BIDIRECTS parameter to WGL output in SIMULATOR command: SIMULATOR WGL -SEPARATE_BIDIRECTS, ... ; This will cause the output WGL file to list the bidirectional signals in the form: pattern group_all( .. bidir1:I, bidir1:0, ... ) instead of pattern group_all( .. bidir1, ... ) which is the default. This also has a minor affect on how the vector data is listed - it adds a space between input and output data. 3) Added an optional ALIAS_TSET command to the TVF_BLOCK of the vtran command file. This command can be used to change the names of Timing Sets between the input file (usually WGL or STIL) and the output file. The syntax is: ALIAS_TSET ovfts1 = tvfts1, ovfts2 = tvfts2, ... ; where ovfts1 is the name of the timing set in the input file, and tvfts1 is the new name to appear in the output vector file. An example might be: ALIAS_TSET _default_WFT_ = tset1; 4) Added -edge_format1 flag option to WGL output formatter. This flag directs vtran to use a slightly modified timing format for edge strobes on output signals. For an output signal (sig1) whose timing is defined as pintype stb sig1 @ 95; The default format for edge strobes in the WGL timing block is: sig1 := output [0PS:X, 95NS:Q'edge]; if the -edge_format1 flag is present, then the output looks like: sig1 := output [0PS:X, 95NS:Q'edge, 100NS:X]; where the 100NS is the cycle time (period) for the timeset. The syntax for using this flag is: SIMULATOR WGL -edge_format1, ... ; 5) Added support for generating a timing file for the J973 test format. This file is generated when the WR_TIMESET_FILE parameter is specified: TESTER_FORMAT teradyne, -J973, . . . PATGEN = "single_tg", WR_TIMESET_FILE = "Xj973.waveadr", ; The PATGEN parameter is part of this support and can be used to specify the "patgen" parameter in the .wavadr timing file. 6) Added a canned reader for the Teradyne J973 tester format. The application for this reader is to allow a vtran-generated J973 test program file to be read back by vtran for the purpose of generating a Verilog or VHDL testbench file for verifying, thru re-simulation, the correctness of the test program. As such, the reader only supports the subset of J973 commands and features used by vtran in the generation process. Also, translations from this tester format are only supported to simulation formats which use flat event-based simulation data. Because of this, the -CYCLE and -SCAN flags are ignored. When invoking the reader, the following syntax should be used in the OVF_BLOCK: TABULAR_FORMAT J973 ; ORIG_FILE = "file.lvmadr"; AUX_FILE = "file.waveadr"; The reader takes 2 files: the ORIG_FILE is the J973 lvmadr vector file, and the AUX_FILE is the timing file generated by vtran during translation. The J973 reader requires that both files be available. An example command file for a J973->Verilog testbench translation might look like: ovf_block begin tabular_format J973; orig_file = "micro_chip.lvmadr"; aux_file = "micro_chip.waveadr"; end proc_block begin state_trans 'H'->'1', 'L'->'0'; state_trans inputs 'X'->'Z'; disable_vector_filter; end tvf_block begin target_file = "micro_chip.v"; simulator verilog_tb timescale = "1ps/1ps" ; end; end The primary benefit of this new reader is the ability to directly verify the correctness of a vtran-generated test program for the Teradyne J973 tester thru direct generation of a simulation testbench file. This essentially closes the loop from a verification perspective, and provides a high degree of confidence for a working test program. Additional readers for other vtran-supported tester formats are planned for the near future. 7) Added XMODE option to Agilent 93000 test output format. This feature provides for a way to gain significant improvements in tester speed, and/or in memory compaction of vector data by combining multiple device cycles into a single tester cycle. The specification describing the flow and parameters associated with vtran's support for generating Agilent 93000 files which are XMODE-compatible can be found in the XMODE.spec document under the INTERFACES/HP93000 directory and in the Vtran User's Guide for Release 7.1 . 8) Enhanced VCD/EVCD canned reader to handle a wider range of format syntax generated by different tools. 9) Further enhanced WGL canned reader to speed-up processing of scanstate data. This enhancement can result in 2X to 8X improvement in speed when reading large WGL files with large amounts of scan data. RELEASE 7.0 -------------- 0) Modified behavior of -scan_pad command line parameter and SCANIN_DEFAULT parameter used in TESTER_FORMAT and SIMULATOR commands. Both of these were modified to accept 2 characters as arguements. If only one character is specified with either, then the behavior is identical to its behavior in vtran Release 6.6 - i.e. the state character is used as the scan-in pad character for short scan chains when reading WGL files and the scan-out padding state character is calculated from this scan-in pad character and the number of inversions thru the scan chain. If, however, 2 characters as specified, for example: vtran -scan_pad 0X cmd_file or TESTER_FORMAT SWAV , SCANIN_DEFAULT = "0X", ... ; then the second character becomes the scan-out character used for padding scan-out data on short scan chains in WGL files. This second state character overrides any calculated value and is forced as the scan-out pad character state for short chains. 1) Substantial up-grade of STIL reader to provide support for many of the new 1450.1 features which are anticipated for use in the near future: - Variables: Integer and SignalVariables - Expressions: Logical, Integer and Boolean - Scan Shift with overload (immediate) data. - LoopData with passed and overload (immediate) data - MergedScan() - Scan Cell names with bus notation - Scan Chain names and usage in other chains - If / Else constructs - While construct - ScanChainGroups - ParallelPatList with LockStep - AllowInterleave - ActiveScanChain In addition to these, other more subtle improvements were made including the treatment of input vs. output state persistance on bidirectional signals, support for passing scan data thru multiple-levels of Macro/Procedure calls, and the use of SignalVariables for specifying scan data. 2) Enhanced TDL_91 output to automatically insert the output file name for the PATTERN_SET_NAME parameter. In the vtran command file, this parameter normally has the form: simulator tdl_91 . . . PATTERN_SET_NAME = "SetName", . . . This resulted in a fixed "SetName". The new feature uses the following syntax to get the output file name for this parameter: PATTERN_SET_NAME = "'filename", 3) Added a canned reader for the Credence SWAV tester format. The application for this reader is to allow a vtran-generated SWAV test program file to be read back by vtran for the purpose of generating a Verilog or VHDL testbench file for verifying, thru re-simulation, the correctness of the test program. As such, the reader only supports the subset of SWAV commands and features used by vtran in the generation process. Also, translations from this tester format are only supported to simulation formats which use flat event-based simulation data. Because of this, the -CYCLE and -SCAN flags are ignored. When invoking the reader, the following syntax should be used in the OVF_BLOCK: TABULAR_FORMAT SWAV ; ORIG_FILE = "file.swav"; The vectors and timing information are both contained in the "file.swav". An example command file for an SWAV->Verilog testbench translation might ' look like: ovf_block begin tabular_format swav; orig_file = "micro_chip.swav" ; end proc_block begin state_trans 'H'->'1', 'L'->'0'; disable_vector_filter; end tvf_block begin target_file = "micro_chip.v"; simulator verilog_tb timescale = "1ps/1ps" ; end; end The primary benefit of this new reader is the ability to directly verify the correctness of a vtran-generated test program for the Credence tester thru direct generation of a simulation testbench file. This essentially closes the loop from a verification perspective, and provides a high degree of confidence for a working test program. Additional readers for other vtran-supported tester formats are planned for the near future. 4) Added optional flag to STIL writer interface which forces the STIL output file to have no empty Vector { } statements. While these statements are correct syntactically for the case where there are no changes in signal state from the last Vector statement, some tools have difficulty with them. Adding the -NO_EMPTY_VECTORS flag to the "TESTER_FORMAT STIL ..." statement in the TVF_BLOCK will cause the previous vector statement to be duplicated instead of an empty vector statement - the results are identical. The syntax is: TVF_BLOCK begin tester_format STIL, -NO_EMPTY_VECTORS, ... ; ... end 5) Added a canned reader for the Teradyne J750 tester format. The application for this reader is to allow a vtran-generated J750 test program file to be read back by vtran for the purpose of generating a Verilog or VHDL testbench file for verifying, thru re-simulation, the correctness of the test program. As such, the reader only supports the subset of J750 commands and features used by vtran in the generation process. Also, translations from this tester format are only supported to simulation formats which use flat event-based simulation data. Because of this, the -CYCLE and -SCAN flags are ignored. When invoking the reader, the following syntax should be used in the OVF_BLOCK: TABULAR_FORMAT J750 ; ORIG_FILE = "file.tp"; AUX_FILE = "file.tim"; The reader takes 2 files: the ORIG_FILE is the J750 test vector file, and the AUX_FILE is the timing file generated by vtran during translation. The J750 reader requires that both files be available. An example command file for a J750->Verilog testbench translation might look like: ovf_block begin tabular_format J750; orig_file = "micro_chip.tp"; aux_file = "micro_chip.tim"; end proc_block begin state_trans 'H'->'1', 'L'->'0'; disable_vector_filter; end tvf_block begin target_file = "micro_chip.v"; simulator verilog_tb timescale = "1ps/1ps" ; end; end The primary benefit of this new reader is the ability to directly verify the correctness of a vtran-generated test program for the Teradyne J750 tester thru direct generation of a simulation testbench file. This essentially closes the loop from a verification perspective, and provides a high degree of confidence for a working test program. Additional readers for other vtran-supported tester formats are planned for the near future. 6) Added -ALLOW_WINDOW_COMPARE flag to the SWAV output formatter. Previously, the timing generated in SWAV files for output pins only would accommodate edge compares. Adding this flag to the parameter list for SWAV out will cause the outputs to be window strobed when this is specified in the input file or in a pintype stb statement (by specifying both t1 and t2) in the PROC_BLOCK. 7) Added a canned reader for the Teradyne Catalyst tester format. The application for this reader is to allow a vtran-generated Catalyst test program file to be read back by vtran for the purpose of generating a Verilog or VHDL testbench file for verifying, thru re-simulation, the correctness of the test program. As such, the reader only supports the subset of Catalyst commands and features used by vtran in the generation process. Also, translations from this tester format are only supported to simulation formats which use flat event-based simulation data. Because of this, the -CYCLE and -SCAN flags are ignored. When invoking the reader, the following syntax should be used in the OVF_BLOCK: TABULAR_FORMAT Catalyst ; ORIG_FILE = "file.tp"; AUX_FILE = "file.tim"; The reader takes 2 files: the ORIG_FILE is the Catalyst test vector file, and the AUX_FILE is the timing file generated by vtran during translation. The Catalyst reader requires that both files be available. An example command file for a Catalyst->Verilog testbench translation might look like: ovf_block begin tabular_format Catalyst; orig_file = "micro_chip.tp"; aux_file = "micro_chip.tim"; end proc_block begin state_trans 'H'->'1', 'L'->'0'; disable_vector_filter; end tvf_block begin target_file = "micro_chip.v"; simulator verilog_tb -verbose, timescale = "1ps/1ps" ; end; end The primary benefit of this new reader is the ability to directly verify the correctness of a vtran-generated test program for the Teradyne Catalyst tester thru direct generation of a simulation testbench file. This essentially closes the loop from a verification perspective, and provides a high degree of confidence for a working test program. Additional readers for other vtran-supported tester formats are planned for the near future. 8) Added -USE_Z_DELAY flag to Agilent(HP)93000 output format. Normally, in the dvc file timing section, for bidirectional signals, when they change direction from input to output an input Z event is specified with a 0 delay from the beginning of the cycle. This flag causes the delay for the Z event to be the same as the specified delay for the other 1 or 0 logic transitions. 9) Added a -MINIMIZE_SCAN flag to Teradyne Catalyst and J971/3 tester output formats. Normally, for these tester formats, all scan chains are normallized (padded) to the length of the longest scan chain for each scan operation being performed, regardless of whether or not the longest chain was actually being scanned each time. This flag causes the length of the scan data on all scan pins, for any given scan operation, to be only as long as the longest scan chain which is actually being scanned in that particular scan operation. 10) Modified slightly the behavior of both the STIL reader and STIL writer in how drive vs. compare states are handled on bidirectional signals. In order to more accurately reflect the 1450-1999 specification, the drive states and compare states are handled independently - as two separate event streams. Assigning a state to one stream does not affect the current state of the other event stream. RELEASE 6.6 ----------- 1) Added SAMPLE_POINT statement to TIMESET block for TEMPLATE CYCLIZATION processing. The syntax is: SAMPLE_POINT @