Simulate Translate Test

VTRAN® Quickstart

Welcome to VTRAN®! VTRAN® is a powerful vector translation tool that translates vectors to and from a variety of IC development environments with virtually any data manipulation desired. Over 30 popular logic simulator and tester formats as well as user defined formats are supported. The frustration of dealing with dissimilar simulator data formats is eliminated with VTRAN®. Common uses of VTRAN® include

  • Re-formatting existing simulation data files which were generated by one simulator into files compatible with another simulator.
  • Translating state data files from logic analyzers, test programs or other data sources into stimulus files compatible with logic simulators. This includes the incorporation of pin timing.
  • Modifying simulation data files including changing pin lists, pin order, bus radixes, time offsets, pin timing and time scaling.
  • Translating simulation/ATPG output vector data or test programs into testbench data files for Verilog/VHDL re-simulation and verification.
  • Vector translation from simulation or ATPG-generated vectors into functional test vectors for physical device testers.
  • Act as a front-end to graphical waveform tools enabling them to read and display nearly any vector data file.

This application note provides all the information necessary to get started using VTRAN®.

Note: Usage of commands may vary depending on operating system, shell, and the name of the software bundle selected.

Getting VTRAN® Software

VTRAN® is available for Solaris 32-bit, Solaris 64-bit, Linux 32-bit, and Linux 64-bit operating systems. To install VTRAN® on your system:

  • Go to
  • Create a working directory on your local machine.
    mkdir source3 
  • Select the desired software bundle on the web page.
  • Download by pressing the RMB and "Save Link Target As..." into your local directory.
  • Select and download the INTERFACES bundle which includes example files and documentation on popular translations.
  • Create and populate your working directory with the executables and examples using the UNIX "gunzip" and "tar" utilities.
    gunzip linux64_vtran_tar.gz  
    tar xvfp linux64_vtran_tar  
    gunzip INTERFACES_tar.gz  
    tar xvfp INTERFACES_tar  

Installing VTRAN® Software

Launch the installer script in the newly created linux64 directory.


This is a short, text based question and answer session that prompts you for preferences, installs the software, and then provides you with the exact environment setup lines that you need. See the details below.

    • Install directory: You can specify a new or existing directory. You may specify the directory you just unpacked (this is the default).
    • Licensing. Do you want to use FlexLM-based licensing or do you want to use SDMT licensing?

To try out VTRAN® in the PREVIEW mode using a key that allows VTRAN® to run in a full feature mode but limits the number of vectors which can be translated to a few hundred, specify SDMT. Otherwise, specify "FLEX" to select the FlexLM licensing management system.

    • If FlexLM Licensing has been selected, please enter the full path to the license file you received from Source III (or the directory in which the file resides). You can also specify a license server in the form PORT@SERVERNAME.
    • Review the Installation summary information and restart the installer if necessary. Note the Environment Variable requirements. In your startup script (i.e. .cshrc, login) set the environment variable "S3_ROOT" to the name of the directory into which the software was loaded, include S3_ROOT in your search path, and provide licensing info.
setenv S3_ROOT /usr/source3/linux64 
setenv VTRAN®_USE_FLEX_LICENSING 1  # or 0 if SDMT PREVIEW mode has been selected
setenv LM_LICENSE_FILE /path/to/license/file.lic
set path = ($S3_ROOT $path) 
    • Initialize your environment by logging out and logging back in or In C shell use
      source .cshsrc
      source .login
    • At anytime, use the installer with the "-check" flag to verify your installation and environment.
      ./ -check

Setting Up VTRAN® Licensing


To use only the PREVIEW key that allows VTRAN® to run in a full feature mode but limit the number of vectors which can be translated to a few hundred, use the sdmt.preview file contained in the software bundle. Copy this file to sdmt.enable in the S3_ROOT directory.

cp sdmt.preview sdmt.enable 


To get a full-feature evaluation FlexLM license file, without limits on number of vectors, please fill in the form at Include the operating system and host ID of the computer you wish to evaluate the software on. Determine the host ID from the command line using the VTRAN® executable installed above.

vtran -hostid 

For FlexLM-based licensing, you can choose between node-locked and floating licenses. Use a node-locked license if you plan to run VTRAN® on only one system. This will allow unlimited copies of VTRAN® to run concurrently, but only on one system.

Whether you get a node-locked or floating license, you will need to set an environment variable LM_LICENSE_FILE to point at the file in your start-up script.

setenv LM_LICENSE_FILE /path/to/license/file.lic

If you already have a LM_LICENSE_FILE environment variable set up, you can either append your license location to it, separated by a colon, or you can use the alternate environment variable SIII_LICENSE_FILE.

setenv LM_LICENSE_FILE ${LM_LICENSE_FILE}:/path/to/license/file.lic
setenv SIII_LICENSE_FILE /path/to/license/file.lic

To run VTRAN® on multiple systems, use an existing FlexLM license server on your network, or set one up. At a bare minimum this requires running "lmgrd" on your designated license server, and pointing it to a suitable license file.

lmgrd -c /path/to/license/file.lic 

Find an "lmgrd" binary included with your VTRAN® software, in the support/ subdirectory along with the "siiid" vendor daemon, used only for floating licenses. There are many other possible configuration options when setting up a floating license server. Refer to the detailed License Administration Guide which is available on the Flexera Software support website.

Running VTRAN®

The VTRAN® program is text based application designed to perform vector translations. It reads in vector data from logic simulators or ATPG tools and translates it into ATE test programs or formats for other EDA environments. The user controls the VTRAN® translation process with an ASCII command file. Original and target waveforms can be displayed using DFTView, the Source III graphical display tool. Historically, the ASCII command file has been created using a text editor and VTRAN® has been launched from the command line. See a VTRAN® translation example and run it from the command line by going to the INTERFACES directory created above.

vtran exp1.vtran

While, this continues to be an option, the VTRAN® User Interface Utility (VUI) is now available. It is a graphical user interface developed specifically for generating VTRAN® command files and is automatically* installed with VTRAN® in the S3_ROOT directory. Though originally intended for the novice user it can be effectively used to generate even the most complex VTRAN® command files. VUI provides context sensitive help for all form fields, interactive syntax checking, and parameter compatibility analysis.

The VTRAN® translation process may be launched from within the VUI. Original and target waveforms can be also be displayed using DFTView via the VUI.

The VTRAN® User Interface is typically launched without any command line arguments.


* Since the VTRAN® 9.6.3 release, the VUI has been included in the VTRAN® bundle. A separate VUI bundle is available. This may be useful if, for example, you have an older VTRAN® package installed (although upgrading is always recommended!), or if you wish to evaluate newer VUI releases separately from the main VTRAN® bundle.

Getting Information

On-line support for VTRAN® is available on the Source III web site at Common problems related to the system environment are covered on the Source III FAQs page at A VTRAN® manual, VUI manual, Data Sheet, Training Foils, and a series of Application Notes can be found by clicking this link. Additionally the software and INTERFACES downloads are rich with README files.

VUI Overview

The VUI is designed to guide you through the process of generating a VTRAN® command file with the required parameter and statements by presenting a series of five forms. Default values are presented where possible and only relevant choices are displayed. When the VTRAN® flow has been specified, a command file is created, VTRAN® is executed, and the results are displayed. The target waveform is immediately available for viewing if DFTView is installed.

Three of the VUI forms correspond to the three blocks that make up the VTRAN® command file.

  • OVF_BLOCK - The Original Vector File Block
  • PROC_BLOCK - The Process Block
  • TVF BLOCK - The Target Vector Block

Other forms include "Initial Setup", used to specify some global parameters, and "Preview", used to display the actual VTRAN® command file. The "Preview" form is also used to launch VTRAN® and DFTView (if installed).

The next several sections show the construction of a VTRAN® command file used to translate a cycle based STIL source into a test program file for a 93000 VLSI Test System.


The main purpose of this form is to select the input and output formats and file names. The choices you select on this page will then automatically customize each following form pages to only prompt for inputs related to the formats you choose. VTRAN® provides interfaces for almost any print-on-change and cycle-based format. VUI currently supports only a subset of these interfaces and formats. If you don't see your interface or format listed, let us know.

See the Initial Setup form used to specify the STIL to 93000 translation. Note the Context-Sensitive Help that appears when the mouse hovers over the TMPDIR field. Context-Sensitive Help is enabled/disabled via the Help Menu in the Upper Right Hand corner of each form.


The OVF_BLOCK is used to tell VTRAN® how to read the Original Vector File (OVF). Many times, the default parameters are all that is needed. Such is this case in this example. If the OVF format selection was something else the OVF_Block form might look different. VUI displays only the pertinent parameters.


The PROC_Block contains commands that tell VTRAN® what data processing functions to perform on the OVF data during translation. At a minimum these functions will usually include state mapping. Other functions such as cyclization, bidirectional data control considerations, adding pins, masking pins, inserting statements, and modifying the timing of state transitions are dependent on the needs of the particular translation. For this example, the applicable fields are Data Modification Directives, and Output Timing. Default values are provided where possible, most notably STATE MAPPING.

The processing functions occur in a predefined order and are not affected by the order in which they appear in the PROC block. Some information about the processing sequence is provided in the following discussion of each translation type. See the VTRAN® User's Guide Section 6.2 for more details.


The commands in the TVF block tell VTRAN® how to format the vectors in the Target Vector File and what if any reporting parameters are desired. In this example, though the default selections are sufficient, a report on the behavior of all outputs has been selected . Notice that VUI allows for the use of an External Editor on all multi-line form fields.


The resultant VTRAN® ASCII command file is available for study on this form. Pressing 'Run VTRAN®" causes VTRAN® to execute and summary results to be displayed in a separate window.

VTRAN® Feedback Window with Summarized Results. The DFTView Display Options are available when the VTRAN® execution is successful and DFTView is installed.

OTHER VUI Features

  • VUI provides a parameter save/restore feature. VTRAN® command files can also be saved and launched directly or within a batch processing system.
  • A PINS mode extracts the signal names and directions from an Original Vector File (OVF) supported by a canned reader for the purpose of verifying signal names or generating pin lists for use in the VTRAN® command file.

Useful  VTRAN® Concepts

Original Vector File Formats Signal Direction Considerations in the OVF Block

In the case of a well known format, VTRAN® most likely has a canned reader. If this format also allows VTRAN® to automatically determine signal direction (as is the case with Verilog EVCD, WGL, STIL,) there is often very little additional information actually needed and default values will suffice. If this format does not, however, allow VTRAN® to automatically determine signal direction (as is the case with Verilog VCD), pin declarations are required. INPUTS, OUTPUTS, and BIDIRECTS commands are used for this purpose. They can be used in any order and as many times as desired to specify the signals you wish to have read from the original vector file. Note that the order of declarations also determines the order of the signals in the output vector file unless overridden in the TVF_BLOCK.

OVF_Block Form INPUTS/OUTPUTS/BIDIRECTS/ field example when the format of the Original Vector File is Verilog VCD.

User-Programmed Reader

When no canned reader exists to read the format of the vectors in the original vector file, more information must be specified in the OVF block for the User-Programmed Reader. The INPUTS, OUTPUTS, and BIDIRECTS commands shown above, as well as the detailed user format descriptions in SCRIPT_FORMAT, TABULAR_FORMAT, and WAVEFORM_FORMAT commands are critical components in the successful input of User Formats. Additional commands that may be used to specify reader options for user formats include BEGIN_LINE, BEGIN_STRING, BUSFORMAT, WHITESPACE, CASE_SENSITIVE, GROUP, and MAX_UNMATCHED. See the VTRAN® User's Guide Section 3.0 for details on how to use these commands.


Multiple vector files can be merged horizontally or vertically using VTRAN®. The original files may contain all the same signals (in which case the merge is actually a concatenation), all different signals, or there may be an overlap of some of the signals in some of the original files. See the Application Note titled "Merging Multiple Input Files" ( for more details.

An example of the Merge File Directives being specified in the ADDITIONAL_STATEMENTS field of the VUI OVF_Block Form.

State Mapping

State Mapping considerations apply to nearly every translation type and a default is always provided in the VUI PROC_Block Form.

The state characters used in the Original Vector File will most likely be different than those used in the Target Vector File. For example, in a standard Verilog VCD file, the state characters are 1, 0, X, Z, x, and z. The state character set used by a target vector format tester will vary. A typical set (say for a Credence tester) would be 1, 0, H, L, X, Z. It may also be desirable to map the Z state on outputs to an X so the checking is masked, and perhaps any X states on pure inputs to a valid 1 or 0 state. State mapping is accomplished using the STATE_TRANS command. The above example can be accomplished with:

STATE_TRANS inputs 'x'->'1', 'X'->'1', 'z'->'Z';
STATE_TRANS outputs '1'->H', '0'->'L', 'z'->'X',
            'Z'->'X',' 'x'->X';

Note the use of predefined signal group inputs and outputs. Other predefined signal groups are pure_inputs, pure_outputs, bidir_inputs, and bidir_outputs.

Important: STATE_TRANS is one of the last processes applied to the Original Vector File. This means that most all other processes invoked by the PROC block use the states directly from the OVF input file for logic expressions (i.e. before STATE_TRANS is applied).


Translations from print-on-change (POC) formats to cycle based formats require a process called cyclization. POC formats such as Verilog VCD, Mentor's LSIM, TSSI's TDS or Novas FSDB typically have state data and time entries in the vector file every time there is a state change on any pin. One can consider these as flat or time-expanded vectors. Cycle-based formats used by testers such as Credence, Teradyne and Verigy, however, use a single vector to combine all the state transitions that occur in a given time period or cycle. The cyclization commands tell VTRAN® how many print-on-change vectors should be collapsed into a cycle vector, how to gather meaningful state data, and target timing.

VTRAN® supports multiple cyclization flows and can be used with POC files that have both single and multiple timesets. Here, timeset refers to a set of signal behaviors and an associated period. Multiple timeset POC file flows, use the TEMPLATE_CYCLIZATION feature of VTRAN®. This flow is described in detail in a separate Application Note titled "VTRAN® Template Cyclization Feature" ( Single timeset POC file flows use the ALIGN commands and are described in the Application Note titled "Print-on-change to Cycle-based Translations" (

The ALIGN_TO_CYCLE and all other Cyclization Functions are selected on the VUI PROC_Block Form.

Bi-directional Data Control

VTRAN® creates two internal pins versions for each bi-directional signal. The input uses the defined name and is used to store the input data from the OVF. Output data is stored on the output version of the signal "signal.O". The input is assigned a Z state when the pin direction is determined to be output. Similarly, the output is assigned an X state when the pin direction is determined to be input. For some vector formats like Verilog VCD files, there is no distinction in the data itself for determining whether the state data on a bi-directional signal is input data or output data. It is therefore necessary to use a VTRAN® process like BIDIRECT_CONTROL (located on the PROC_Block Form) to specify when states represent input data or output data, usually as a logical function of a control signal. An example of this would be:

Here we specify that the state data on the bi-directional signals bidirSig1, bidirSig2, and bidirSig3 in the VCD file should be interpreted as input data when the control signal OutputEnable is a logic 0. By default, this implies it is output state data if OutputEnable is not 0. All bi-directional signals in the VCD file need to have their data directions specified in a manner similar to this. Multiple BIDIRECT_CONTROL statements can be used (up to one for each bi-directional pin if needed). BIDIRECT_STATES commands are also used to specify signal direction and are used when the OVF is a user format and the format uses different characters for input data than for output data.

If the OVF format contains information such that the VTRAN® reader can make a determination when data on a bidirectional pin represents an input state or an output state, BIDIRECT_CONTROL statements are not needed. WGL, STIL, and Verilog EVCD are examples of this type of format.


ADD_PIN provides a way to add pins to the TVF that did not exist in the OVF. Found on the PROC_Block Form, this feature allows for a set of state value assignments where each assignment is based upon the evaluation of a compound logic expression. Once created, this pin can be manipulated like any other signal in the original vector file. See the Application Note titled "Using the ADD PIN Command" (


The MASK_PINS command (PROC_Block Form) can be used to modify the state defined for a signal in the Original Vector File (OVF). This command can be applied both to input and output signals, and to both the input and output data of a bidirectional signal. Any state can be used as a mask character. Pin states can be masked within each cycle, or in multiple vectors within a time range, or when specified masking conditions are met. MASK_PINS can be used to mask output signals for times in the cycle they are not in a stable state or for debugging a functional test program. MASK_PINS is applied before STATE_TRANS. For details on how to use command see the Application Note titled "Using the MASK_PINS Command" (

Inserting Statements into the Target Vector File

The intention of this feature (PROC_Block Form) is to allow arbitrary tester or simulation statements to be inserted into the target vector file. This can be used to insert macros or subroutine calls in a test pattern or a testbench. It can also be used to insert comments for documentation. See the Application Note titled "Adding Statements to Target Vector File" (

Modifying Timing State Transitions

Extensive modifications to the timing of state transitions in POC vector files for the purpose of re-simulation using the same or another simulator can be made using the PROC_Block Form SCALE and EDGE_SHIFT commands.


The CREATE_STATISTICS command causes VTRAN® to accumulate and report statistics on the states and state transitions of any or all signals for some or all the vector space. This is especially useful, when generating test programs or test bench files, where it is important to know to what extent output signals are being checked. Use the TVF_Block Form and see the Application Note titled "Generating Device Test Program Statistics" (

Specific Translation Examples

Specific translation examples are available in the INTERFACES bundle (see the Getting VTRAN® Software sections of this document) and in the following list of application notes:

  • Cycle-based to Testbench Translations
  • Print-on-change to Testbench Translations
  • Verifying VTRAN®-generated Test Programs
  • Translating EDA Vector Files to SPICE
  • Translating WGL/STIL Vector Files to Teradyne Tester Formats
  • Translating WGL/STIL Vector Files to HP83000/93000 Tester Formats
  • Translating WGL/STIL Vector Files to the Credence Tester Format
  • Control Signal and Vector Insertion for Q-Star Test Modules

While these examples generally focus on specific formats, the strategies and processing illustrated can be applied to other translations.

Product Support

Customer Quotes

  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • We currently use Vtran for translating wgl, evcd and vcd vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with SourceIII has been positive and their support is extremely responsive and timely.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
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