News > New VTRAN 9.1 Release

New VTRAN 9.1 Release

Source III announces the release of VTRAN 9.1 for the Solaris SPARC, Solaris X86 and Linux platforms.

This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following:

• Enhanced tester interface for the Advantest T2000 tester adding support for scan data on both the T2000 writer and ReadBack module.
• Enhanced general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files.
• Enhanced Verilog testbench output formatters to include vector and cycle count information which corresponds to vectors in the input source file. Very useful when using ReadBack modules for Teradyne, Verigy or Credence to validate test programs.
• Enhanced TSTL2 writer to better support various combinations of signal grouping and timing.
• Enhanced MERGE_FILE feature to give more flexibility handling timing of non-common signals for concatenated files.
• Added ability to pass STIL statement labels as comments to ATE writers.
• Updated FSDB (Springsoft) writer.
• VTRAN now supports Include files in the command file facilitating the use of common files

In addition to these highlights, VTRAN has had on-going improvements to its speed, memory efficiency and overall program quality. VTRAN has played an important roll in linking simulation/ATPG to test for over 18 years with thousands of successful vector translations.