Q-Star Test and Source III announce a strategic partnership to help further reduce test costs and enhance product quality - February 22, 2008
Q-Star Test and Source III announce a collaboration targeting the automatic insertion of Q-Star Test Ixxx module control using Source III's VTRAN tool into test pattern data when generating a test program starting from ATPG vectors incorporating IDDQ measurement points in WGL or STIL format.  More.. 

Magma Design Automation collaborates with Source III to offer direct path from Talus ATPG to ATE testers -- October 15, 2007
Magma Design Automation, a provider of chip design software, announced that it has partnered with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to a variety of testers via Source III's VTRAN. With a foundation in IEEE 1450 STIL and thru its collaboration with Source III, Magma is working to improve test quality, streamline test flow and reduce test costs. More...

CADENCE Expands Design Chain Through Encounter Test Collaboration with Source III -- SAN JOSE, Calif. , October 25, 2006
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Source III, Inc., a leading developer of test conversion and verification programs, have announced a collaboration to enable improved test validation and faster test conversion for enhanced chip quality.

The joint effort expands the silicon design chain to include validation by Source III of test programs developed on the Cadence® Encounter® Test automated test program generation (ATPG) platform, as well as conversion of semiconductor test programs to targeted automatic-test-equipment (ATE) platforms.

Source III will validate test programs generated on the Encounter Test platform using Verilog model simulations as the golden standard. Additionally, Source III will convert and generate test programs from the Cadence standard test interface language STIL to a format readable by targeted ATE platforms. More...

Source III Announces Release 7.6 of VTRAN - June 29, 2006
The 7.6 release of vtran provides significant enhancements to the STIL interfaces, both canned reader module and the STIL output formatter. The ReadBack modules from previous releases have been enhanced to provide cycle-based readback as well as the event-based capabilities. This means that vtran-generated test programs can be directly translated to other tester formats as well as testbench formats for verification. The Agilent (HP) 93000 interface has been enhanced to handle Pincsale capabilities with optimized resource assignments in the dvc files. In addition, numerous new parameters have been added to different interfaces to improve user control and customization of the translated vector data.

Source III Announces Release 7.1 of VTRAN - August 2004
The 7.1 release of vtran continues to strengthen the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces additional canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750, J973 and Catalyst are included in this release. XMODE support for the Agilent 93000 tester is now available, enabling significant memory size and performance improvements.

Source III Announces Release 7.0 of VTRAN - March 2004
The 7.0 release of vtran strengthens the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces a new set of canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750 and Catalyst are included in this release. The STIL reader has also undergone substantial upgrades in this release, adding support for many of the popular 1450.1 features needed to handle today's complex SOC designs.

Source III Announces Release 6.5 of VTRAN - April 2003
The 6.5 release of vtran introduces the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. Thus, popular VCD files with dynamically changing timing can now be translated to test programs using this feature. Also in this release is initial support for the ITS900 tester. Other new features include enhanced signal masking capabilities, dramatically improved WGL reader performance, a new PIN_INFO_FILE feature, and numerous interface enhancements and upgrades.

Source III Announces Release 6.0 of VTRAN - February 2002
The new 6.0 release of vtran enhances a number of interfaces including the following; STIL reader adds support for many .1 (dot 1) extensions, MUX support for WGL, passing of structural loops and repeats between formats, enhanced Verilog and VHDL testbench features plus many more. An initial IMS MEM output format is included in this release. Also this release includes the first 64-bit Solaris version of vtran, pushing its ability to handle very large files beyond the 2GB limit.. With this release, Source III continues its constant improvements and feature enhancements of vtran, based upon customer needs and requests.

Source III Announces release of VTRAN 5.0 - February 2001
This new release of VTRAN adds support for the Teradyne J971 and J973 testers, in addition to significant enhancements to signal masking processing and the direct reading of gzip'ed files. A new interface to the HSIM simulator from Nassda is also included in this release. The Verilog and VHDL testbench interfaces were both enhanced with additional optional parameters to further customize testbenches.

Source III / Synopsys Provide Joint Solution - September 2000
Source III joins Synopsys’ In-Sync Program to provide a joint solution for quick and easy translation of TetraMAX-generated vectors in either WGL or STIL format to test programs for Credence, Teradyne and HP testers. Using vtran, users can readily translate large scan-based vector sets generated by ATPG products into ready-to-use test programs. Click here for more details.

Source III Announces support for HP83000/93000 testers - August 2000
With the release of VTAN 4.6, Source III announces support for the HP83000 and HP93000 testers as target formats for vector translations from WGL, STIL, Verilog VCD and many other formats. With this new interface, the popular HP testers become easily accessible to users with almost any simulation or ATPG-generated vector sets.

Source III Releases VTRAN 4.6 on - August 2000
Source III announces the release of VTRAN 4.6 with several enhancements to vector translations and support for several new tester formats. With this release, VTRAN now fully supports translations of vector data which include scan chains and scan-formatted data from the popular WGL, as well as the new IEEE STIL, vector formats to the Teradyne (Catalyst and J750), Credence, HP83000/93000 and HP-3070 (PCF) tester formats, as well as numerous ASIC (TSTL2, TDL_91, ..) and simulator formats (Verilog/VHDL testbench, ..). One of the primary focuses of this new release was the enhanced support of scan data during translation between popular simulator and tester formats. This is an increasingly more common need as scan-based DFT and ATPG tools, such as Synopsys' Design Compiler and new TetraMAX(tm), create vector sets for large complex designs. Support for additional tester formats are planned for release over the next year.

Source III Announces enhanced STIL support - August 2000
The latest 4.6 Release of VTRAN now includes support for reading the new IEEE Standard Test Interface Language (1450) vector files. With this improved canned reader, VTRAN can handle translations from STIL to a variety of testers (including Teradyne, Credence, HP83000/93000 and HP-3070 PCF), ASIC formats such as TSTL2 and TDL_91, and simulator formats such as Verilog and VHDL testbenches. As tools that generate vector data begin to standardize on this new IEEE standard format, the need for a bridge to the numerous other formats accepted by today’s simulation tools and testers increases. In addition to providing this bridge, VTRAN also can be effectively used for verifying tools that generate STIL by providing a path back to simulation - essentially closing the loop. A STIL writer is also under development for release next year.