Simulate Translate Test

List of File Formats Supported by DFTView

Wednesday, 21 December 2016 13:04
Recently, after months of development by our amazing staff here at Source III, our team was able to release one of its most important updates: VTRAN and DFTView release 10.3 has added support for Advantest SmarTest8. Now you can read, display, and translate between SmarTest8 and dozens of the most popular file formats utilized in DFT. It seems like now is a good time to re-release the list of file format and filename extensions that are supported by our DFTView system which is powerful enough to handle all of the following File Formats: Advantest T2000 Advantest SmarTest8 EVCD HP 93000 STIL SVF Teradyne Catalyst Teradyne FLEX (inc. iFLEX, microFLEX and ultraFLEX) Teradyne J750 (and Teradyne J750+) Texas Instruments TDL 91 Toshiba TSTL 2 VCD WGL Some of these file formats are often given different file name extensions. For reference, the following represent the file extensions that DFTView can use to…
We are pleased to announce that, on Monday, Source III released a major update to our VTRAN Software Bundle functionality. After over 2 years of development working directly with Advantest, VTRAN now offers Advantest SmarTest8 Support. This functionality was thanks to the combined efforts of our entire team here at Source III, including Linda, Carrie, Brian, and Frances, and we’re very pleased that our customers can now use our tool to assist them with their Advantest V93000 SmartTest8 testers, and includes: Advantest V93000 SmarTest8 Interface Advantest V93000 SmarTest8 Reader The reader can be used to generate a Verilog or VHDL TestBench file. For those that need assistance in using the VTRAN 10.3 Software Bundle for their Advantest SmarTest support, we have tips and assistance available in our 10.3 Release Notes. Additional Functionality In addition to this major update, we also have added several features that our clients have requested over…
Our support team at Source III is the best in the vector translation business. On occasion, we are asked a great question by our customers, and when we think that the answer may be relevant for other clients, we turn it into a blog post. The following is a recent customer question, followed by the response from our support team: Question: "Does VTRAN allow STIL vector statements with no arguments (signifying no change from the previous vector) or vector statements with vector strings of different lengths when applied to different signal groups?" Answer: The short answer is yes, VTRAN handles this just fine.  It maintains the previous state on any pin not modified in a particular vector.   Longer answer:  Vector statements (shorthand V) in STIL typically only specify changes relative to the previous cycle.  Thus any signal or group not explicitly referenced will retain the previous state, and active…
Question: I have a simulation file in VCD format and want to use VTRAN to generate an ATE device test program.  Because of the complexity of this device, the test program will need to have multiple timesets.  I think I need to use VTRAN's TEMPLATE_CYCLIZATION strategy. How do I get started? Answer: If you have a situation where you need to generate multiple timesets and :        all of timesets have the same cycle length, but you do not have a tester that supports flexible waveform descriptions OR        the timesets have different cycle lengths you do need to use the TEMPLATE_CYCLIZATION strategy.  The feature is quite powerful and described fully in the VTRAN User Guide and in the Applcation Note titled "TEMPLATE CYCLIZATION".   Here are the basics. How does it work? TEMPLATE CYCLIZATION works by applying user created timesets to the original waveform.  VTRAN determines which timeset to apply based on…

Question: How do I choose a Cyclization Strategy?

Thursday, 15 September 2016 10:50
Question: What is cylization and how do I choose a cyclization strategy using the VTRAN Tool Suite? Answer: Event-based formats like VCD and EVCD typically have state data and time entries in the vector file every time there is a state change on any pin. These are considered flat or time-expanded vectors.  Cycle-based formats, used in ATE device test program files, combine all the state transitions that occur in a given time period or cycle into a single vector that references a separate "timing" (i.e. waveform edge times) section of the target format. Cyclization is the process of collapsing the event driven vector data from event-based formats into cycle-based formats . VTRAN has several cyclization flows and the best choice depends on the translation. VCAP STIL_TRANS If the waveforms in the Original Vector File can be represented by cycles of a consistent length, and the target vector format supports flexible…