Simulate Translate Test


Source III was founded in 1980 to provide full custom and semicustom design services, making extensive use of gate array and standard cell design methodologies. During the first 6 years of its existence dozens of custom and semicustom design projects were completed for many large electronics companies.

In 1986 the company was restructured to provide not only design services, but to also develop and market design tools for ASIC and system designers. The ongoing involvement of Source III in the use of CAE design tools for designing ICs resulted in the development and introduction of its first product (VGEN®) in 1987. Source III found a significant weak link in the design process offered by most CAE vendors in the area of simulation stimulus generation. Initially developed for internal use, VGEN® provides a powerful, simulator independent, high-level language for the stimulus generation task.

The first customer installation of the VGEN® compiler occurred in late 1987 and the product has evolved substantially over the past several years. Over 1000 design engineers have used VGEN® to create, manage and document logic simulation stimulus files.

In 1990, Source III introduced its second product - VTRAN®, a powerful vector translation utility which enables designers to move simulation stimulus files between different logic simulators while optionally performing various timing and state modifications. This product currently provides a link between over 30 different simulation tools.

In October of 1991, VCAP®, a powerful simulation data comparison and analysis program was introduced. This program is designed to meet the need for verification of simulation results data. It also performs timing analysis on simulation results files producing reports on output min/max delays and pin behavior.

VTRAN®'s first links between simulation data results files or ATPG-produced files and physical device testers were introduced in 1992. This software produces functional test programs for testers from simulation and ATPG-generated data files under complete user control. It supports canned readers for all popular EDA vector formats (VCD, EVCD, WGL, STIL, ...) and links to most popular testers including Verigy, Teradyne, Credence, Advantest, LTX and others. VTRAN® has been used successfully by hundreds of engineers on thousands of vectors translations over the past 19 years.

Source III uses a combination of direct sales and OEM relationships to sell its products, with more emphasis on the direct sales channels. Source III currently has OEM relationships with the following companies:

Synopsys (TetraMAX™) - Writer IP / custom VTRAN®

Cadence (Quickturn Design Systems) - Reader IP / custom VTRAN®

We have a distributor in China. Some of the companies currently using our tools are: AMD, Broadcom, TI, Intel, Marvell, Qualcomm, ARM, NXP, Cisco Systems and many more.

The current focus of the company is providing CAE tools which aid the designer in the data-intensive aspects of design/simulation/test. This includes stimulus generation (VGEN®), simulation data translation (VTRAN® and test option), and simulation data verification/analysis (VCAP®). All areas in which growing needs are not being met by the major CAE vendors.

Product Support

Customer Quotes

  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
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