INTERFACES/000075500001440000012000000000001123464374600133435ustar00jcosleystaff00000400000023INTERFACES/QSTAR/000075500001440000012000000000001103104161000142065ustar00jcosleystaff00000400000023INTERFACES/QSTAR/WGL/000075500001440000012000000000001103104161000146375ustar00jcosleystaff00000400000023INTERFACES/QSTAR/WGL/exp1.wgl000064400001440000012000000104131103104161000162260ustar00jcosleystaff00000400000023 { # Translation Date: Thu Aug 2 16:52:06 2007 # VTRAN Version: 7.7.5 } waveform "TMDEMO240C" signal "InData[1]" : input ; "InData[0]" : input ; "BidData[1]" : bidir ; "BidData[0]" : bidir ; "OutData" : output ; "En" : input ; "Sclk" : input ; "SDI0" : input ; "SDO0" : output ; "SEN" : input ; end timeplate "_default_WFT_" period 100NS "InData[1]" := input[0PS:S]; "InData[0]" := input[0PS:S]; "BidData[1]" := input[0PS:S]; "BidData[1]" := output[0PS:X, 40NS:Q'edge]; "BidData[0]" := input[0PS:S]; "BidData[0]" := output[0PS:X, 40NS:Q'edge]; "OutData" := output[0PS:X, 40NS:Q'edge]; "En" := input[0PS:S]; "Sclk" := input[0PS:D, 50NS:S, 80NS:D]; "SDI0" := input[0PS:S]; "SDO0" := output[0PS:X, 40NS:Q'edge]; "SEN" := input[0PS:S]; end timeplate "_scannnn_WFT_" period 80NS "InData[1]" := input[0PS:S]; "InData[0]" := input[0PS:S]; "BidData[1]" := input[0PS:S]; "BidData[1]" := output[0PS:X, 40NS:Q'edge]; "BidData[0]" := input[0PS:S]; "BidData[0]" := output[0PS:X, 40NS:Q'edge]; "OutData" := output[0PS:X, 40NS:Q'edge]; "En" := input[0PS:S]; "Sclk" := input[0PS:D, 50NS:S, 70NS:D]; "SDI0" := input[0PS:S]; "SDO0" := output[0PS:X, 40NS:Q'edge]; "SEN" := input[0PS:S]; end pattern group_ALL ("InData[1]", "InData[0]", "BidData[1]", "BidData[0]", "OutData", "En", "Sclk", "SDI0", "SDO0", "SEN") vector(0nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 0 ]; vector(100nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; { this is some pattern annotations } { this is some more -> pattern annotations } vector(200nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 X 1 ]; vector(280nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 X 1 ]; vector(360nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(460nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 0 1 ]; vector(540nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 0 1 ]; vector(620nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(720nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 1 1 ]; { measIDDQ } vector(800nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 1 1 ]; vector(880nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(980nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 0 1 ]; vector(1060nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 0 1 ]; vector(1140nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(1240nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 X 1 ]; vector(1320nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 X 1 ]; vector(1400nS, "_default_WFT_") := [ 0 1 -X -X X 0 0 0 X 0 ]; vector(1500nS, "_default_WFT_") := [ 0 1 -1 -0 1 0 0 0 0 0 ]; vector(1600nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(1700nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 0 1 ]; vector(1780nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 0 1 1 ]; { measIDDQ } vector(1860nS, "_default_WFT_") := [ 1 1 -X -X X 0 0 1 X 0 ]; vector(1960nS, "_default_WFT_") := [ 1 1 -1 -0 1 0 0 1 1 0 ]; vector(2060nS, "_default_WFT_") := [ 1 1 -X -X X 0 1 1 X 0 ]; vector(2160nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(2260nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 1 1 ]; vector(2340nS, "_scannnn_WFT_") := [ X X X- X- X 1 1 1 1 1 ]; vector(2420nS, "_default_WFT_") := [ 0 0 -X -X X 0 0 1 X 0 ]; vector(2520nS, "_default_WFT_") := [ 0 0 -0 -1 0 0 0 1 1 0 ]; vector(2620nS, "_default_WFT_") := [ 0 0 -X -X X 0 1 1 X 0 ]; vector(2720nS, "_default_WFT_") := [ X X X- X- X 1 0 X X 1 ]; vector(2820nS, "_default_WFT_") := [ X X X- X- X 1 0 X 1 1 ]; vector(2920nS, "_default_WFT_") := [ X X X- X- 0 1 0 X 1 1 ]; vector(3020nS, "_default_WFT_") := [ 1 X X- X- 0 1 0 X 1 1 ]; vector(3120nS, "_default_WFT_") := [ 1 X X- X- 0 1 0 X 1 1 ]; vector(3220nS, "_default_WFT_") := [ 1 0 X- X- 0 1 0 X 0 1 ]; vector(3320nS, "_default_WFT_") := [ 1 0 X- X- 0 1 0 X 0 1 ]; vector(3420nS, "_default_WFT_") := [ 1 0 X- X- 1 1 0 X 0 1 ]; vector(3520nS, "_default_WFT_") := [ 0 0 X- X- 1 1 0 X 0 1 ]; vector(3620nS, "_default_WFT_") := [ 0 0 X- X- 1 1 0 X 1 1 ]; vector(3720nS, "_default_WFT_") := [ 0 X X- X- 1 1 0 X 1 1 ]; vector(3820nS, "_default_WFT_") := [ 0 X X- X- 1 1 0 X 1 1 ]; vector(3920nS, "_default_WFT_") := [ 0 X X- X- 1 1 0 X X 1 ]; vector(4020nS, "_scannnn_WFT_") := [ 0 X X- X- X 1 1 0 0 1 ]; vector(4100nS, "_scannnn_WFT_") := [ 0 X X- X- X 1 1 0 0 1 ]; end end INTERFACES/QSTAR/WGL/exp1.vtran000064400001440000012000000042201103104161000165660ustar00jcosleystaff00000400000023{ #======================================================================# # Translation: WGL < to > WGL with Q-Star IDDQ test control insertion # # Original File: "exp1.wgl" # # Target File: "exp1_out.wgl" # # Command File: "exp1.vtran" # # Author: SOURCE III, Inc. # # VTRAN 8.1 (C) 2008 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. It also specifies the Q-Star parameters # # for inserting control vectors for the QD1011 IDDQ test H/W # #======================================================================# } ovf_block begin orig_file = "exp1.wgl"; comments on; tabular_format wgl -cycle -scan -keep_annotations ; QStar Product = "QD1011" , ComTest = "Y" , Sample = "1" , GRef = "D 0.4mA .8ma" , Keyword = "measIDDQ", Mode = "1" ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing for translations # # There is no processing necessary for WGL-to-WGL flow. # #======================================================================# } proc_block begin end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin simulator WGL addresselement="cyclenumber", addresselement="time"; target_file = "exp1_out.wgl"; end end INTERFACES/QSTAR/WGL/exp2.wgl000064400001440000012000000376661103104161000162520ustar00jcosleystaff00000400000023# WGL pattern output written by TetraMAX (TM) 1999.10-i000127_103904 # Date: Fri Feb 4 12:43:54 2000 # Module tested: TMDEMO240C # === bidimap === # in out in out; # 00 00 # 10 10 # X0 X0 # Z0 -0 # -0 -0 # 01 01 # 11 11 # X1 X1 # Z1 -1 # -1 -1 # 0X 0- # 1X 1- # XX X- # ZX -X # -X -X # 0Z 0Z # 1Z 1Z # XZ XZ # ZZ -Z # -Z -Z # 0- 0- # 1- 1- # X- X- # Z- -- # -- -- # scanchain inversion reference is set to omit # Uncollapsed Fault Summary Report # ----------------------------------------------- # fault class code #faults # ------------------------------ ---- --------- # Detected DT 87 # Possibly detected PT 7 # Undetectable UD 2 # ATPG untestable AU 10 # Not detected ND 0 # ----------------------------------------------- # total faults 106 # test coverage 87.02% # ----------------------------------------------- # # Pattern Summary Report # ----------------------------------------------- # #internal patterns 3 # #basic_scan patterns 3 # ----------------------------------------------- # # rule severity #fails description # ---- -------- ------ --------------------------------- # B8 warning 1 unconnected module input pin # B9 warning 6 undriven module internal net # B10 warning 13 unconnected module internal net # Z9 warning 2 bidi bus driver enable affected by scan cell # # clock_name off usage # ---------------- --- -------------------------- # /Sclk 0 master shift # # port_name constraint_value # ---------------- --------------- # /SEN 0 # # There are no equivalent pins # There are no net connections waveform TMDEMO240C signal "InData[1]" : input; "InData[0]" : input; "BidData[1]" : bidir; "BidData[0]" : bidir; "OutData" : output; "En" : input; "Sclk" : input; "SDI0" : input; "SDO0" : output; "SEN" : input; end timeplate "_default_WFT_" period 100ns "InData[1]" := input [0ps:S]; "InData[0]" := input [0ps:S]; "BidData[1]" := input [0ps:S]; "BidData[1]" := output [0ps:X, 40ns:Q'edge]; "BidData[0]" := input [0ps:S]; "BidData[0]" := output [0ps:X, 40ns:Q'edge]; "OutData" := output [0ps:X, 40ns:Q'edge]; "En" := input [0ps:S]; "Sclk" := input [0ps:D, 50ns:S, 80ns:D]; "SDI0" := input [0ps:S]; "SDO0" := output [0ps:X, 40ns:Q'edge]; "SEN" := input [0ps:S]; end timeplate "_scannnn_WFT_" period 80ns "InData[1]" := input [0ps:S]; "InData[0]" := input [0ps:S]; "BidData[1]" := input [0ps:S]; "BidData[1]" := output [0ps:X, 40ns:Q'edge]; "BidData[0]" := input [0ps:S]; "BidData[0]" := output [0ps:X, 40ns:Q'edge]; "OutData" := output [0ps:X, 40ns:Q'edge]; "En" := input [0ps:S]; "Sclk" := input [0ps:D, 50ns:S, 70ns:D]; "SDI0" := input [0ps:S]; "SDO0" := output [0ps:X, 40ns:Q'edge]; "SEN" := input [0ps:S]; end scancell "SFF1"; "SFF2"; A; B; C; D; E; F; G; IN0G ["SFF1", "SFF2", A, B, C, D, E, F, G ]; end scanchain IN0 ["SDI0", "SFF1", "SFF2", A, B, C, D, E, F, G, "SDO0" ]; end scanstate # The notester_ready option has no effect with inversion_reference set to omit. { chain_test } IN0E0 := IN0G(XXXXXXXXX); IN0C0 := IN0G(000000000); IN0E1 := IN0G(000000000); IN0C1 := IN0G(111100000); IN0E2 := IN0G(111100000); IN0C2 := IN0G(000001111); IN0E3 := IN0G(000001111); IN0C3 := IN0G(111111111); { scan_test } IN0U0 := IN0G(XXXXXXXXX); IN0L0 := IN0G(011110000); IN0U1 := IN0G(011110000); IN0L1 := IN0G(100001111); IN0U2 := IN0G(111000111); IN0L2 := IN0G(110000011); IN0U3 := IN0G(001111100); IN0L3 := IN0G(000000111); end pattern group_ALL ("InData[1]", "InData[0]", "BidData[1]":I, "BidData[0]":I, "En", "Sclk", "SDI0", "SEN", "BidData[1]":O, "BidData[0]":O, "OutData", "SDO0") { test_setup } vector("_default_WFT_") := [ X X X X 1 0 X 0 - - X X ]; { chain_test } { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0E0], input [IN0:IN0C0]; { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0E1], input [IN0:IN0C1]; { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0E2], input [IN0:IN0C2]; { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0E3], input [IN0:IN0C3]; {IDDQ} { scan_test } { pattern 0 } { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0U0], input [IN0:IN0L0]; { capture } vector("_default_WFT_") := [ 0 1 - - 0 0 0 0 X X X X ]; vector("_default_WFT_") := [ 0 1 - - 0 0 0 0 1 0 1 0 ]; { pattern 1 } { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0U1], input [IN0:IN0L1]; { capture_Sclk } vector("_default_WFT_") := [ 1 1 - - 0 0 1 0 X X X X ]; vector("_default_WFT_") := [ 1 1 - - 0 0 1 0 1 0 1 1 ]; vector("_default_WFT_") := [ 1 1 - - 0 1 1 0 X X X X ]; {IDDQ} { pattern 2 } { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; scan("_scannnn_WFT_") := [ X X X X 1 1 - 1 - - X - ], output [IN0:IN0U2], input [IN0:IN0L2]; { capture_Sclk } vector("_default_WFT_") := [ 0 0 - - 0 0 1 0 X X X X ]; vector("_default_WFT_") := [ 0 0 - - 0 0 1 0 0 1 0 1 ]; vector("_default_WFT_") := [ 0 0 - - 0 1 1 0 X X X X ]; {IDDQ} { load_unload } vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; scan("_scannnn_WFT_") := [ 0 X X X 1 1 - 1 - - X - ], output [IN0:IN0U3], input [IN0:IN0L3]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 1 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 1 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X X ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - X 1 ]; vector("_default_WFT_") := [ X X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 X X X 1 0 X 1 - - 0 1 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 0 0 ]; vector("_default_WFT_") := [ 1 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 0 ]; vector("_default_WFT_") := [ 0 0 X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 1 ]; vector("_default_WFT_") := [ 0 X X X 1 0 X 1 - - 1 X ]; end end X X X X ]; vector("_default_WFT_") := [ 0 0 - - 0 0 1 0 0 1 0 1 ]; vINTERFACES/QSTAR/WGL/exp2.vtran000064400001440000012000000042621103104161000165750ustar00jcosleystaff00000400000023{ #======================================================================# # Translation: WGL < to > WGL with Q-Star IDDQ test control insertion # # Original File: "exp2.wgl" # # Target File: "exp2_out.wgl" # # Command File: "exp2.vtran" # # Author: SOURCE III, Inc. # # VTRAN 8.1 (C) 2008 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. It also specifies the Q-Star parameters # # for inserting control vectors for the QD1011 IDDQ test H/W # #======================================================================# } ovf_block begin orig_file = "exp2.wgl"; comments on; tabular_format wgl -cycle -scan -keep_annotations -include_cells ; QStar Product = "QD1011HC24" , ComTest = "Y" , Sample = "4" , GRef = "D 10A, 20A" , Keyword = "IDDQ", MemRead = "Y 5", Mode = "2" ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing for translations # # There is no processing necessary for WGL-to-WGL flow. # #======================================================================# } proc_block begin end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin simulator WGL addresselement="cyclenumber", addresselement="time"; target_file = "exp2_out.wgl"; end end INTERFACES/QSTAR/WGL/exp3.vtran000064400001440000012000000047671103104161000166100ustar00jcosleystaff00000400000023{ #======================================================================# # Translation: WGL < to > FLEX # # Original File: "exp1.wgl" # # Target File: "exp1.flex " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin comments ON; orig_file "exp2.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan -keep_annotations -include_cells; Q-star Product = "QD1011" , ComTest = "Y" , Sample = "4" , Readout = "A SV" , Keyword = "IDDQ", Mode = "1" ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'FLEX' #### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; TESTER_FORMAT TERADYNE -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp3" ; {#### OUTPUT FORMAT ####} target_file "exp3.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/QSTAR/WGL/exp4.vtran000064400001440000012000000047051103104161000166010ustar00jcosleystaff00000400000023{ #======================================================================# # Translation: WGL < to > HP93K # # Original File: "exp4.wgl" # # Target File: "exp4.avc" # # Command File: "exp4.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin comments ON; orig_file "exp2.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan -keep_annotations -include_cells; Q-star Product = "QD1011HCLite" , ComTest = "N" , Sample = "16" , Readout = "A SV" , Keyword = "IDDQ", Mode = "1" ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into 93K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'93K' #### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'M', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; tester_format hp93000 -auto_group DVC_FILE = "exp4.dvc"; {#### OUTPUTF ORMAT ####} target_file "exp4.avc"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/QSTAR/WGL/exp2_out.wgl000064400001440000012000001427001103104161000171230ustar00jcosleystaff00000400000023 # Translation Date: Wed Feb 27 17:08:28 2008 # VTRAN Version: 8.1 waveform TMDEMO240C signal Q_MD : input ; Q_CLK : input ; Q_DOUT : output ; InData[1..0] : input ; BidData[1..0] : bidir ; OutData : output ; En : input ; Sclk : input ; SDI0 : input ; SDO0 : output ; SEN : input ; end timeplate _default_WFT_ period 100NS Q_MD := input[0PS:S]; Q_CLK := input[0PS:S]; Q_DOUT := output[0PS:X, 50NS:Q'edge]; InData[1] := input[0PS:S]; InData[0] := input[0PS:S]; BidData[1] := input[0PS:S]; BidData[1] := output[0PS:X, 40NS:Q'edge]; BidData[0] := input[0PS:S]; BidData[0] := output[0PS:X, 40NS:Q'edge]; OutData := output[0PS:X, 40NS:Q'edge]; En := input[0PS:S]; Sclk := input[0PS:D, 50NS:S, 80NS:D]; SDI0 := input[0PS:S]; SDO0 := output[0PS:X, 40NS:Q'edge]; SEN := input[0PS:S]; end timeplate _scannnn_WFT_ period 80NS Q_MD := input[0PS:S]; Q_CLK := input[0PS:S]; Q_DOUT := output[0PS:X, 40NS:Q'edge]; InData[1] := input[0PS:S]; InData[0] := input[0PS:S]; BidData[1] := input[0PS:S]; BidData[1] := output[0PS:X, 40NS:Q'edge]; BidData[0] := input[0PS:S]; BidData[0] := output[0PS:X, 40NS:Q'edge]; OutData := output[0PS:X, 40NS:Q'edge]; En := input[0PS:S]; Sclk := input[0PS:D, 50NS:S, 70NS:D]; SDI0 := input[0PS:S]; SDO0 := output[0PS:X, 40NS:Q'edge]; SEN := input[0PS:S]; end scancell "SFF1" ; "SFF2" ; "A" ; "B" ; "C" ; "D" ; "E" ; "F" ; "G" ; end scanchain IN0 [SDI0, "SFF1", "SFF2", "A", "B", "C", "D", "E", "F", "G", SDO0]; end scanstate IN0I1 := IN0(000000000); IN0O1 := IN0(XXXXXXXXX); IN0I2 := IN0(111100000); IN0O2 := IN0(000000000); IN0I3 := IN0(000001111); IN0O3 := IN0(111100000); IN0I4 := IN0(111111111); IN0O4 := IN0(000001111); IN0I5 := IN0(011110000); IN0O5 := IN0(XXXXXXXXX); IN0I6 := IN0(100001111); IN0O6 := IN0(011110000); IN0I7 := IN0(110000011); IN0O7 := IN0(111000111); IN0I8 := IN0(000000111); IN0O8 := IN0(001111100); end pattern group_ALL (Q_MD, Q_CLK, Q_DOUT, InData, BidData, OutData, En, Sclk, SDI0, SDO0, SEN) # ---insert ComTest vectors here repeat 50 vector(0, 0nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(1, 5000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(2, 6000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(3, 7000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 20 vector(4, 8000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(5, 10000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(6, 11000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(7, 12000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(8, 13000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(9, 14000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(10, 15000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(11, 16000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(12, 17000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(13, 18000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(14, 19000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(15, 20000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(16, 21000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(17, 22000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(18, 23000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(19, 24000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(20, 25000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(21, 26000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(22, 27000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(23, 28000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(24, 29000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(25, 30000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(26, 31000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(27, 32000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(28, 33000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 100 vector(29, 34000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(30, 44000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(31, 45000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(32, 46000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 20 vector(33, 47000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(34, 49000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(35, 49900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(36, 50000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(37, 50900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(38, 51000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(39, 51900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(40, 52000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(41, 52900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(42, 53000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(43, 53900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(44, 54000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(45, 54900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(46, 55000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(47, 55900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(48, 56000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(49, 56900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(50, 57000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(51, 57900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(52, 58000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(53, 58900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(54, 59000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(55, 59900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(56, 60000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(57, 60900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(58, 61000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(59, 61900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(60, 62000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(61, 62900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(62, 63000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(63, 63900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(64, 64000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(65, 64900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(66, 65000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(67, 65900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(68, 66000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(69, 66900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(70, 67000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(71, 67900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(72, 68000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(73, 68900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(74, 69000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(75, 69900nS, _default_WFT_) := [ 1 1 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(76, 70000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(77, 70900nS, _default_WFT_) := [ 1 0 1 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(78, 71000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; vector(79, 71900nS, _default_WFT_) := [ 1 1 0 00 --XX X 0 0 0 X 0 ]; repeat 9 vector(80, 72000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; vector(81, 72900nS, _default_WFT_) := [ 1 0 0 00 --XX X 0 0 0 X 0 ]; repeat 40 vector(82, 73000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; # ---insert Mode vectors here repeat 40 vector(83, 77000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(84, 81000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(85, 82000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(86, 83000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 20 vector(87, 84000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(88, 86000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(89, 87000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 40 vector(90, 88000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; # ---insert Sample vectors here repeat 30 vector(91, 92000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(92, 95000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(93, 96000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(94, 97000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 20 vector(95, 98000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(96, 100000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(97, 101000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(98, 102000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(99, 103000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 40 vector(100, 104000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; # ---insert DVRef vectors here repeat 50 vector(101, 108000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(102, 113000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(103, 114000nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(104, 115000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 20 vector(105, 116000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(106, 118000nS, _default_WFT_) := [ 0 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(107, 119000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(108, 120000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(109, 121000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(110, 122000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(111, 123000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(112, 124000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(113, 125000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(114, 126000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(115, 127000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(116, 128000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(117, 129000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(118, 130000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(119, 131000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(120, 132000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(121, 133000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(122, 134000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(123, 135000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(124, 136000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(125, 137000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(126, 138000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(127, 139000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(128, 140000nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(129, 141000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 12 vector(130, 142000nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(131, 143200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(132, 144200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(133, 145200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(134, 146200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(135, 147200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(136, 148200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(137, 149200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(138, 150200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(139, 151200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(140, 152200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(141, 153200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(142, 154200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(143, 155200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(144, 156200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(145, 157200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(146, 158200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(147, 159200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(148, 160200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(149, 161200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(150, 162200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(151, 163200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(152, 164200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(153, 165200nS, _default_WFT_) := [ 1 1 X 00 --XX X 0 0 0 X 0 ]; repeat 10 vector(154, 166200nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 0 X 0 ]; repeat 40 vector(155, 167200nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 0 X 0 ]; # test_setup vector(156, 171200nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 0 ]; # chain_test # load_unload vector(157, 171300nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(158, 171400nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I1], output [IN0:IN0O1]; # load_unload vector(167, 172120nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(168, 172220nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I2], output [IN0:IN0O2]; # load_unload vector(177, 172940nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(178, 173040nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I3], output [IN0:IN0O3]; # load_unload vector(187, 173760nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(188, 173860nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I4], output [IN0:IN0O4]; # ---insert Measure IDDQ vectors here repeat 125 vector(197, 174580nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 0 1 X 1 ]; repeat 1888 vector(198, 184580nS, _scannnn_WFT_) := [ 0 0 X XX XX-- X 1 0 1 X 1 ]; repeat 12 vector(199, 335620nS, _scannnn_WFT_) := [ 0 0 X XX XX-- X 1 0 1 X 1 ]; vector(200, 336580nS, _scannnn_WFT_) := [ 0 0 1 XX XX-- X 1 0 1 X 1 ]; repeat 63 vector(201, 336660nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 0 1 X 1 ]; # IDDQ # scan_test # pattern 0 # load_unload vector(202, 341700nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(203, 341800nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I5], output [IN0:IN0O5]; # capture vector(212, 342520nS, _default_WFT_) := [ 1 0 X 01 --XX X 0 0 0 X 0 ]; vector(213, 342620nS, _default_WFT_) := [ 1 0 X 01 --10 1 0 0 0 0 0 ]; # pattern 1 # load_unload vector(214, 342720nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(215, 342820nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I6], output [IN0:IN0O6]; # capture_Sclk vector(224, 343540nS, _default_WFT_) := [ 1 0 X 11 --XX X 0 0 1 X 0 ]; vector(225, 343640nS, _default_WFT_) := [ 1 0 X 11 --10 1 0 0 1 1 0 ]; vector(226, 343740nS, _default_WFT_) := [ 1 0 X 11 --XX X 0 1 1 X 0 ]; # ---insert Measure IDDQ vectors here repeat 100 vector(227, 343840nS, _default_WFT_) := [ 1 0 X 11 --XX X 0 0 1 X 0 ]; repeat 1510 vector(228, 353840nS, _default_WFT_) := [ 0 0 X 11 --XX X 0 0 1 X 0 ]; repeat 9 vector(229, 504840nS, _default_WFT_) := [ 0 0 X 11 --XX X 0 0 1 X 0 ]; vector(230, 505740nS, _default_WFT_) := [ 0 0 1 11 --XX X 0 0 1 X 0 ]; repeat 50 vector(231, 505840nS, _default_WFT_) := [ 1 0 X 11 --XX X 0 0 1 X 0 ]; # IDDQ # pattern 2 # load_unload vector(232, 510840nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; scan(233, 510940nS, _scannnn_WFT_) := [ 1 0 X XX XX-- X 1 1 - - 1 ], input [IN0:IN0I7], output [IN0:IN0O7]; # capture_Sclk vector(242, 511660nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 1 X 0 ]; vector(243, 511760nS, _default_WFT_) := [ 1 0 X 00 --01 0 0 0 1 1 0 ]; vector(244, 511860nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 1 1 X 0 ]; # ---insert Measure IDDQ vectors here repeat 100 vector(245, 511960nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 1 X 0 ]; repeat 1510 vector(246, 521960nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 1 X 0 ]; repeat 9 vector(247, 672960nS, _default_WFT_) := [ 0 0 X 00 --XX X 0 0 1 X 0 ]; vector(248, 673860nS, _default_WFT_) := [ 0 0 1 00 --XX X 0 0 1 X 0 ]; repeat 50 vector(249, 673960nS, _default_WFT_) := [ 1 0 X 00 --XX X 0 0 1 X 0 ]; # IDDQ # load_unload vector(250, 678960nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(251, 679060nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(252, 679160nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(253, 679260nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(254, 679360nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(255, 679460nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(256, 679560nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(257, 679660nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(258, 679760nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(259, 679860nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(260, 679960nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(261, 680060nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(262, 680160nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; scan(263, 680260nS, _scannnn_WFT_) := [ 1 0 X 0X XX-- X 1 1 - - 1 ], input [IN0:IN0I8], output [IN0:IN0O8]; vector(272, 680980nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(273, 681080nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(274, 681180nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(275, 681280nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(276, 681380nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(277, 681480nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(278, 681580nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(279, 681680nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(280, 681780nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(281, 681880nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(282, 681980nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(283, 682080nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(284, 682180nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(285, 682280nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(286, 682380nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(287, 682480nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(288, 682580nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(289, 682680nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(290, 682780nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(291, 682880nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(292, 682980nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(293, 683080nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(294, 683180nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(295, 683280nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(296, 683380nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(297, 683480nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(298, 683580nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(299, 683680nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(300, 683780nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(301, 683880nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(302, 683980nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(303, 684080nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(304, 684180nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(305, 684280nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(306, 684380nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(307, 684480nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(308, 684580nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(309, 684680nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(310, 684780nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(311, 684880nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(312, 684980nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(313, 685080nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(314, 685180nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(315, 685280nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(316, 685380nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(317, 685480nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(318, 685580nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(319, 685680nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(320, 685780nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(321, 685880nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(322, 685980nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(323, 686080nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(324, 686180nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(325, 686280nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(326, 686380nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(327, 686480nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(328, 686580nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(329, 686680nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(330, 686780nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(331, 686880nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(332, 686980nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(333, 687080nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(334, 687180nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(335, 687280nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(336, 687380nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(337, 687480nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(338, 687580nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(339, 687680nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(340, 687780nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(341, 687880nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(342, 687980nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(343, 688080nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(344, 688180nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(345, 688280nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(346, 688380nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(347, 688480nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(348, 688580nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(349, 688680nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(350, 688780nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(351, 688880nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(352, 688980nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(353, 689080nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(354, 689180nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(355, 689280nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(356, 689380nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(357, 689480nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(358, 689580nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(359, 689680nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(360, 689780nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(361, 689880nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(362, 689980nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(363, 690080nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(364, 690180nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(365, 690280nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(366, 690380nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(367, 690480nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(368, 690580nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(369, 690680nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(370, 690780nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(371, 690880nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(372, 690980nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(373, 691080nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(374, 691180nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(375, 691280nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(376, 691380nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(377, 691480nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(378, 691580nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(379, 691680nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(380, 691780nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(381, 691880nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(382, 691980nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(383, 692080nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(384, 692180nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(385, 692280nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(386, 692380nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(387, 692480nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(388, 692580nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(389, 692680nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(390, 692780nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(391, 692880nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(392, 692980nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(393, 693080nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(394, 693180nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(395, 693280nS, _default_WFT_) := [ 1 0 X 00 XX-- 0 1 0 X 0 1 ]; vector(396, 693380nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(397, 693480nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(398, 693580nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 1 1 ]; vector(399, 693680nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(400, 693780nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(401, 693880nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(402, 693980nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(403, 694080nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(404, 694180nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(405, 694280nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(406, 694380nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(407, 694480nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(408, 694580nS, _default_WFT_) := [ 1 0 X 11 XX-- 0 1 0 X 0 1 ]; vector(409, 694680nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(410, 694780nS, _default_WFT_) := [ 1 0 X 01 XX-- 1 1 0 X 0 1 ]; vector(411, 694880nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(412, 694980nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(413, 695080nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(414, 695180nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; vector(415, 695280nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X X 1 ]; vector(416, 695380nS, _default_WFT_) := [ 1 0 X XX XX-- X 1 0 X 1 1 ]; vector(417, 695480nS, _default_WFT_) := [ 1 0 X XX XX-- 0 1 0 X 1 1 ]; vector(418, 695580nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(419, 695680nS, _default_WFT_) := [ 1 0 X 1X XX-- 0 1 0 X 1 1 ]; vector(420, 695780nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(421, 695880nS, _default_WFT_) := [ 1 0 X 10 XX-- 0 1 0 X 0 1 ]; vector(422, 695980nS, _default_WFT_) := [ 1 0 X 10 XX-- 1 1 0 X 0 1 ]; vector(423, 696080nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 0 1 ]; vector(424, 696180nS, _default_WFT_) := [ 1 0 X 00 XX-- 1 1 0 X 1 1 ]; vector(425, 696280nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(426, 696380nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X 1 1 ]; vector(427, 696480nS, _default_WFT_) := [ 1 0 X 0X XX-- 1 1 0 X X 1 ]; # ---insert MemRead read vectors here repeat 50 vector(428, 696580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(429, 701580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(430, 702580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(431, 703580nS, _default_WFT_) := [ 0 1 X 0X XX-- X 1 0 X X 1 ]; repeat 20 vector(432, 704580nS, _default_WFT_) := [ 0 0 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(433, 706580nS, _default_WFT_) := [ 0 1 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(434, 707580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 10 vector(435, 708580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(436, 709580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(437, 710480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(438, 710580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(439, 711480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(440, 711580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(441, 712480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(442, 712580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(443, 713480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(444, 713580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(445, 714480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(446, 714580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(447, 715480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(448, 715580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(449, 716480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(450, 716580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(451, 717480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(452, 717580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(453, 718480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(454, 718580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(455, 719480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(456, 719580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(457, 720480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(458, 720580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(459, 721480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(460, 721580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(461, 722480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(462, 722580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(463, 723480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(464, 723580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(465, 724480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(466, 724580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(467, 725480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(468, 725580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(469, 726480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(470, 726580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(471, 727480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(472, 727580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(473, 728480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(474, 728580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(475, 729480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(476, 729580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(477, 730480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(478, 730580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(479, 731480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(480, 731580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(481, 732480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(482, 732580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(483, 733480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; # ---insert MemRead read vectors loop start repeat 10 vector(484, 733580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(485, 734580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(486, 735480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(487, 735580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(488, 736480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(489, 736580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(490, 737480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(491, 737580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(492, 738480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(493, 738580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(494, 739480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(495, 739580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(496, 740480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(497, 740580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(498, 741480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(499, 741580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(500, 742480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(501, 742580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(502, 743480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(503, 743580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(504, 744480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(505, 744580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(506, 745480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(507, 745580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(508, 746480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(509, 746580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(510, 747480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(511, 747580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(512, 748480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(513, 748580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(514, 749480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(515, 749580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(516, 750480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(517, 750580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(518, 751480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(519, 751580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(520, 752480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(521, 752580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(522, 753480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(523, 753580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(524, 754480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(525, 754580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(526, 755480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(527, 755580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(528, 756480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(529, 756580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(530, 757480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(531, 757580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(532, 758480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; # ---insert MemRead read vectors loop end repeat 10 vector(533, 758580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(534, 759580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(535, 760480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(536, 760580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(537, 761480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(538, 761580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(539, 762480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(540, 762580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(541, 763480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(542, 763580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(543, 764480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(544, 764580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(545, 765480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(546, 765580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(547, 766480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(548, 766580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(549, 767480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(550, 767580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(551, 768480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(552, 768580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(553, 769480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(554, 769580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(555, 770480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(556, 770580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(557, 771480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(558, 771580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(559, 772480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(560, 772580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(561, 773480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(562, 773580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(563, 774480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(564, 774580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(565, 775480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(566, 775580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(567, 776480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(568, 776580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(569, 777480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(570, 777580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(571, 778480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(572, 778580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(573, 779480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(574, 779580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(575, 780480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(576, 780580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(577, 781480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(578, 781580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(579, 782480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(580, 782580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(581, 783480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; # ---insert MemRead read vectors loop end repeat 10 vector(582, 783580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(583, 784580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(584, 785480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(585, 785580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(586, 786480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(587, 786580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(588, 787480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(589, 787580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(590, 788480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(591, 788580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(592, 789480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(593, 789580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(594, 790480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(595, 790580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(596, 791480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(597, 791580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(598, 792480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(599, 792580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(600, 793480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(601, 793580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(602, 794480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(603, 794580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(604, 795480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(605, 795580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(606, 796480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(607, 796580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(608, 797480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(609, 797580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(610, 798480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(611, 798580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(612, 799480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(613, 799580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(614, 800480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(615, 800580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(616, 801480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(617, 801580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(618, 802480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(619, 802580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(620, 803480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(621, 803580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(622, 804480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(623, 804580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(624, 805480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(625, 805580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(626, 806480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(627, 806580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(628, 807480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(629, 807580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(630, 808480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; # ---insert MemRead read vectors loop end repeat 10 vector(631, 808580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(632, 809580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(633, 810480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(634, 810580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(635, 811480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(636, 811580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(637, 812480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(638, 812580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(639, 813480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(640, 813580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(641, 814480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(642, 814580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(643, 815480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(644, 815580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(645, 816480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(646, 816580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(647, 817480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(648, 817580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(649, 818480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(650, 818580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(651, 819480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(652, 819580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(653, 820480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(654, 820580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(655, 821480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(656, 821580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(657, 822480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(658, 822580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(659, 823480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(660, 823580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(661, 824480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(662, 824580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(663, 825480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(664, 825580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(665, 826480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(666, 826580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(667, 827480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(668, 827580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(669, 828480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(670, 828580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(671, 829480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(672, 829580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(673, 830480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(674, 830580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; vector(675, 831480nS, _default_WFT_) := [ 1 0 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(676, 831580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vector(677, 832480nS, _default_WFT_) := [ 1 1 1 0X XX-- X 1 0 X X 1 ]; repeat 9 vector(678, 832580nS, _default_WFT_) := [ 0 0 X 0X XX-- X 1 0 X X 1 ]; vector(679, 833480nS, _default_WFT_) := [ 0 0 1 0X XX-- X 1 0 X X 1 ]; repeat 40 vector(680, 833580nS, _default_WFT_) := [ 1 0 X 0X XX-- X 1 0 X X 1 ]; end end 7580nS, _default_WFT_) := [ 1 1 X 0X XX-- X 1 0 X X 1 ]; vectoINTERFACES/QSTAR/STIL/000075500001440000012000000000001103104161000147615ustar00jcosleystaff00000400000023INTERFACES/QSTAR/STIL/exp1.vtran000064400001440000012000000014561103104161000167200ustar00jcosleystaff00000400000023ovf_block begin orig_file = "exp1.stil"; comments on; tabular_format stil -cycle -scan -keep_annotations -include_cells; QStar Product = "QD1011HC24" , ComTest = "Y" , Sample = "4" , GRef = "D 10A, 20A" , Keyword = "IDDQ", MemRead = "Y 5", Mode = "2" ; end proc_block begin state_trans inputs 'D'->'0', 'U'->'1'; state_trans outputs 'l'->'L', 'h'->'H'; end tvf_block begin title = "TMDEMO240C" ; resolution = 0.1; { #### .1ns resolution for times #### } tester_format STIL {#### OUTPUT VECTOR FILE ####} { -quote_names, #### quote all signal/cell/chain names #### } scanin_default = "^"; { #### pad short scan chains with first non-X char # ### } target_file = "exp1_out.stil"; end end INTERFACES/QSTAR/STIL/exp3.vtran000064400001440000012000000013261103104161000167160ustar00jcosleystaff00000400000023ovf_block begin orig_file = "exp1.stil"; comments on; tabular_format stil -cycle -scan -keep_annotations ; QStar Product = "QD1011HCLite" , ComTest = "Y" , Sample = "16" , GRef = "S 50mA" , MemRead = "N", Mode = "1" ; end proc_block begin state_trans inputs 'D'->'0', 'U'->'1', 'N'->'0', '?'->'0'; state_trans outputs 'l'->'L', 'h'->'H', '?'->'X'; end tvf_block begin title = "TMDEMO240C" ; resolution = 0.1; { #### .1ns resolution for times #### } TESTER_FORMAT TERADYNE -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp3" ; {#### OUTPUT FORMAT ####} target_file "exp3.flex"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/QSTAR/STIL/exp2.vtran000064400001440000012000000010661103104161000167160ustar00jcosleystaff00000400000023ovf_block begin orig_file = "exp1.stil"; comments on; tabular_format stil -cycle -scan -keep_annotations -include_cells; { QStar Product = "QD1011HC24" , ComTest = "Y" , Sample = "4" , GRef = "D 10A, 20A" , Keyword = "IDDQ", MemRead = "Y 5", Mode = "2" ; } end proc_block begin state_trans inputs 'D'->'0', 'U'->'1', 'N'->'X'; state_trans outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1'; end tvf_block begin simulator WGL addresselement="cyclenumber", addresselement="time"; target_file = "exp2.wgl"; end end INTERFACES/QSTAR/STIL/exp4.vtran000064400001440000012000000013001103104161000167070ustar00jcosleystaff00000400000023ovf_block begin orig_file = "exp1.stil"; comments on; tabular_format stil -cycle -scan -keep_annotations ; QStar Product = "QD1011HCLite" , ComTest = "N" , Sample = "16" , GRef = "N" , Readout = "A SV", MemRead = "N", Mode = "1" ; end proc_block begin state_trans inputs 'D'->'0', 'U'->'1', 'N'->'0', '?'->'0'; state_trans outputs 'l'->'L', 'h'->'H', '?'->'X', 'T'->'M'; end tvf_block begin title = "TMDEMO240C" ; resolution = 0.1; { #### .1ns resolution for times #### } tester_format hp93000 -auto_group DVC_FILE = "exp4.dvc"; {#### output timing file ####} target_file "exp4.avc"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/QSTAR/STIL/exp1.stil000064400001440000012000000300771103104161000165420ustar00jcosleystaff00000400000023STIL 1.0 ; Header { Title "TMDEMO240C" ; Date "Wed Feb 27 16:49:17 2008" ; Source "vtran version 8.1" ; } Signals { InData[1] In; InData[0] In; BidData[1] InOut; BidData[0] InOut; OutData Out; En In; Sclk In; SDI0 In { ScanIn; } SDO0 Out { ScanOut; } SEN In; } SignalGroups { Group_1 = 'InData[1] + InData[0] + En + Sclk + SDI0 + SEN'; Group_2 = 'BidData[1] + BidData[0]'; Group_3 = 'OutData + SDO0'; } Timing { WaveformTable _default_WFT_ { Period '100.0ns' ; Waveforms { InData[1] { 10ZN { '0.0ns' U/D/Z/N; } } InData[0] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[1] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[1] { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } BidData[0] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[0] { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } OutData { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } En { 10ZN { '0.0ns' U/D/Z/N; } } Sclk { 10ZN { '0.0ns' D; '50.0ns' U/D/Z/N; '80.0ns' D; } } SDI0 { 10ZN { '0.0ns' U/D/Z/N; } } SDO0 { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } SEN { 10ZN { '0.0ns' U/D/Z/N; } } } } WaveformTable _scannnn_WFT_ { Period '80.0ns' ; Waveforms { InData[1] { 10ZN { '0.0ns' U/D/Z/N; } } InData[0] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[1] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[1] { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } BidData[0] { 10ZN { '0.0ns' U/D/Z/N; } } BidData[0] { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } OutData { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } En { 10ZN { '0.0ns' U/D/Z/N; } } Sclk { 10ZN { '0.0ns' D; '50.0ns' U/D/Z/N; '70.0ns' D; } } SDI0 { 10ZN { '0.0ns' U/D/Z/N; } } SDO0 { HLXT { '0.0ns' X; '40.0ns' H/L/X/T; } } SEN { 10ZN { '0.0ns' U/D/Z/N; } } } } } ScanStructures { ScanChain IN0 { ScanLength 9 ; ScanIn SDI0 ; ScanOut SDO0 ; ScanCells SFF1 SFF2 A B C D E F G ; ScanInversion 0 ; } } PatternBurst "_burst_" { PatList { "_pattern_" { } } } PatternExec { PatternBurst "_burst_" ; } MacroDefs { "_scan_op_" { Shift { V { SDI0 = #; SDO0 = #; } } } } Pattern "_pattern_" { // test_setup W _default_WFT_; V { // 0.0 Group_1 = NN10N0; Group_2 = NN; Group_3 = XX; } // chain_test // load_unload V { // 100.0 Group_1 = NN10N1; } W _scannnn_WFT_; C { // 200.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 000000000; SDO0 = XXXXXXXXX; } // load_unload W _default_WFT_; V { // 920.0 Group_1 = NN10N1; } W _scannnn_WFT_; C { // 1020.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 000001111; SDO0 = LLLLLLLLL; } // load_unload W _default_WFT_; V { // 1740.0 Group_1 = NN10N1; Group_3 = XX; } W _scannnn_WFT_; C { // 1840.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 111100000; SDO0 = LLLLLHHHH; } // load_unload W _default_WFT_; V { // 2560.0 Group_1 = NN10N1; Group_3 = XX; } W _scannnn_WFT_; C { // 2660.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 111111111; SDO0 = HHHHLLLLL; } IddqTestPoint; // scan_test // pattern 0 // load_unload W _default_WFT_; V { // 3380.0 Group_1 = NN10N1; Group_3 = XX; } W _scannnn_WFT_; C { // 3480.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 000011110; SDO0 = XXXXXXXXX; } // capture W _default_WFT_; V { // 4200.0 Group_1 = 010000; Group_2 = ZZ; } V { // 4300.0 Group_2 = HL; Group_3 = HL; } // pattern 1 // load_unload V { // 4400.0 Group_1 = NN10N1; Group_2 = NN; Group_3 = XX; } W _scannnn_WFT_; C { // 4500.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 111100001; SDO0 = LLLLHHHHL; } // capture_Sclk W _default_WFT_; V { // 5220.0 Group_1 = 110010; Group_2 = ZZ; Group_3 = XX; } V { // 5320.0 Group_2 = HL; Group_3 = HH; } V { // 5420.0 Group_1 = 110110; Group_2 = ZZ; Group_3 = XX; } IddqTestPoint; // pattern 2 // load_unload V { // 5520.0 Group_1 = NN10N1; Group_2 = NN; } W _scannnn_WFT_; C { // 5620.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 110000011; SDO0 = HHHLLLHHH; } // capture_Sclk W _default_WFT_; V { // 6340.0 Group_1 = 000010; Group_2 = ZZ; Group_3 = XX; } V { // 6440.0 Group_2 = LH; Group_3 = LH; } V { // 6540.0 Group_1 = 000110; Group_2 = ZZ; Group_3 = XX; } IddqTestPoint; // load_unload V { // 6640.0 Group_1 = NN10N1; Group_2 = NN; } V { // 6740.0 Group_3 = XH; } V { // 6840.0 Group_3 = LH; } V { // 6940.0 Group_1 = 1N10N1; } V { // 7040.0 } V { // 7140.0 Group_1 = 1010N1; Group_3 = LL; } V { // 7240.0 } V { // 7340.0 Group_3 = HL; } V { // 7440.0 Group_1 = 0010N1; } V { // 7540.0 Group_3 = HH; } V { // 7640.0 Group_1 = 0N10N1; } V { // 7740.0 } V { // 7840.0 Group_3 = HX; } W _scannnn_WFT_; C { // 7940.0 Group_1 = 0N11Z1; Group_3 = XX; } Macro "_scan_op_" { SDI0 = 111000000; SDO0 = LLHHHHHLL; } W _default_WFT_; V { // 8660.0 Group_1 = NN10N1; Group_3 = XX; } V { // 8760.0 Group_3 = XH; } V { // 8860.0 Group_3 = LH; } V { // 8960.0 Group_1 = 1N10N1; } V { // 9060.0 } V { // 9160.0 Group_1 = 1010N1; Group_3 = LL; } V { // 9260.0 } V { // 9360.0 Group_3 = HL; } V { // 9460.0 Group_1 = 0010N1; } V { // 9560.0 Group_3 = HH; } V { // 9660.0 Group_1 = 0N10N1; } V { // 9760.0 } V { // 9860.0 Group_3 = HX; } V { // 9960.0 Group_1 = NN10N1; Group_3 = XX; } V { // 10060.0 Group_3 = XH; } V { // 10160.0 Group_3 = LH; } V { // 10260.0 Group_1 = 1N10N1; } V { // 10360.0 } V { // 10460.0 Group_1 = 1010N1; Group_3 = LL; } V { // 10560.0 } V { // 10660.0 Group_3 = HL; } V { // 10760.0 Group_1 = 0010N1; } V { // 10860.0 Group_3 = HH; } V { // 10960.0 Group_1 = 0N10N1; } V { // 11060.0 } V { // 11160.0 Group_3 = HX; } V { // 11260.0 Group_1 = NN10N1; Group_3 = XX; } V { // 11360.0 Group_3 = XH; } V { // 11460.0 Group_3 = LH; } V { // 11560.0 Group_1 = 1N10N1; } V { // 11660.0 } V { // 11760.0 Group_1 = 1010N1; Group_3 = LL; } V { // 11860.0 } V { // 11960.0 Group_3 = HL; } V { // 12060.0 Group_1 = 0010N1; } V { // 12160.0 Group_3 = HH; } V { // 12260.0 Group_1 = 0N10N1; } V { // 12360.0 } V { // 12460.0 Group_3 = HX; } V { // 12560.0 Group_1 = NN10N1; Group_3 = XX; } V { // 12660.0 Group_3 = XH; } V { // 12760.0 Group_3 = LH; } V { // 12860.0 Group_1 = 1N10N1; } V { // 12960.0 } V { // 13060.0 Group_1 = 1010N1; Group_3 = LL; } V { // 13160.0 } V { // 13260.0 Group_3 = HL; } V { // 13360.0 Group_1 = 0010N1; } V { // 13460.0 Group_3 = HH; } V { // 13560.0 Group_1 = 0N10N1; } V { // 13660.0 } V { // 13760.0 Group_3 = HX; } V { // 13860.0 Group_1 = NN10N1; Group_3 = XX; } V { // 13960.0 Group_3 = XH; } V { // 14060.0 Group_3 = LH; } V { // 14160.0 Group_1 = 1N10N1; } V { // 14260.0 } V { // 14360.0 Group_1 = 1010N1; Group_3 = LL; } V { // 14460.0 } V { // 14560.0 Group_3 = HL; } V { // 14660.0 Group_1 = 0010N1; } V { // 14760.0 Group_3 = HH; } V { // 14860.0 Group_1 = 0N10N1; } V { // 14960.0 } V { // 15060.0 Group_3 = HX; } V { // 15160.0 Group_1 = NN10N1; Group_3 = XX; } V { // 15260.0 Group_3 = XH; } V { // 15360.0 Group_3 = LH; } V { // 15460.0 Group_1 = 1N10N1; } V { // 15560.0 } V { // 15660.0 Group_1 = 1010N1; Group_3 = LL; } V { // 15760.0 } V { // 15860.0 Group_3 = HL; } V { // 15960.0 Group_1 = 0010N1; } V { // 16060.0 Group_3 = HH; } V { // 16160.0 Group_1 = 0N10N1; } V { // 16260.0 } V { // 16360.0 Group_3 = HX; } V { // 16460.0 Group_1 = NN10N1; Group_3 = XX; } V { // 16560.0 Group_3 = XH; } V { // 16660.0 Group_3 = LH; } V { // 16760.0 Group_1 = 1N10N1; } V { // 16860.0 } V { // 16960.0 Group_1 = 1010N1; Group_3 = LL; } V { // 17060.0 } V { // 17160.0 Group_3 = HL; } V { // 17260.0 Group_1 = 0010N1; } V { // 17360.0 Group_3 = HH; } V { // 17460.0 Group_1 = 0N10N1; } V { // 17560.0 } V { // 17660.0 Group_3 = HX; } V { // 17760.0 Group_1 = NN10N1; Group_3 = XX; } V { // 17860.0 Group_3 = XH; } V { // 17960.0 Group_3 = LH; } V { // 18060.0 Group_1 = 1N10N1; } V { // 18160.0 } V { // 18260.0 Group_1 = 1010N1; Group_3 = LL; } V { // 18360.0 } V { // 18460.0 Group_3 = HL; } V { // 18560.0 Group_1 = 0010N1; } V { // 18660.0 Group_3 = HH; } V { // 18760.0 Group_1 = 0N10N1; } V { // 18860.0 } V { // 18960.0 Group_3 = HX; } V { // 19060.0 Group_1 = NN10N1; Group_3 = XX; } V { // 19160.0 Group_3 = XH; } V { // 19260.0 Group_3 = LH; } V { // 19360.0 Group_1 = 1N10N1; } V { // 19460.0 } V { // 19560.0 Group_1 = 1010N1; Group_3 = LL; } V { // 19660.0 } V { // 19760.0 Group_3 = HL; } V { // 19860.0 Group_1 = 0010N1; } V { // 19960.0 Group_3 = HH; } V { // 20060.0 Group_1 = 0N10N1; } V { // 20160.0 } V { // 20260.0 Group_3 = HX; } V { // 20360.0 Group_1 = NN10N1; Group_3 = XX; } V { // 20460.0 Group_3 = XH; } V { // 20560.0 Group_3 = LH; } V { // 20660.0 Group_1 = 1N10N1; } V { // 20760.0 } V { // 20860.0 Group_1 = 1010N1; Group_3 = LL; } V { // 20960.0 Group_1 = 0010N1; } V { // 21060.0 Group_1 = 1010N1; Group_3 = HL; } V { // 21160.0 Group_1 = 0010N1; } V { // 21260.0 Group_1 = 1010N1; Group_3 = HH; } V { // 21360.0 Group_1 = 0N10N1; } V { // 21460.0 } V { // 21560.0 Group_3 = HX; } V { // 21660.0 Group_1 = NN10N1; Group_3 = XX; } V { // 21760.0 Group_3 = XH; } V { // 21860.0 Group_3 = LH; } V { // 21960.0 Group_1 = 1N10N1; } V { // 22060.0 } V { // 22160.0 Group_1 = 1010N1; Group_3 = LL; } V { // 22260.0 Group_1 = 1110N1; } V { // 22360.0 Group_1 = 1010N1; Group_3 = HL; } V { // 22460.0 Group_1 = 0110N1; } V { // 22560.0 Group_1 = 0010N1; Group_3 = HH; } V { // 22660.0 Group_1 = 0N10N1; } V { // 22760.0 } V { // 22860.0 Group_3 = HX; } V { // 22960.0 Group_1 = NN10N1; Group_3 = XX; } V { // 23060.0 Group_3 = XH; } V { // 23160.0 Group_3 = LH; } V { // 23260.0 Group_1 = 1N10N1; } V { // 23360.0 } V { // 23460.0 Group_1 = 1010N1; Group_3 = LL; } V { // 23560.0 } V { // 23660.0 Group_3 = HL; } V { // 23760.0 Group_1 = 0010N1; } V { // 23860.0 Group_3 = HH; } V { // 23960.0 Group_1 = 0N10N1; } V { // 24060.0 } V { // 24160.0 Group_3 = HX; } } Group_1 = 110110; Group_2 = ZZ; Group_3 = XX; } IddqTestPoint; // pattern 2 // load_unload V { // 5520.0 Group_1 = NN10N1; Group_2 = NN; } W _scannnn_WFT_; C { // 5620.0 Group_1 = NN11Z1; } Macro "_scan_op_" { SDI0 = 110000011; SDO0 = HHHLLLHHH; } // capture_Sclk W _default_WFT_; V { // 6340.0 Group_1 = 000010; Group_2 = ZZ; Group_3 = XX; } V { // 6INTERFACES/QSTAR/README000064400001440000012000000037521103104161000150750ustar00jcosleystaff00000400000023Q-Star ----- This main directory is "QSTAR" and the sub-directories are: -> WGL/ -> STIL/ The sub-directories provide examples of vtran translations from WGL and STIL to several formats in which test control vectors and signals are inserted into the source WGL or STIL file to support the Q-Star IDDQ test module family. The source WGL or STIL file will have been generated by an ATPG program specifically for IDDQ testing. The files will include Iddq testing point markers in the form of either a comment (for WGL) or a IddqTestPoint (for STIL). In order to instruct vtran to automatically insert these control vectors, a QSTAR statement block is added to the OVF_BLOCK in the vtran command file. This statement has the following syntax and parameter options: Q-Star Product = "QD1011 | QD1011HC24 | QD1011HCLite", [Keyword = "IDDQ_keyword",] { default is measureIDDQ for WGL } [Comtest = "Y | N",] [SF = "Y | N"], [Mode = "1 | 2",] [Sample = "1 | 4 | 16 | 256 | 1024",] [GRef = "N|S|D, value_1, [value_2]",] [VRef = "N|Y, [vec#, value_1 [,vec#, value_2]]",] [NoM = "N|Y, value",] [Readout = "N|A|S, [SV|DV,] [1,2,...N]",] [MemRead = "N|Y, [value]"] ; All of the paramters are optional except for the Product parameter which is required. All other parameters have default values which may depend on the Product specified. For the WGL flow, the Keyword parameter can be used to set the comment text used in the file to indicate the IDDQ test points. Note that not all combinations of parameter values are valid; refer to Q-Star product information for appropriate parameters. The sub-directories contain the following examples: WGL/ exp1.vtran WGL-to-WGL flow exp2.vtran WGL-to-WGL flow exp3.vtran WGL-to-FLEX flow exp4.vtran WGL-to-Agilent 93K flow STIL/ exp1.vtran STIL-to-STIL flow exp2.vtran STIL-to-WGL flow exp3.vtran STIL-to-FLEX flow exp4.vtran STIL-to-Agilent 93K flow INTERFACES/HP94K/000075500001440000012000000000001103104161000141135ustar00jcosleystaff00000400000023INTERFACES/HP94K/WGLHP94K/000075500001440000012000000000001103104161000152645ustar00jcosleystaff00000400000023INTERFACES/HP94K/WGLHP94K/exp1.vtran000064400001440000012000000051561103104161000172240ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > HP94K # # Original File: "exp1.wgl" # # Target File: "exp1.hp94k " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } { #### no -scan since HP94000 interface does not support scan #### } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into HP94K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'HP94K'#### } state_trans outputs '1'->'H', '0'->'L'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file = "exp1.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp1.dts" { #### name of the dts file #### } PIN_FILE = "exp1.pin" { #### name of the pin file #### } ; resolution = 0.01; end end e = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } { #### no -scan since HP94000 interface does not support scan #### } end { #======================================================================# # PROCESSING- BLOCK INTERFACES/HP94K/STILHP94K/000075500001440000012000000000001103104161000154065ustar00jcosleystaff00000400000023INTERFACES/HP94K/STILHP94K/exp1.vtran000064400001440000012000000052221103104161000173400ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > HP94K # # Original File: "exp1.stil" # # Target File: "exp1.hp94k" # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into HP94K format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'HP94K'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file = "exp1.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp1.dts" { #### name of the dts file #### } PIN_FILE = "exp1.pin" { #### name of the pin file #### } ; resolution = 0.01; end end INTERFACES/HP94K/VCDHP94K/000075500001440000012000000000001103104161000152475ustar00jcosleystaff00000400000023INTERFACES/HP94K/VCDHP94K/exp1.vtran000064400001440000012000000067661103104161000172170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > HP94K # # Original File: "exp1.vcd" # # Target File: "exp1.hp94k " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into HP94K format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN cycle 250; {4 MHz cycle} BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; check_window * @ 195, 200; { strobe all outs at 195 } { #### state character translations for 'VCD'->'HP94K'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file = "exp1.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp1.dts" { #### name of the dts file #### } PIN_FILE = "exp1.pin" { #### name of the pin file #### } ; resolution = 0.01; end end INTERFACES/HP94K/VCDHP94K/exp2.vtran000064400001440000012000000065501103104161000172070ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > HP94K # # Original File: "exp1.vcd" # # Target File: "exp2.hp94k " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into HP94K format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; Include "../../DATA/exp1.tcyc" { #### state character translations for 'VCD'->'HP94K'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file = "exp2.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp2.dts" { #### name of the dts file #### } PIN_FILE = "exp2.pin" { #### name of the pin file #### } ; resolution = 0.01; end end INTERFACES/HP94K/EVCDHP94K/000075500001440000012000000000001103104161000153545ustar00jcosleystaff00000400000023INTERFACES/HP94K/EVCDHP94K/exp1.vtran000064400001440000012000000101441103104161000173050ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > HP94K # # Original File: "exp1.evcd" # # Target File: "exp1.hp94k " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into HP94K format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'HP94K' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; target_file = "exp1.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp1.dts" { #### name of the dts file #### } PIN_FILE = "exp1.pin" { #### name of the pin file #### } ; resolution = 0.01; end INTERFACES/HP94K/EVCDHP94K/exp2.vtran000064400001440000012000000075511103104161000173160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > HP94K # # Original File: "exp1.evcd" # # Target File: "exp2.hp94k " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into HP94K format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'HP94K' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; target_file = "exp2.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp2.dts" { #### name of the dts file #### } PIN_FILE = "exp2.pin" { #### name of the pin file #### } ; resolution = 0.01; end INTERFACES/HP94K/README000064400001440000012000000103701103104161000147740ustar00jcosleystaff00000400000023HP94000 ------- The main directory is "HP94K" and the sub-directories are -> WGLHP94K -> VCDHP94K -> STILHP94K -> EVCDHP94K The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLHP94K" contains the translation of WGL file to HP94K output format. Sub-directory -> "EVCDHP94K" contains the translation of EVCD file to HP94K output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The initial tester interface for the HP94000 tester does not support scan data, so if translating from STIL or WGL files to HP94000, any scan data must be expanded (do not include the -scan flag in the TABULAR_FORMAT statement). This interface is invoked with the following statement and has the indicated optional parameters: TESTER_FORMAT HP94000, USE_TIMESET = "name", { force TSET to "name" - if missing uses timeplate or Waveform names in WGL/STIL input file } DTS_FILE = "name.dts", { creates a timing file "name.dts" } PIN_FILE = "name.pin", { creates a pin info file "name.pin" } TIME_STAMPS = "ON | OFF" { adds timestamp in comment field } ; The state characters typically used in the HP94000 format are: 0 Input logic 0 1 Input logic 1 Z Input tristate H Output logic 1 L Output logic 0 X Output don't care Use the STATE_TRANS statement to map state characters from the input vector data to these if they are different. The input file is exp1.wgl, and the three output HP94000 files are exp1.dts, exp1.pin and exp1.hp94 An example command file for an WGL -> HP94000 translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > HP94K # # Original File: "exp1.wgl" # # Target File: "exp1.hp94k " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle; {#### INPUT FORMAT ####} { #### no -scan since HP94000 interface does not support scan #### } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into HP94K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'HP94K'#### } state_trans outputs '1'->'H', '0'->'L'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file = "exp1.hp94k"; {#### OUTPUT VECTOR FILE ####} header 500; tester_format hp94000, {#### OUTPUT FORMAT ####} USE_TIMESET = "TSET", { #### name of the timeset to use #### } DTS_FILE = "exp1.dts" { #### name of the dts file #### } PIN_FILE = "exp1.pin" { #### name of the pin file #### } ; resolution = 0.01; end end ################################################################################ INTERFACES/IMS/000075500001440000012000000000001103104161000137445ustar00jcosleystaff00000400000023INTERFACES/IMS/WGLIMS/000075500001440000012000000000001103104161000147465ustar00jcosleystaff00000400000023INTERFACES/IMS/WGLIMS/exp3.vtran000064400001440000012000000046201103104161000167030ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > IMS # # Original File: "exp1.wgl" # # Target File: "exp3.ims " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.wgl; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'IMS'#### } state_trans 'P'->'^', '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp3.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "300" , TIME_STAMPS = "10" TERMINATE = "HALT" DRIVE = "200mV,3.50V,9", ACTIVE = "Off,0nA,0nA,1.40V", THRESHOLD = "1.00V,2.00V" ; end; end; INTERFACES/IMS/WGLIMS/exp1.vtran000064400001440000012000000050051103104161000166770ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > IMS # # Original File: "exp1.wgl" # # Target File: "exp1.ims " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.wgl; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'IMS'#### } state_trans 'P'->'^', '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp1.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "300" , REPEAT_THRESHOLD = "2", TIME_STAMPS = "10" TERMINATE = "HALT" DRIVE = "200mV,3.50V,9", ACTIVE = "Off,0nA,0nA,1.40V", THRESHOLD = "1.00V,2.00V" ; end; end; INTERFACES/IMS/WGLIMS/exp2.vtran000064400001440000012000000046121103104161000167030ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > IMS # # Original File: "exp1.wgl" # # Target File: "exp2.ims " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.wgl; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'IMS'#### } state_trans 'P'->'^', '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp2.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "300" , TIME_STAMPS = "10" TERMINATE = "HALT" DRIVE = "200mV,3.50V,9", ACTIVE = "Off,0nA,0nA,1.40V", THRESHOLD = "1.00V,2.00V" ; end; end; INTERFACES/IMS/STILIMS/000075500001440000012000000000001103104161000150705ustar00jcosleystaff00000400000023INTERFACES/IMS/STILIMS/exp2.vtran000064400001440000012000000050531103104161000170250ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > IMS # # Original File: "exp1.stil" # # Target File: "exp2.ims " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.stil; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'IMS'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X', 'P'->'^'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'Z', 'l'->'0', 'h'->'1', 't'->'Z', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp2.ims ; {#### OUTPUT FILES (exp2.ims, exp2.set) ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "2" , TIME_STAMPS = "10" , { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; end; INTERFACES/IMS/STILIMS/exp1.vtran000064400001440000012000000051411103104161000170220ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > IMS # # Original File: "exp1.stil" # # Target File: "exp1.ims " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.stil; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'IMS'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X', 'P'->'^'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'Z', 'l'->'0', 'h'->'1', 't'->'Z', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp1; {#### BASE OUTPUT FILE NAME (exp1.mem, exp1.set) ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; end; INTERFACES/IMS/STILIMS/exp3.vtran000064400001440000012000000050631103104161000170270ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > IMS # # Original File: "exp1.stil" # # Target File: "exp3.ims " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file ../../DATA/exp1.stil; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle -scan -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'IMS'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X', 'P'->'^'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'Z', 'l'->'0', 'h'->'1', 't'->'Z', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp3.ims ; {#### OUTPUT FILES exp3.ims, exp3.set ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "2", TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; end; ======================# # This is vtran command file. # # Translation: STIL < to > IMS # # Original File: "exp1.stil" # # Target File: "exp3.ims " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" #INTERFACES/IMS/STILIMS/log000064400001440000012000000204561103104161000156030ustar00jcosleystaff00000400000023 VTRAN 8.0.1 (C) 2007 Source III, Inc. Reading command file... Processing command file OVF_BLOCK... Using VREAD to read stil formatted file .... Loading STIL file.....complete. Size = 3769 Parsing STIL file.....complete. Generating vector data... stil file successfully read. get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 Original Vector File successfully loaded. Processing command file TVF_BLOCK... Formatting Target Vector File in IMS mem format... get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 get_nln(): LOOP_param=-1, next_LOOP_param=-1 INVOKE get_nln: LOOP_param = -1, next_LOOP_param = -1 IMS_FMT: generating term [2] (end_flag=1) IMS_FMT: generating term [5] (end_flag=1) Translation complete. No errors detected. Output in file: exp2.ims INTERFACES/IMS/STILIMS/exp2.ims000064400001440000012000000027541103104161000164700ustar00jcosleystaff00000400000023Rem Rem Converted by vtran version: 8.0.1 Rem Date: Thu Nov 8 14:07:13 2007 Rem Source file: ../../DATA/exp1.stil Rem Rem Rem Group1A BIN Force Rem in0 Rem in1 Rem in2 Rem Group1B BIN Force Rem clk1 Rem clk2 Rem Group1C BIN Force Rem SDI0 Rem SDI1 Rem Group1D BIN Force Rem ACK0 Rem Group1E BIN Force Rem BCK0 Rem Group1F BIN Compare Rem out0 Rem out1 Rem out2 Rem SDO0 Rem SDO1 Rem Group1A Group1B Group1C Group1D Group1E Group1F Rem Rem Init Memory MEM 0, #TXT Rem Sequence 0 at 0.000ns NNN 00 NN 0 0XXXXX NNN 00 00 1 1XXXXX : Repeat 2 Times NNN 00 10 1 1XXXXX NNN 00 01 1 1XXXXX 010 00 11 0 0XXXXX 100 00 10 0 0XXXXX NNN 00 NN 0 1XXXXX : Repeat 12 Times NNN 11 NN 0 0XXXXX NNN 01 NN 0 1XXXXX 100 00 10 0 0XXXXX Rem Sequence 10 at 2180.000ns NNN 00 NN 0 1XXXXX NNN 01 NN 1 1XXXXX NNN 10 NN 0 1XXXXX NNN 01 NN 0 1XXXXX 100 00 10 0 0XXXXX NNN 00 NN 0 1XXXXX NNN 01 NN 1 1XXXXX NNN 10 NN 0 1XXXXX NNN 01 NN 0 1XXXXX 100 00 10 0 0XXXXX Rem Sequence 20 at 3160.000ns NNN 00 NN 0 1XXXXX NNN 01 NN 1 1XXXXX NNN 10 NN 0 1XXXXX NNN 01 NN 0 1XXXXX 100 00 10 0 0XXXXX NNN 00 NN 0 1XXXXX NNN 01 NN 1 1XXXXX NNN 10 NN 0 1XXXXX NNN 01 NN 0 1XXXXX 100 00 10 0 0XXXXX Rem Sequence 30 at 4140.000ns NNN 00 NN 0 1XXXXX NNN 01 NN 1 1XXXXX NNN 10 NN 0 1XXXXX NNN 01 NN 0 1XXXXX 100 00 00 1 1XXXXX : Repeat 2 Times 100 00 00 1 1XXX1X 100 00 00 1 1XXX0X NNN 01 NN 1 1XXXXX : Repeat 3 Times NNN 01 NN 0 1XXXXX : HALT NNN 01 NN 0 0XXXXX : HALT MEM End INTERFACES/IMS/STILIMS/exp2.set000064400001440000012000000121201103104161000164570ustar00jcosleystaff00000400000023Set Settings #TXT Rem Rem Converted by vtran version: 8.0.1 Rem Date: Thu Nov 8 14:07:13 2007 Rem Source file: ../../DATA/exp1.stil Rem Rem Init All Event 0=User0, Off Event 1=User1, Off Event 2=STM-2, Off Event 3=Error, On Rem ***** Socket and Config info here Rem Rem ***** Testconditions info here Rem Rem Rem TimeSet TS1 ******** Clk Internal,90.000ns Resource Group1A=Force #TXT 4, in0 5, in1 6, in2 Resource End Radix Group1A=Bin Polarity Group1A=Positive Format Group1A=DNRZ,0.000ns,Timing,1,Reset Drive Group1A=200mV,3.50V,9 Resource Group1B=Force #TXT 7, clk1 8, clk2 Resource End Radix Group1B=Bin Polarity Group1B=Positive Format Group1B=RZ,70.000ns,10.000ns,Timing,2,Reset Drive Group1B=200mV,3.50V,9 Resource Group1C=Force #TXT 9, SDI0 10, SDI1 Resource End Radix Group1C=Bin Polarity Group1C=Positive Format Group1C=DNRZ,0.000ns,Timing,1,Reset Drive Group1C=200mV,3.50V,9 Resource Group1D=Force #TXT 13, ACK0 Resource End Radix Group1D=Bin Polarity Group1D=Positive Format Group1D=RZ,20.000ns,10.000ns,Timing,2,Reset Drive Group1D=200mV,3.50V,9 Resource Group1E=Force #TXT 14, BCK0 Resource End Radix Group1E=Bin Polarity Group1E=Positive Format Group1E=RZ,60.000ns,10.000ns,Timing,2,Reset Drive Group1E=200mV,3.50V,9 Resource Group1F=Compare #TXT 1, out0 2, out1 3, out2 11, SDO0 12, SDO1 Resource End Radix Group1F=Bin Polarity Group1F=Positive Format Group1F=Edge,10.000ns,Timing,5,Reset Threshold Group1F=1.00V,2.00V Terminate Group1F=Off Active Group1F=Off,0nA,0nA,1.40V Rem Rem TimeSet TS2 ******** Clk Internal,90.000ns Resource Group1A=Force #TXT 4, in0 5, in1 6, in2 Resource End Radix Group1A=Bin Polarity Group1A=Positive Format Group1A=DNRZ,0.000ns,Timing,1,Reset Drive Group1A=200mV,3.50V,9 Resource Group1B=Force #TXT 7, clk1 8, clk2 Resource End Radix Group1B=Bin Polarity Group1B=Positive Format Group1B=RZ,70.000ns,10.000ns,Timing,2,Reset Drive Group1B=200mV,3.50V,9 Resource Group1C=Force #TXT 9, SDI0 10, SDI1 Resource End Radix Group1C=Bin Polarity Group1C=Positive Format Group1C=DNRZ,0.000ns,Timing,1,Reset Drive Group1C=200mV,3.50V,9 Resource Group1D=Force #TXT 13, ACK0 Resource End Radix Group1D=Bin Polarity Group1D=Positive Format Group1D=RZ,20.000ns,10.000ns,Timing,2,Reset Drive Group1D=200mV,3.50V,9 Resource Group1E=Force #TXT 14, BCK0 Resource End Radix Group1E=Bin Polarity Group1E=Positive Format Group1E=RZ,60.000ns,10.000ns,Timing,2,Reset Drive Group1E=200mV,3.50V,9 Resource Group1F=Compare #TXT 1, out0 2, out1 3, out2 11, SDO0 12, SDO1 Resource End Radix Group1F=Bin Polarity Group1F=Positive Format Group1F=Edge,10.000ns,Timing,5,Reset Threshold Group1F=1.00V,2.00V Terminate Group1F=Off Active Group1F=Off,0nA,0nA,1.40V Rem Rem TimeSet TS3 ******** Clk Internal,110.000ns Resource Group1A=Force #TXT 4, in0 5, in1 6, in2 Resource End Radix Group1A=Bin Polarity Group1A=Positive Format Group1A=DNRZ,0.000ns,Timing,1,Reset Drive Group1A=200mV,3.50V,9 Resource Group1B=Force #TXT 7, clk1 8, clk2 Resource End Radix Group1B=Bin Polarity Group1B=Positive Format Group1B=RZ,20.000ns,10.000ns,Timing,2,Reset Drive Group1B=200mV,3.50V,9 Resource Group1C=Force #TXT 9, SDI0 10, SDI1 Resource End Radix Group1C=Bin Polarity Group1C=Positive Format Group1C=DNRZ,0.000ns,Timing,1,Reset Drive Group1C=200mV,3.50V,9 Resource Group1D=Force #TXT 13, ACK0 Resource End Radix Group1D=Bin Polarity Group1D=Positive Format Group1D=RZ,20.000ns,10.000ns,Timing,2,Reset Drive Group1D=200mV,3.50V,9 Resource Group1E=Force #TXT 14, BCK0 Resource End Radix Group1E=Bin Polarity Group1E=Positive Format Group1E=RZ,60.000ns,10.000ns,Timing,2,Reset Drive Group1E=200mV,3.50V,9 Resource Group1F=Compare #TXT 1, out0 2, out1 3, out2 11, SDO0 12, SDO1 Resource End Radix Group1F=Bin Polarity Group1F=Positive Format Group1F=Edge,10.000ns,Timing,5,Reset Threshold Group1F=1.00V,2.00V Terminate Group1F=Off Active Group1F=Off,0nA,0nA,1.40V Rem Rem TimeSet TS4 ******** Clk Internal,100.000ns Resource Group1A=Force #TXT 4, in0 5, in1 6, in2 Resource End Radix Group1A=Bin Polarity Group1A=Positive Format Group1A=DNRZ,0.000ns,Timing,1,Reset Drive Group1A=200mV,3.50V,9 Resource Group1B=Force #TXT 7, clk1 8, clk2 Resource End Radix Group1B=Bin Polarity Group1B=Positive Format Group1B=RZ,50.000ns,30.000ns,Timing,2,Reset Drive Group1B=200mV,3.50V,9 Resource Group1C=Force #TXT 9, SDI0 10, SDI1 Resource End Radix Group1C=Bin Polarity Group1C=Positive Format Group1C=DNRZ,0.000ns,Timing,1,Reset Drive Group1C=200mV,3.50V,9 Resource Group1D=Force #TXT 13, ACK0 Resource End Radix Group1D=Bin Polarity Group1D=Positive Format Group1D=RZ,20.000ns,10.000ns,Timing,2,Reset Drive Group1D=200mV,3.50V,9 Resource Group1E=Force #TXT 14, BCK0 Resource End Radix Group1E=Bin Polarity Group1E=Positive Format Group1E=RZ,60.000ns,10.000ns,Timing,2,Reset Drive Group1E=200mV,3.50V,9 Resource Group1F=Compare #TXT 1, out0 2, out1 3, out2 11, SDO0 12, SDO1 Resource End Radix Group1F=Bin Polarity Group1F=Positive Format Group1F=Edge,10.000ns,Timing,5,Reset Threshold Group1F=1.00V,2.00V Terminate Group1F=Off Active Group1F=Off,0nA,0nA,1.40V INTERFACES/IMS/VCDIMS/000075500001440000012000000000001103104161000147315ustar00jcosleystaff00000400000023INTERFACES/IMS/VCDIMS/exp1.vtran000064400001440000012000000067421103104161000166730ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > IMS # # Original File: "exp1.vcd" # # Target File: "exp1.ims " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into IMS format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN cycle 250; {4 MHz cycle} BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; check_window * @ 195, 200; { strobe all outs at 195 } { #### state character translations for 'VCD'->'IMS'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp1.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "5", TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; end; INTERFACES/IMS/VCDIMS/exp2.vtran000064400001440000012000000065241103104161000166720ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > IMS # # Original File: "exp1.vcd" # # Target File: "exp2.ims " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into IMS format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; Include "../../DATA/exp1.tcyc" { #### state character translations for 'VCD'->'IMS'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp2.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "5", TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; end; INTERFACES/IMS/EVCDIMS/000075500001440000012000000000001103104161000150365ustar00jcosleystaff00000400000023INTERFACES/IMS/EVCDIMS/exp1.vtran000064400001440000012000000102461103104161000167720ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > IMS # # Original File: "exp1.evcd" # # Target File: "exp1.ims " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into IMS format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'EVCD'->'IMS '#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'N', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; { #### ovf timing info #### } cycle 20 align_to_cycle 20 * @ 12, mclk.O @ 18, ma[6] @ 20, ma[7] @ 20; pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; target_file exp1.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "10", TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; pt_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxINTERFACES/IMS/EVCDIMS/exp2.vtran000064400001440000012000000077201103104161000167760ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > IMS # # Original File: "exp1.evcd" # # Target File: "exp2.ims " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into IMS format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'EVCD'->'IMS '#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'N', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; { #### ovf timing info #### } Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; target_file exp2.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "78" , REPEAT_THRESHOLD = "10", TIME_STAMPS = "10" { USE_TIMESET = "TRUE", } TERMINATE = "HALT" ; end; INTERFACES/IMS/README000064400001440000012000000174111103104161000146300ustar00jcosleystaff00000400000023IMS ---- The main directory is "IMS" and the sub-directories are -> WGLIMS -> VCDIMS -> STILIMS -> EVCDIMS The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLIMS" contains the translation of WGL file to IMS output format. Sub-directory -> "EVCDIMS" contains the translation of EVCD file to IMS output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The IMS output format is invoked in the TVF_BLOCK with the following command - optional parameters are shown in []: TESTER_FORMAT IMS [, -USE_TSET_NAMES] { use tset names from input file } [, -AUTO_GROUP] { uses algorithm to group signals } [, SCANIN_DEFAULT = "state"] { any input 'X' is mapped to this } [, USE_TIMESET = "name"] { use tset name "name" } [, SETUP_FILE = "filename"] { Create setup file in "filename" } [, DRIVE = "string"] { text string used with DRIVE in setup } [, THRESHOLD = "string"] { text string used with THRESHOLD in setup } [, ACTIVE = "string"] { text string used with ACTIVE in setup } [, MAX_LINE_LENGTH = "nn"] { defines max length of line in tvf } { defaults to 256 characters } [, REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [, TIME_STAMPS = "ON" | "OFF" | "nn"] { enables/disables timestamps in file } { nn is frequency - default is ON } [, TERMINATE = "command"] { text string used with last vector } ; The quoted parameter value strings may contain spaces. When using the WGL or STIL reader it should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -cycle flag prevents the WGL/STIL reader from flattening-out timing when the file is being read. The -scan flag tells the reader to maintain the scan data separately, i.e. do not flatten it out. Since the IMS format supports a scan data structure, we do not want the WGL/STIL reader to flatten it out. If you do wish to have the reader expand the scan data into sequential normal vectors, then leave out the -scan flag here. Note that for STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is scan data in the file. Two output files are created by vtran. The first is a .mem file which contains the vector and scan data. The second file is a .set (setup) file which contains the signal grouping and timing information. This .set file should be considered more of a boiler-plate, to be edited with further setup information such as calibration, Testconditions, Socket, Config, etc. The output file names are determined primarily from the TARGET_FILE base file name. For example: TARGET_FILE = "exp1.ims"; will result in the two output files: exp1.mem and exp1.set being created. A completely different setup file name can be specified using the SETUP_FILE commadn if so desired. In the setup file, several of the optional parameters above can be used to customize the file. The DRIVE, THRESHOLD, and ACTIVE parameters can be used to specify text strings associated with these statements in the setup file. For example: SIMULATOR IMS, .... DRIVE = "200mV,3.50V,9", THRESHOLD = "1.00V,2.00V", ACTIVE = "Off,0nA,0nA,1.40V", .... The -USE_TSET_NAMES flag will cause the timing set names found in the input vector file (typically a WGL or STIL file) to be used in the .mem vector file. The grouping of signals in the .mem and setup files are usually performed by vtran based upon signal timing, direction and ordering. If you would also like vtran to look for other groupings for similar signal names (as in busses), then the -AUTO_GROUP flag should be used. The USE_TIMESET parameter can be used to set the timeset name to a fixed name for use in the vector (.mem) file. The length of vector lines in the .mem file can be controlled with this parameter - the default is 256. The REPEAT_THRESHOLD parameter activates vtran's repeat processing, whereby it looks for consecutive identical vectors that could be compacted using the repeat facilities in the IMS tester format. The parameter value determines the trigger point for this collapsing. For example: REPEAT_THRESHOLD = "21", Tells vtran that if it sees 21 or more consecutive identical vectors in the input file, it should use the repeat option of IMS to compress these in the output file. Note that this feature should not be used with WGL or STIL files which have a separate repeat structure which is passed to vtran and then replicated in the IMS vectors. REPEAT_THRESHOLD would typically be used with, for example, a translation of VERILOG VCD data into IMS vectors. The TIME_STAMPS parameter will cause time and Sequence tags to be inserted in the IMS vector file as remarks (Rem). If the "ON" value is used, the the tags are inserted once every 40 vectors by default. If, however, a numeric value is specified, then its value dictates how often the tags are included. The TERMINATE parameter provides for a way to specify the IMS opcode following the final vector in the .mem file. This will default to "Halt" if not specified. An example command file for an WGL -> IMS translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > IMS # # Original File: "exp1.wgl" # # Target File: "exp1.ims " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file exp1.wgl; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into IMS format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'IMS'#### } state_trans 'P'->'^', '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file exp1.ims ; {#### OUTPUT VECTOR FILE ####} resolution = 0.001; tester_format IMS , {#### OUTPUT FORMAT ####} -AUTO_GROUP, SCANIN_DEFAULT = "0", MAX_LINE_LENGTH = "300" , TIME_STAMPS = "10" TERMINATE = "HALT" DRIVE = "200mV,3.50V,9", ACTIVE = "Off,0nA,0nA,1.40V", THRESHOLD = "1.00V,2.00V" ; end; end; ################################################################################ INTERFACES/ITS9K/000075500001440000012000000000001103104161000141575ustar00jcosleystaff00000400000023INTERFACES/ITS9K/WGLITS9K/000075500001440000012000000000001103104161000153745ustar00jcosleystaff00000400000023INTERFACES/ITS9K/WGLITS9K/exp2.vtran000064400001440000012000000046501103104161000173330ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > ITS9K # # Original File: "exp1.wgl" # # Target File: "exp2.its " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl, -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'ITS9K'#### } state_trans outputs '0'->'L', '1'->'H', '-'->'X'; state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; ALIAS SHFTDR[2] = SHFTDR, VCCCDCDA[4] = VCCCDCDA; { map some signals } target_file = "exp2.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/WGLITS9K/exp1.vtran000064400001440000012000000050111103104161000173220ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > ITS9K # # Original File: "exp1.wgl" # # Target File: "exp1.its " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl, -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'ITS9K'#### } state_trans outputs '0'->'L', '1'->'H', '-'->'X'; state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; ALIAS SHFTDR[2] = SHFTDR, VCCCDCDA[4] = VCCCDCDA; { map some signals } target_file = "exp1.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/WGLITS9K/exp3.vtran000064400001440000012000000046561103104161000173420ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > ITS9K # # Original File: "exp1.wgl" # # Target File: "exp3.its " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl, -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'ITS9K'#### } state_trans outputs '0'->'L', '1'->'H', '-'->'X'; state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; ALIAS SHFTDR[2] = SHFTDR, VCCCDCDA[4] = VCCCDCDA; { map some signals } target_file = "exp3.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/STILITS9K/000075500001440000012000000000001103104161000155165ustar00jcosleystaff00000400000023INTERFACES/ITS9K/STILITS9K/exp1.vtran000064400001440000012000000050251103104161000174510ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > ITS9K # # Original File: "exp1.stil" # # Target File: "exp1.its " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'ITS9K'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp1.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/STILITS9K/exp2.vtran000064400001440000012000000046761103104161000174650ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > ITS9K # # Original File: "exp1.stil" # # Target File: "exp2.its " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'ITS9K'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp2.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/STILITS9K/exp3.vtran000064400001440000012000000046741103104161000174640ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > ITS9K # # Original File: "exp1.stil" # # Target File: "exp3.its " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'ITS9K'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp3.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/VCDITS9K/000075500001440000012000000000001103104161000153575ustar00jcosleystaff00000400000023INTERFACES/ITS9K/VCDITS9K/exp1.vtran000064400001440000012000000066231103104161000173170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > ITS9K # # Original File: "exp1.vcd" # # Target File: "exp1.its " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into ITS9K format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN DISABLE_VECTOR_FILTER; cycle 250; {4 MHz cycle} ALIGN_TO_STEP 250; BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; check_window * @ 195, 200; { strobe all outs at 195 } { #### state character translations for 'VCD'->'ITS9K'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp1.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/VCDITS9K/exp2.vtran000064400001440000012000000063601103104161000173160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > ITS9K # # Original File: "exp1.vcd" # # Target File: "exp2.its " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into ITS9K format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN DISABLE_VECTOR_FILTER; BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; Include "../../DATA/exp1.tcyc" { #### state character translations for 'VCD'->'ITS9K'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp2.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/ITS9K/EVCDITS9K/000075500001440000012000000000001103104161000154645ustar00jcosleystaff00000400000023INTERFACES/ITS9K/EVCDITS9K/exp1.vtran000064400001440000012000000077231103104161000174260ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > ITS9K # # Original File: "exp1.evcd" # # Target File: "exp1.its " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'ITS9K' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp1.its"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/ITS9K/EVCDITS9K/exp2.vtran000064400001440000012000000073301103104161000174210ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > ITS9K # # Original File: "exp1.evcd" # # Target File: "exp2.its " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'ITS9K' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; target_file = "exp2.its"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/ITS9K/README000064400001440000012000000123041103104161000150370ustar00jcosleystaff00000400000023ITS9000: ---------- The main directory is "ITS9K" and the sub-directories are -> WGLITS9K -> VCDITS9K -> STILITS9K -> EVCDITS9K The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLITS9K" contains the translation of WGL file to ITS9K output format. Sub-directory -> "EVCDITS9K" contains the translation of EVCD file to ITS9K output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... This directory presents several examples of translations to the Schlumberger ITS9000 tester format. The ITS9K output format is invoked in the TVF_BLOCK of the command file with the following command - optional parameters are shown in[]: TESTER_FORMAT ITS9K [ MAX_LINE_LENGTH = "nn"] { defines max length of line (token) } { defaults to 1024 characters } [ REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [ VECTOR_DEF = "name", ] { vector definition name - if none in OVF } [ PACKAGE = "name", ] { name of package } [ PATTERN = "name", ] { name of pattern file } [ TIMING = "name", ] { name of timing def } [ SCANIN_DEFAULT = "0", ] [ TIME_STAMPS = "ON"|"OFF" ] { default is ON } ; The ITS9K writer creates 4 output files. When specifying the TARGET_FILE name, use a base name - the 4 file names will be derived from this by adding suffixes. The four files are: exp1.m9k { the mail vector file } exp1.pdef { the pin definition file } exp1.tdef { the timing definition file } exp1.vdef { the vector definition file } All signals are specified as BIN in the pindef table, except for any scan pins, which are specified as HL10. The ITS9K interface supports scan data when translating from WGL or STIL files (set the -scan flag in the TABULAR_FORMAT statement). When translating from WGL or STIL, vector repeats (and single vector Loops in STIL) are passed to the output file while multi-vector loops are expanded. Bus pins in the input file are automatically grouped together in the output. The ITS9K interface uses the following state characters in the output files: INPUTS: 0, 1 OUTPUTS: H, L, Z, X When translating vectors from another format, use the STATE_TRANS commands to do the mapping to these state characters. For example, when translating from a WGL file, the following STATE_TRANS are suggested: state_trans outputs '0'->'L', '1'->'H', '-'->'X'; state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; Also, if not otherwise specified, the default MERGE_BIDIRECTS precedence is: "HL10XZ". An example command file for an WGL -> ITS9K translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > ITS9K # # Original File: "exp1.wgl" # # Target File: "exp1.its " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl, -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into ITS9K format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'ITS9K'#### } state_trans outputs '0'->'L', '1'->'H', '-'->'X'; state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format ITS9K , {#### OUTPUT FORMAT ####} MAX_LINE_LENGTH = "700", TIME_STAMPS = "ON", SCANIN_DEFAULT = "^", ; ALIAS SHFTDR[2] = SHFTDR, VCCCDCDA[4] = VCCCDCDA; { map some signals } target_file = "exp1.its"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/PCF/000075500001440000012000000000001103104161000137245ustar00jcosleystaff00000400000023INTERFACES/PCF/WGLPCF/000075500001440000012000000000001103104161000147065ustar00jcosleystaff00000400000023INTERFACES/PCF/WGLPCF/exp1.vtran000064400001440000012000000046111103104161000166410ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > PCF # # Original File: "exp1.wgl" # # Target File: "exp1.pcf " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into PCF format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'PCF'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.pcf"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; tester_format pcf; {#### OUTPUT FORMAT ####} end end; INTERFACES/PCF/WGLPCF/exp3.vtran000064400001440000012000000045061103104161000166460ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > PCF # # Original File: "exp1.wgl" # # Target File: "exp3.pcf " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into PCF format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'PCF'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp3.pcf"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; tester_format pcf; {#### OUTPUT FORMAT ####} end end; INTERFACES/PCF/VCDPCF/000075500001440000012000000000001103104161000146715ustar00jcosleystaff00000400000023INTERFACES/PCF/VCDPCF/exp1.vtran000064400001440000012000000134561103104161000166330ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > PCF # # Original File: "exp1A.vcd" # # Target File: "exp1.pcf " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #### Passes event sequencing straight thru to pcf file #### } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into PCF format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'PCF '#### } STATE_TRANS inputs 'x'->'Z', 'z'->'Z', 'X'->'Z' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'X', 'z'->'X', 'Z'->'X' ; { #### Separate bidir in from out data using control pins #### } BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; CYCLE = 50; { #### Needed for PCF cycle #### } END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN merge_bidirects 10HLZX; rename_bus_pins $bus$vec; tester_format pcf; {#### OUTPUT FORMAT ####} TARGET_FILE "exp1.pcf"; {#### OUTPUT VECTOR FILE ####} END; UST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , INTERFACES/PCF/STILPCF/000075500001440000012000000000001103104161000150305ustar00jcosleystaff00000400000023INTERFACES/PCF/STILPCF/exp1.vtran000064400001440000012000000050241103104161000167620ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > PCF # # Original File: "exp1.stil" # # Target File: "exp1.pcf " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} { #### loops/repeats always flattened; expand flags not required #### } end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into PCF format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'PCF'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block simulator pcf SIGNAL_FILE = "exp1.sigs"; {#### timing info ####} merge_bidirects 10HLZX; target_file = "exp1.pcf"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/PCF/STILPCF/exp1.sigs000064400001440000012000000044751103104161000166060ustar00jcosleystaff00000400000023assign P_P302_IRQ_1 to pins "1" assign P_ATE_N to pins "2" assign P_DMA_IRQ to pins "3" assign P_DSP_IRQ_1 to pins "4" assign P_DSP_IRQ_2 to pins "5" assign P_CLK to pins "6" assign P_IRQ6 to pins "7" assign P_IRQ7 to pins "8" assign P_S302_IRQ to pins "9" assign P_IRQ4 to pins "10" assign P_IRQ5 to pins "11" assign P_IRQ1 to pins "12" assign P_IRQ2 to pins "13" assign P_IRQ3 to pins "14" assign P_RESET_N to pins "15" assign P_IRQ0 to pins "16" assign P_CS2_N to pins "17" assign P_BMG2 to pins "18" assign P_TIRQ1_2_N to pins "19" assign P_AT_IRQ_2 to pins "20" assign P_NMI_2_N to pins "21" assign P_RW2 to pins "22" assign P_MUSTANG_SE_N to pins "23" assign P_IACK2_N to pins "24" assign P_ADDR2_2 to pins "25" assign P_ADDR2_1 to pins "26" assign P_ADDR2_3 to pins "27" assign P_MUSTANG_TDI to pins "28" assign P_NMI_1_N to pins "29" assign P_TIRQ2_1_N to pins "30" assign P_TIRQ1_1_N to pins "31" assign P_DIRQ_1_N to pins "32" assign P_RW1 to pins "33" assign P_BMG1 to pins "34" assign P_ADDR1_1 to pins "35" assign P_IACK1_N to pins "36" assign P_CS1_N to pins "37" assign P_ADDR1_3 to pins "38" assign P_ADDR1_2 to pins "39" assign P_DATA2_2 to pins "40" assign P_DATA2_0 to pins "41" assign P_DATA2_1 to pins "42" assign P_DATA1_3 to pins "43" assign P_DATA2_4 to pins "44" assign P_DATA2_3 to pins "45" assign P_DATA2_6 to pins "46" assign P_DATA2_5 to pins "47" assign P_DATA2_7 to pins "48" assign P_DATA1_6 to pins "49" assign P_DATA1_7 to pins "50" assign P_DATA1_4 to pins "51" assign P_DATA1_5 to pins "52" assign P_DATA1_0 to pins "53" assign P_DATA1_2 to pins "54" assign P_DATA1_1 to pins "55" assign P_ATSEL_1_N to pins "56" assign P_MUSTANG_TDO to pins "57" assign P_ATSEL_2_N to pins "58" assign P_IPL2_0 to pins "59" assign P_IPL1_1 to pins "60" assign P_IPL1_0 to pins "61" assign P_IPL1_2 to pins "62" assign P_IPL2_1 to pins "63" assign P_IPL2_2 to pins "64" assign P_IACK_7_N to pins "65" assign P_IACK_3_N to pins "66" assign P_IACK_1_N to pins "67" assign P_IACK_0_N to pins "68" assign P_IACK_2_N to pins "69" assign P_IACK_5_N to pins "70" assign P_IACK_4_N to pins "71" assign P_IACK_6_N to pins "72" assign P_IACK_P302_N to pins "73" assign P_IACK_S302_N to pins "74" assign P_DTACK_2_N to pins "75" assign P_DTACK_1_N to pins "76" assign GND to pins "77", "122", "144" assign VDD to pins "78", "99", "143" power GND, VDD INTERFACES/PCF/STILPCF/exp3.vtran000064400001440000012000000046131103104161000167670ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > PCF # # Original File: "exp1.stil" # # Target File: "exp3.pcf " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into PCF format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'PCF'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block simulator pcf SIGNAL_FILE = "exp1.sigs"; {#### timing info ####} merge_bidirects 10HLZX; target_file = "exp3.pcf"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/PCF/README000064400001440000012000000173451103104161000146160ustar00jcosleystaff00000400000023PCF ---- The main directory is "PCF" and the sub-directories are -> WGLPCF -> VCDPCF -> STILPCF -> EVCDPCF ->PCFSTIL ->PCFVERILOG The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLPCF" contains the translation of WGL file to PCF output format. Sub-directory -> "EVCDPCF" contains the translation of EVCD file to PCF output format. Sub-directory -> "PCFSTIL" contains the translation of PCF file to STIL output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The PCF output format is invokde in the TVF_BLOCK with the following command - optional parameters are shown in []: TESTER_FORMAT PCF [, FAMILY = "string"] { specify logic family } [, UNIT = "string"] { specify unit } [, DATE = "string"] { specify date - overrides current date } [, TIMESET = "string"] { specify timeset to be used } [, TIMESET_FILE = "filename"] { specify creation of timing file } [, RECEIVE_DELAY = "nnn"] { specify receive delay in NS } [, SIGNAL_FILE = "filename"] { specify siganl file for assigns } [, SCANIN_DEFAULT="X"] { sets scan-in padding state } ; When using the STIL or WGL reader it should be invoked in the OVF_BLOCK with: tabular_format STIL -cycle, -scan; or tabular_format WGL -cycle, -scan; The -cycle flag prevents the readers from flattening-out timing when the file is being read. In order to maintain the event sequencing from the input file, vtran will generate separate vectors at each unique signal transition time. The types of signal behaviors supported by this interface are NRZ (with ot without delay), RO and RZ for clocks. The -scan flag tells the readers to maintain the scan data separately, i.e. do not flatten it out. Since the PCF format supports a scan data structure, we do not want the readers to flatten it out. When dealing with scan data, however, since PCF does not provide for a setup vector prior to scan in which to set the states of non-scan pins, the interface peels-off the first scan vector as a normal vector in order to set the appropriate constant pin states. After each parallel vector, the time stamp from the STIL/WGL-equivalent file is added as a comment. If the STIL/WGL data contains more than one Timing set, and the TIMESET_FILE parameter is specified, multiple "use timing set .." statements will appear in the PCF file when the timing changes. The SIGNAL_FILE parameter allows the user to specify the signal "assign"'s for the PCF file which define which physical pin numbers are connected to which signals and the power pins. This file should also contain the "power" statement for the power pins. An example file might look like: assign P_IACK_P302_N to pins "73" assign P_IACK_S302_N to pins "74" assign P_DTACK_2_N to pins "75" assign P_DTACK_1_N to pins "76" assign GND to pins "77", "122", "144" assign VDD to pins "78", "99", "143" power GND, VDD The contents of this file are inserted into the PCF file in the "assign" section of the file. If no SIGNAL_FILE parameter is specified, then vtran will make pin assignments as consecutive pin numbers, and will insert a dummy GND and PWR signal. A good way to create this SIGNAL_FILE would be to run the translation with no SIGNAL_FILE specified at first. Then, cut and paste the assign and power statements from this file to another (.sigs) file. Next edit this (.sigs) file to specify the actual signal-to-pin assingmants you need and the power assignments. Finally, in the vtran command file, add the SIGNAL_FILE parameter pointing to this new edited file. From this point on these pin assignments will be used in the PCF file. An example command file for an WGL -> PCF translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > PCF # # Original File: "exp1.wgl" # # Target File: "exp1.pcf " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into PCF format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'PCF'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.pcf"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; tester_format pcf; {#### OUTPUT FORMAT ####} end end; ################################################################################ Beginning with vtran release 7.0, a number of the tester output interface options include a canned reader which is specifically designed to read the vtran-generated tester files and translate these directly to a Verilog or VHDL testbench (or actually any flat format). These canned readers are "Read-Back" modules which provide a direct way to verify the tester files, thru testbench re-simulation, prior to trying them on the tester. Note that these Read-Back modules support only the subset of the tester syntax used by vtran when generating the test programs and only support a flat translation, thus they are not intended for use as a general-purpose translation tool for the tester languages. Both timing and Scan data from the PCF file is flattened out. This supports translation from PCF format to event-based vector formats, such as Verilog and VHDL testbenches. To generate cycle-based output, the timing must be defined in the PROC_BLOCK of the Vtran command file. An example command file for a PCF->Verilog testbench translation might look like: ovf_block begin orig_file "scan1.pcf"; {#### INPUT VECTOR FILE ####} tabular_format PCF ; {#### INPUT FORMAT ####} end proc_block begin disable_vector_filter; { #### state character translations for 'PCF' -> 'Verilog' #### } state_trans outputs 'L'->'0', 'H'->'1'; end tvf_block begin target_file "exp1.vtb"; {#### OUTPUT VECTOR FILE ####} tester_format Verilog_tb; {#### OUTPUT FORMAT ####} end end; The timing, vectors, and Scan data are in the "scan1.pcf" file, a vtran-generated file required by the reader. or WGL reader it should be invoked in the OVF_BLOCK with: tabular_format STIL -cycle, -scan; or tabular_format WGL -cycle, -scan; The -cycle flag prevents the readers from flattening-out timing when the file is being read. In order to maintain the event sequencing from the inINTERFACES/PCF/EVCDPCF/000075500001440000012000000000001103104161000147765ustar00jcosleystaff00000400000023INTERFACES/PCF/EVCDPCF/exp1.vtran000064400001440000012000000077061103104161000167410ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > PCF # # Original File: "exp1.evcd" # # Target File: "exp1.pcf " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into PCF format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'PCF' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; merge_bidirects 10HLZX; rename_bus_pins $bus$vec; tester_format pcf; {#### OUTPUT FORMAT ####} TARGET_FILE "exp1.pcf"; {#### OUTPUT VECTOR FILE ####} END; end INTERFACES/PCF/PCFSTIL/000075500001440000012000000000001103104161000150305ustar00jcosleystaff00000400000023INTERFACES/PCF/PCFSTIL/cyc1.vtran000064400001440000012000000051721103104161000167500ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: PCF < to > STIL # # Original File: "scan1.pcf" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.7 (C) 2007 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/scan1.pcf"; {#### INPUT VECTOR FILE ####} tabular_format PCF ; {#### INPUT FORMAT ####} { #### PCR Reader always flattens vectors #### } { #### no cycle, loops, repeats, or scan flags #### } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the PCF # # vector data to translate into STIL format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'PCF'->'STIL'#### } state_trans inputs '0'->'D', '1'->'U', 'X'->'Z'; { #### need to cyclize data since PCF reader flattens events #### } cycle 500; align_to_cycle 500, all_inputs @ 0, all_outputs @ 490; { #### timing for STIL file #### } PINTYPE NRZ all_inputs @ 0; PINTYPE STB all_outputs @ 400; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} tester_format stil; {#### OUTPUT FORMAT ####} end end; # # Translation: PCF < to > STIL # # Original File: "scan1.pcf" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" #INTERFACES/PCF/PCFVERILOG/000075500001440000012000000000001103104161000153645ustar00jcosleystaff00000400000023INTERFACES/PCF/PCFVERILOG/exp1.vtran000064400001440000012000000044161103104161000173220ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: PCF < to > Verilog_tb # # Original File: "scan1.pcf" # # Target File: "exp1.vtb " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.7 (C) 2007 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/scan1.pcf"; {#### INPUT VECTOR FILE ####} tabular_format PCF ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into PCF format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'PCF' -> 'Verilog' #### } state_trans outputs 'L'->'0', 'H'->'1'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.vtb"; {#### OUTPUT VECTOR FILE ####} tester_format Verilog_tb; {#### OUTPUT FORMAT ####} end end; INTERFACES/STIL/000075500001440000012000000000001103104161000140675ustar00jcosleystaff00000400000023INTERFACES/STIL/WGLSTIL/000075500001440000012000000000001103104161000152145ustar00jcosleystaff00000400000023INTERFACES/STIL/WGLSTIL/exp2.vtran000064400001440000012000000046761103104161000171630ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > STIL # # Original File: "exp1.wgl" # # Target File: "exp2.stil " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl -cycle ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'STIL'#### } state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin resolution = 0.1; { #### .1ns resolution for times #### } tester_format STIL {#### OUTPUT VECTOR FILE ####} -quote_names, { #### quote all signal/cell/chain names #### } scanin_default = "^"; { #### pad short scan chains with first non-X char #### } target_file "exp2.stil"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/STIL/WGLSTIL/exp1.vtran000064400001440000012000000050361103104161000171510ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > STIL # # Original File: "exp1.wgl" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'STIL'#### } state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin resolution = 0.1; { #### .1ns resolution for times #### } tester_format STIL {#### OUTPUT VECTOR FILE ####} -quote_names, { #### quote all signal/cell/chain names #### } scanin_default = "^"; { #### pad short scan chains with first non-X char #### } target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} end; end; ==========================================# } ovf_block begin tabular_format wgl -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into SINTERFACES/STIL/WGLSTIL/exp3.vtran000064400001440000012000000047041103104161000171540ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > STIL # # Original File: "exp1.wgl" # # Target File: "exp3.stil " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'STIL'#### } state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin resolution = 0.1; { #### .1ns resolution for times #### } tester_format STIL {#### OUTPUT VECTOR FILE ####} -quote_names, { #### quote all signal/cell/chain names #### } scanin_default = "^"; { #### pad short scan chains with first non-X char #### } target_file "exp3.stil"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/STIL/WGLSTIL/insertstmt.vtran000064400001440000012000000055571103104161000205200ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > STIL # # Original File: "exp4.wgl" # # Target File: "exp4.stil " # # Command File: "insertstmt.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 8.1.1 (C) 2008 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp4.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'STIL'#### } state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; INSERT_STATEMENT "// This is first addition" @ CONDITION in0 = 0; INSERT_STATEMENT "// This is second addition" @ TRANSITION in1 0N ; INSERT_STATEMENT "// This is third addition" @ TRANSITION ACK0 0-1 ; INSERT_STATEMENT "// This is fourth addition" @ TRANSITION -count 3 BCK0 1->0 ; INSERT_STATEMENT "// This is fifth addition" @ TIME -after 1080; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format STIL ; {#### OUTPUT VECTOR FILE ####} { scanin_default = "^"; } { #### pad short scan chains with first non-X char #### } target_file "exp4.stil"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/STIL/VCDSTIL/000075500001440000012000000000001103104161000151775ustar00jcosleystaff00000400000023INTERFACES/STIL/VCDSTIL/exp1.vtran000064400001440000012000000332021103104161000171300ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > STIL # # Original File: "exp1.vcd" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.vcd"; {#### INPUT VECTOR FILE ####} tabular_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} inputs BPCCE, CFG66, S_CFN_L, MSK_IN, P_GNT_L, P_IDSEL, P_LOCK_L, P_M66EN, S_SERR_L, P_CLK, P_RESET_L, S_CLKIN, TDI, TMS, TCK, TRST_L, P_VIO, S_VIO, MS0, MS1; inputs S_REQ_L[8:0]; outputs P_SERR_L, P_REQ_L, S_RESET_L, TDO, ENUM_L, LOO; outputs S_GNT_L[8:0]; outputs S_CLKOUT[9:0]; bidirects S_M66EN, P_DEVSEL_L, P_FRAME_L, P_IRDY_L, P_PAR, P_PERR_L, P_STOP_L, P_TRDY_L, S_DEVSEL_L, S_FRAME_L, S_IRDY_L, S_LOCK_L, S_PAR, S_PERR_L, S_STOP_L, S_TRDY_L; bidirects GPIO[3:0]; bidirects P_AD[31:0]; bidirects P_CBE[3:0]; bidirects S_AD[31:0]; bidirects S_CBE[3:0]; outputs { #### These are actually bidirect control signals #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'VCD'->'STIL'#### } STATE_TRANS 'x'->'N', 'X'->'N', 'z'->'Z' ; STATE_TRANS outputs '0'->'L', '1'->'H', 'Z'->'T', 'z'->'T'; { #### tell vtran how to determine bidirect signal direction #### } bidirect_control S_M66EN = output when xs_m66en_gmux_out = 0; bidirect_control P_DEVSEL_L = output when xp_devsel_gmux_out = 0; bidirect_control P_FRAME_L = output when xp_frame_gmux_out = 0; bidirect_control P_IRDY_L = output when xp_irdy_gmux_out = 0; bidirect_control P_PAR = output when xp_par_gmux_out = 0; bidirect_control P_PERR_L = output when xp_perr_gmux_out = 0; bidirect_control P_STOP_L = output when xp_stop_gmux_out = 0; bidirect_control P_TRDY_L = output when xp_trdy_gmux_out = 0; bidirect_control S_DEVSEL_L = output when xs_devsel_gmux_out = 0; bidirect_control S_FRAME_L = output when xs_frame_gmux_out = 0; bidirect_control S_IRDY_L = output when xs_irdy_gmux_out = 0; bidirect_control S_LOCK_L = output when xs_lock_gmux_out = 0; bidirect_control S_PAR = output when xs_par_gmux_out = 0; bidirect_control S_PERR_L = output when xs_perr_gmux_out = 0; bidirect_control S_STOP_L = output when xs_stop_gmux_out = 0; bidirect_control S_TRDY_L = output when xs_trdy_gmux_out = 0; bidirect_control GPIO[3] = output when x_gpio_3_gmux_out = 0; bidirect_control GPIO[2] = output when x_gpio_2_gmux_out = 0; bidirect_control GPIO[1] = output when x_gpio_1_gmux_out = 0; bidirect_control GPIO[0] = output when x_gpio_0_gmux_out = 0; bidirect_control P_AD[31] = output when xp_ad31_gmux_out = 0; bidirect_control P_AD[30] = output when xp_ad30_gmux_out = 0; bidirect_control P_AD[29] = output when xp_ad29_gmux_out = 0; bidirect_control P_AD[28] = output when xp_ad28_gmux_out = 0; bidirect_control P_AD[27] = output when xp_ad27_gmux_out = 0; bidirect_control P_AD[26] = output when xp_ad26_gmux_out = 0; bidirect_control P_AD[25] = output when xp_ad25_gmux_out = 0; bidirect_control P_AD[24] = output when xp_ad24_gmux_out = 0; bidirect_control P_AD[23] = output when xp_ad23_gmux_out = 0; bidirect_control P_AD[22] = output when xp_ad22_gmux_out = 0; bidirect_control P_AD[21] = output when xp_ad21_gmux_out = 0; bidirect_control P_AD[20] = output when xp_ad20_gmux_out = 0; bidirect_control P_AD[19] = output when xp_ad19_gmux_out = 0; bidirect_control P_AD[18] = output when xp_ad18_gmux_out = 0; bidirect_control P_AD[17] = output when xp_ad17_gmux_out = 0; bidirect_control P_AD[16] = output when xp_ad16_gmux_out = 0; bidirect_control P_AD[15] = output when xp_ad15_gmux_out = 0; bidirect_control P_AD[14] = output when xp_ad14_gmux_out = 0; bidirect_control P_AD[13] = output when xp_ad13_gmux_out = 0; bidirect_control P_AD[12] = output when xp_ad12_gmux_out = 0; bidirect_control P_AD[11] = output when xp_ad11_gmux_out = 0; bidirect_control P_AD[10] = output when xp_ad10_gmux_out = 0; bidirect_control P_AD[9] = output when xp_ad9_gmux_out = 0; bidirect_control P_AD[8] = output when xp_ad8_gmux_out = 0; bidirect_control P_AD[7] = output when xp_ad7_gmux_out = 0; bidirect_control P_AD[6] = output when xp_ad6_gmux_out = 0; bidirect_control P_AD[5] = output when xp_ad5_gmux_out = 0; bidirect_control P_AD[4] = output when xp_ad4_gmux_out = 0; bidirect_control P_AD[3] = output when xp_ad3_gmux_out = 0; bidirect_control P_AD[2] = output when xp_ad2_gmux_out = 0; bidirect_control P_AD[1] = output when xp_ad1_gmux_out = 0; bidirect_control P_AD[0] = output when xp_ad0_gmux_out = 0; bidirect_control P_CBE[3] = output when xp_cbe3_gmux_out = 0; bidirect_control P_CBE[2] = output when xp_cbe2_gmux_out = 0; bidirect_control P_CBE[1] = output when xp_cbe1_gmux_out = 0; bidirect_control P_CBE[0] = output when xp_cbe0_gmux_out = 0; bidirect_control S_AD[31] = output when xs_ad31_gmux_out = 0; bidirect_control S_AD[30] = output when xs_ad30_gmux_out = 0; bidirect_control S_AD[29] = output when xs_ad29_gmux_out = 0; bidirect_control S_AD[28] = output when xs_ad28_gmux_out = 0; bidirect_control S_AD[27] = output when xs_ad27_gmux_out = 0; bidirect_control S_AD[26] = output when xs_ad26_gmux_out = 0; bidirect_control S_AD[25] = output when xs_ad25_gmux_out = 0; bidirect_control S_AD[24] = output when xs_ad24_gmux_out = 0; bidirect_control S_AD[23] = output when xs_ad23_gmux_out = 0; bidirect_control S_AD[22] = output when xs_ad22_gmux_out = 0; bidirect_control S_AD[21] = output when xs_ad21_gmux_out = 0; bidirect_control S_AD[20] = output when xs_ad20_gmux_out = 0; bidirect_control S_AD[19] = output when xs_ad19_gmux_out = 0; bidirect_control S_AD[18] = output when xs_ad18_gmux_out = 0; bidirect_control S_AD[17] = output when xs_ad17_gmux_out = 0; bidirect_control S_AD[16] = output when xs_ad16_gmux_out = 0; bidirect_control S_AD[15] = output when xs_ad15_gmux_out = 0; bidirect_control S_AD[14] = output when xs_ad14_gmux_out = 0; bidirect_control S_AD[13] = output when xs_ad13_gmux_out = 0; bidirect_control S_AD[12] = output when xs_ad12_gmux_out = 0; bidirect_control S_AD[11] = output when xs_ad11_gmux_out = 0; bidirect_control S_AD[10] = output when xs_ad10_gmux_out = 0; bidirect_control S_AD[9] = output when xs_ad9_gmux_out = 0; bidirect_control S_AD[8] = output when xs_ad8_gmux_out = 0; bidirect_control S_AD[7] = output when xs_ad7_gmux_out = 0; bidirect_control S_AD[6] = output when xs_ad6_gmux_out = 0; bidirect_control S_AD[5] = output when xs_ad5_gmux_out = 0; bidirect_control S_AD[4] = output when xs_ad4_gmux_out = 0; bidirect_control S_AD[3] = output when xs_ad3_gmux_out = 0; bidirect_control S_AD[2] = output when xs_ad2_gmux_out = 0; bidirect_control S_AD[1] = output when xs_ad1_gmux_out = 0; bidirect_control S_AD[0] = output when xs_ad0_gmux_out = 0; bidirect_control S_CBE[3] = output when xs_cbe3_gmux_out = 0; bidirect_control S_CBE[2] = output when xs_cbe2_gmux_out = 0; bidirect_control S_CBE[1] = output when xs_cbe1_gmux_out = 0; bidirect_control S_CBE[0] = output when xs_cbe0_gmux_out = 0; bidirect_control S_CLKOUT[9] = output when 0; { #### collapse to cycle-based data, strobe all pins at 49 in cycle #### } {################################################################## The vector data in the VCD file is in a print-on-change format. The vector data for the STIL file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, sampling all input signals at 5 and all output signals at 98 nS into the 100 nS cycle, but sampling the two clock signals at 40 nS into the cycle ######################################################################} CYCLE = 100; ALIGN_TO_CYCLE 100 ALL_INPUTS @ 5, ALL_OUTPUTS @ 98, P_CLK @ 40 S_CLKIN @ 40; { ####now define some timing for the STIL file ####} { #### since VCD file does not contain this info separately ####} PINTYPE NRZ * @ 0, 0; { #### drive all inputs at 0 #### } PINTYPE STB * @ 98; { #### strobe all outputs at 15 #### } PINTYPE RZ P_CLK @ 0, 50; { #### clock waveform #### } PINTYPE RZ S_CLKIN @ 10, 60; { #### clock waveform #### } end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin TESTER_FORMAT STIL {#### OUTPUT FORMAT ####} -quote_names, INPUT_GROUP = "S_AD", { #### make separate group to reduce file size #### } INPUT_GROUP = "P_AD", { #### make separate group to reduce file size #### } ; DELETE_PINS { #### don't want these controls in STIL file #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into STIL format # #======================================================================# } proc_block INTERFACES/STIL/VCDSTIL/exp1.vcd000064400001440000012000004261431103104161000165640ustar00jcosleystaff00000400000023$date Dec 3, 2001 16:19:45 $end $version VERILOG-XL 2.7.s032 $end $timescale 10ps $end $scope module pcibridge_tb $end $var wire 1 ! TCK $end $var wire 1 " TMS $end $var wire 1 # TDI $end $var wire 1 $ TDO $end $var wire 1 % TRST_L $end $var wire 1 & BPCCE $end $var wire 1 ' CFG66 $end $var wire 1 ( S_CFN_L $end $var wire 1 ) P_SERR_L $end $var wire 1 * S_M66EN $end $var wire 1 + GPIO [3] $end $var wire 1 , GPIO [2] $end $var wire 1 - GPIO [1] $end $var wire 1 . GPIO [0] $end $var wire 1 / MSK_IN $end $var wire 1 0 P_AD [31] $end $var wire 1 1 P_AD [30] $end $var wire 1 2 P_AD [29] $end $var wire 1 3 P_AD [28] $end $var wire 1 4 P_AD [27] $end $var wire 1 5 P_AD [26] $end $var wire 1 6 P_AD [25] $end $var wire 1 7 P_AD [24] $end $var wire 1 8 P_AD [23] $end $var wire 1 9 P_AD [22] $end $var wire 1 : P_AD [21] $end $var wire 1 ; P_AD [20] $end $var wire 1 < P_AD [19] $end $var wire 1 = P_AD [18] $end $var wire 1 > P_AD [17] $end $var wire 1 ? P_AD [16] $end $var wire 1 @ P_AD [15] $end $var wire 1 A P_AD [14] $end $var wire 1 B P_AD [13] $end $var wire 1 C P_AD [12] $end $var wire 1 D P_AD [11] $end $var wire 1 E P_AD [10] $end $var wire 1 F P_AD [9] $end $var wire 1 G P_AD [8] $end $var wire 1 H P_AD [7] $end $var wire 1 I P_AD [6] $end $var wire 1 J P_AD [5] $end $var wire 1 K P_AD [4] $end $var wire 1 L P_AD [3] $end $var wire 1 M P_AD [2] $end $var wire 1 N P_AD [1] $end $var wire 1 O P_AD [0] $end $var wire 1 P P_CBE [3] $end $var wire 1 Q P_CBE [2] $end $var wire 1 R P_CBE [1] $end $var wire 1 S P_CBE [0] $end $var wire 1 T P_DEVSEL_L $end $var wire 1 U P_FRAME_L $end $var wire 1 V P_GNT_L $end $var wire 1 W P_IDSEL $end $var wire 1 X P_IRDY_L $end $var wire 1 Y P_LOCK_L $end $var wire 1 Z P_M66EN $end $var wire 1 [ P_PAR $end $var wire 1 \ P_PERR_L $end $var wire 1 ] P_REQ_L $end $var wire 1 ^ P_STOP_L $end $var wire 1 _ P_TRDY_L $end $var wire 1 ` S_AD [31] $end $var wire 1 a S_AD [30] $end $var wire 1 b S_AD [29] $end $var wire 1 c S_AD [28] $end $var wire 1 d S_AD [27] $end $var wire 1 e S_AD [26] $end $var wire 1 f S_AD [25] $end $var wire 1 g S_AD [24] $end $var wire 1 h S_AD [23] $end $var wire 1 i S_AD [22] $end $var wire 1 j S_AD [21] $end $var wire 1 k S_AD [20] $end $var wire 1 l S_AD [19] $end $var wire 1 m S_AD [18] $end $var wire 1 n S_AD [17] $end $var wire 1 o S_AD [16] $end $var wire 1 p S_AD [15] $end $var wire 1 q S_AD [14] $end $var wire 1 r S_AD [13] $end $var wire 1 s S_AD [12] $end $var wire 1 t S_AD [11] $end $var wire 1 u S_AD [10] $end $var wire 1 v S_AD [9] $end $var wire 1 w S_AD [8] $end $var wire 1 x S_AD [7] $end $var wire 1 y S_AD [6] $end $var wire 1 z S_AD [5] $end $var wire 1 { S_AD [4] $end $var wire 1 | S_AD [3] $end $var wire 1 } S_AD [2] $end $var wire 1 ~ S_AD [1] $end $var wire 1 !! S_AD [0] $end $var wire 1 "! S_CLKOUT [9] $end $var wire 1 #! S_CLKOUT [8] $end $var wire 1 $! S_CLKOUT [7] $end $var wire 1 %! S_CLKOUT [6] $end $var wire 1 &! S_CLKOUT [5] $end $var wire 1 '! S_CLKOUT [4] $end $var wire 1 (! S_CLKOUT [3] $end $var wire 1 )! S_CLKOUT [2] $end $var wire 1 *! S_CLKOUT [1] $end $var wire 1 +! S_CLKOUT [0] $end $var wire 1 ,! S_CBE [3] $end $var wire 1 -! S_CBE [2] $end $var wire 1 .! S_CBE [1] $end $var wire 1 /! S_CBE [0] $end $var wire 1 0! S_DEVSEL_L $end $var wire 1 1! S_FRAME_L $end $var wire 1 2! S_GNT_L [8] $end $var wire 1 3! S_GNT_L [7] $end $var wire 1 4! S_GNT_L [6] $end $var wire 1 5! S_GNT_L [5] $end $var wire 1 6! S_GNT_L [4] $end $var wire 1 7! S_GNT_L [3] $end $var wire 1 8! S_GNT_L [2] $end $var wire 1 9! S_GNT_L [1] $end $var wire 1 :! S_GNT_L [0] $end $var wire 1 ;! S_IRDY_L $end $var wire 1 ! S_RESET_L $end $var wire 1 ?! S_PERR_L $end $var wire 1 @! S_REQ_L [8] $end $var wire 1 A! S_REQ_L [7] $end $var wire 1 B! S_REQ_L [6] $end $var wire 1 C! S_REQ_L [5] $end $var wire 1 D! S_REQ_L [4] $end $var wire 1 E! S_REQ_L [3] $end $var wire 1 F! S_REQ_L [2] $end $var wire 1 G! S_REQ_L [1] $end $var wire 1 H! S_REQ_L [0] $end $var wire 1 I! S_SERR_L $end $var wire 1 J! S_STOP_L $end $var wire 1 K! S_TRDY_L $end $var wire 1 L! P_CLK $end $var wire 1 M! P_RESET_L $end $var wire 1 N! S_CLKIN $end $var wire 1 O! LOO $end $var wire 1 P! P_VIO $end $var wire 1 Q! S_VIO $end $var wire 1 R! ENUM_L $end $var wire 1 S! MS0 $end $var wire 1 T! MS1 $end $scope task print_bit_string $end $upscope $end $scope task async_tap_reset $end $upscope $end $scope task sync_tap_reset $end $upscope $end $scope task shift_instr_register_with_pause $end $scope begin insert_overshifted_pattern $end $upscope $end $scope begin check_TDO_for_shifted_pattern $end $upscope $end $upscope $end $scope task shift_boundary_register_with_pause $end $scope begin insert_overshifted_pattern $end $upscope $end $scope begin check_TDO_for_shifted_pattern $end $upscope $end $upscope $end $scope task run_all_tap_states $end $upscope $end $scope task set_instruction $end $upscope $end $scope task insert_serial_data_TDI $end $upscope $end $scope task create_out_bscells_pattern_1 $end $upscope $end $scope task create_out_bscells_pattern_0 $end $upscope $end $scope task create_out_bscells_pattern_01 $end $upscope $end $scope task create_out_bscells_pattern_10 $end $upscope $end $scope task create_out_bscells_pattern_z $end $upscope $end $scope task create_out_bscells_pattern_inverted $end $upscope $end $scope task initialize_input_bscells $end $upscope $end $scope task set_input_bscells_0 $end $upscope $end $scope task set_input_bscells_1 $end $upscope $end $scope task set_input_bscells_01 $end $upscope $end $scope task set_input_bscells_10 $end $upscope $end $scope task set_input_bscells_01_sample $end $upscope $end $scope task set_input_bscells_10_sample $end $upscope $end $scope task set_bidi_pads_Z $end $upscope $end $scope task check_output_bscells_0 $end $upscope $end $scope task check_output_bscells_1 $end $upscope $end $scope task check_output_bscells_01 $end $upscope $end $scope task check_output_bscells_10 $end $upscope $end $scope task check_output_bscells_Z $end $upscope $end $scope task check_output_bscells_highz_Z $end $upscope $end $scope task check_output_bscells_extest $end $upscope $end $scope task check_output_bscells_sample $end $upscope $end $scope task check_default_instruction $end $upscope $end $scope task check_TDO_for_capture_pattern $end $upscope $end $scope task check_bypass_reg $end $upscope $end $scope task check_boundary_reg_with_patterns_01 $end $upscope $end $scope task check_boundary_reg_with_patterns_10 $end $upscope $end $scope task check_boundary_reg_with_patterns_01_sample $end $upscope $end $scope task check_boundary_reg_with_patterns_10_sample $end $upscope $end $scope task check_boundary_reg_with_patterns_0 $end $upscope $end $scope task check_boundary_reg_with_patterns_1 $end $upscope $end $scope task check_TDO_Z $end $upscope $end $scope task sample_TDO $end $upscope $end $scope module chip $end $scope module pad_i1 $end $scope module xp_serr $end $var wire 1 U! gmux_out $end $upscope $end $scope module xs_m66en $end $var wire 1 V! xs_m66en_gmux_out $end $upscope $end $scope module x_gpio_0 $end $var wire 1 W! x_gpio_0_gmux_out $end $upscope $end $scope module x_gpio_1 $end $var wire 1 X! x_gpio_1_gmux_out $end $upscope $end $scope module x_gpio_2 $end $var wire 1 Y! x_gpio_2_gmux_out $end $upscope $end $scope module x_gpio_3 $end $var wire 1 Z! x_gpio_3_gmux_out $end $upscope $end $scope module xp_ad0 $end $var wire 1 [! xp_ad0_gmux_out $end $upscope $end $scope module xp_ad1 $end $var wire 1 \! xp_ad1_gmux_out $end $upscope $end $scope module xp_ad2 $end $var wire 1 ]! xp_ad2_gmux_out $end $upscope $end $scope module xp_ad3 $end $var wire 1 ^! xp_ad3_gmux_out $end $upscope $end $scope module xp_ad4 $end $var wire 1 _! xp_ad4_gmux_out $end $upscope $end $scope module xp_ad5 $end $var wire 1 `! xp_ad5_gmux_out $end $upscope $end $scope module xp_ad6 $end $var wire 1 a! xp_ad6_gmux_out $end $upscope $end $scope module xp_ad7 $end $var wire 1 b! xp_ad7_gmux_out $end $upscope $end $scope module xp_ad8 $end $var wire 1 c! xp_ad8_gmux_out $end $upscope $end $scope module xp_ad9 $end $var wire 1 d! xp_ad9_gmux_out $end $upscope $end $scope module xp_ad10 $end $var wire 1 e! xp_ad10_gmux_out $end $upscope $end $scope module xp_ad11 $end $var wire 1 f! xp_ad11_gmux_out $end $upscope $end $scope module xp_ad12 $end $var wire 1 g! xp_ad12_gmux_out $end $upscope $end $scope module xp_ad13 $end $var wire 1 h! xp_ad13_gmux_out $end $upscope $end $scope module xp_ad14 $end $var wire 1 i! xp_ad14_gmux_out $end $upscope $end $scope module xp_ad15 $end $var wire 1 j! xp_ad15_gmux_out $end $upscope $end $scope module xp_ad16 $end $var wire 1 k! xp_ad16_gmux_out $end $upscope $end $scope module xp_ad17 $end $var wire 1 l! xp_ad17_gmux_out $end $upscope $end $scope module xp_ad18 $end $var wire 1 m! xp_ad18_gmux_out $end $upscope $end $scope module xp_ad19 $end $var wire 1 n! xp_ad19_gmux_out $end $upscope $end $scope module xp_ad20 $end $var wire 1 o! xp_ad20_gmux_out $end $upscope $end $scope module xp_ad21 $end $var wire 1 p! xp_ad21_gmux_out $end $upscope $end $scope module xp_ad22 $end $var wire 1 q! xp_ad22_gmux_out $end $upscope $end $scope module xp_ad23 $end $var wire 1 r! xp_ad23_gmux_out $end $upscope $end $scope module xp_ad24 $end $var wire 1 s! xp_ad24_gmux_out $end $upscope $end $scope module xp_ad25 $end $var wire 1 t! xp_ad25_gmux_out $end $upscope $end $scope module xp_ad26 $end $var wire 1 u! xp_ad26_gmux_out $end $upscope $end $scope module xp_ad27 $end $var wire 1 v! xp_ad27_gmux_out $end $upscope $end $scope module xp_ad28 $end $var wire 1 w! xp_ad28_gmux_out $end $upscope $end $scope module xp_ad29 $end $var wire 1 x! xp_ad29_gmux_out $end $upscope $end $scope module xp_ad30 $end $var wire 1 y! xp_ad30_gmux_out $end $upscope $end $scope module xp_ad31 $end $var wire 1 z! xp_ad31_gmux_out $end $upscope $end $scope module xp_cbe0 $end $var wire 1 {! xp_cbe0_gmux_out $end $upscope $end $scope module xp_cbe1 $end $var wire 1 |! xp_cbe1_gmux_out $end $upscope $end $scope module xp_cbe2 $end $var wire 1 }! xp_cbe2_gmux_out $end $upscope $end $scope module xp_cbe3 $end $var wire 1 ~! xp_cbe3_gmux_out $end $upscope $end $scope module xp_devsel $end $var wire 1 !" xp_devsel_gmux_out $end $upscope $end $scope module xp_frame $end $var wire 1 "" xp_frame_gmux_out $end $upscope $end $scope module xp_irdy $end $var wire 1 #" xp_irdy_gmux_out $end $upscope $end $scope module xp_par $end $var wire 1 $" xp_par_gmux_out $end $upscope $end $scope module xp_perr $end $var wire 1 %" xp_perr_gmux_out $end $upscope $end $scope module xp_req $end $var wire 1 &" gmux_out $end $upscope $end $scope module xp_stop $end $var wire 1 '" xp_stop_gmux_out $end $upscope $end $scope module xp_trdy $end $var wire 1 (" xp_trdy_gmux_out $end $upscope $end $scope module xs_ad0 $end $var wire 1 )" xs_ad0_gmux_out $end $upscope $end $scope module xs_ad1 $end $var wire 1 *" xs_ad1_gmux_out $end $upscope $end $scope module xs_ad2 $end $var wire 1 +" xs_ad2_gmux_out $end $upscope $end $scope module xs_ad3 $end $var wire 1 ," xs_ad3_gmux_out $end $upscope $end $scope module xs_ad4 $end $var wire 1 -" xs_ad4_gmux_out $end $upscope $end $scope module xs_ad5 $end $var wire 1 ." xs_ad5_gmux_out $end $upscope $end $scope module xs_ad6 $end $var wire 1 /" xs_ad6_gmux_out $end $upscope $end $scope module xs_ad7 $end $var wire 1 0" xs_ad7_gmux_out $end $upscope $end $scope module xs_ad8 $end $var wire 1 1" xs_ad8_gmux_out $end $upscope $end $scope module xs_ad9 $end $var wire 1 2" xs_ad9_gmux_out $end $upscope $end $scope module xs_ad10 $end $var wire 1 3" xs_ad10_gmux_out $end $upscope $end $scope module xs_ad11 $end $var wire 1 4" xs_ad11_gmux_out $end $upscope $end $scope module xs_ad12 $end $var wire 1 5" xs_ad12_gmux_out $end $upscope $end $scope module xs_ad13 $end $var wire 1 6" xs_ad13_gmux_out $end $upscope $end $scope module xs_ad14 $end $var wire 1 7" xs_ad14_gmux_out $end $upscope $end $scope module xs_ad15 $end $var wire 1 8" xs_ad15_gmux_out $end $upscope $end $scope module xs_ad16 $end $var wire 1 9" xs_ad16_gmux_out $end $upscope $end $scope module xs_ad17 $end $var wire 1 :" xs_ad17_gmux_out $end $upscope $end $scope module xs_ad18 $end $var wire 1 ;" xs_ad18_gmux_out $end $upscope $end $scope module xs_ad19 $end $var wire 1 <" xs_ad19_gmux_out $end $upscope $end $scope module xs_ad20 $end $var wire 1 =" xs_ad20_gmux_out $end $upscope $end $scope module xs_ad21 $end $var wire 1 >" xs_ad21_gmux_out $end $upscope $end $scope module xs_ad22 $end $var wire 1 ?" xs_ad22_gmux_out $end $upscope $end $scope module xs_ad23 $end $var wire 1 @" xs_ad23_gmux_out $end $upscope $end $scope module xs_ad24 $end $var wire 1 A" xs_ad24_gmux_out $end $upscope $end $scope module xs_ad25 $end $var wire 1 B" xs_ad25_gmux_out $end $upscope $end $scope module xs_ad26 $end $var wire 1 C" xs_ad26_gmux_out $end $upscope $end $scope module xs_ad27 $end $var wire 1 D" xs_ad27_gmux_out $end $upscope $end $scope module xs_ad28 $end $var wire 1 E" xs_ad28_gmux_out $end $upscope $end $scope module xs_ad29 $end $var wire 1 F" xs_ad29_gmux_out $end $upscope $end $scope module xs_ad30 $end $var wire 1 G" xs_ad30_gmux_out $end $upscope $end $scope module xs_ad31 $end $var wire 1 H" xs_ad31_gmux_out $end $upscope $end $scope module xs_cbe0 $end $var wire 1 I" xs_cbe0_gmux_out $end $upscope $end $scope module xs_cbe1 $end $var wire 1 J" xs_cbe1_gmux_out $end $upscope $end $scope module xs_cbe2 $end $var wire 1 K" xs_cbe2_gmux_out $end $upscope $end $scope module xs_cbe3 $end $var wire 1 L" xs_cbe3_gmux_out $end $upscope $end $scope module xs_devsel $end $var wire 1 M" xs_devsel_gmux_out $end $upscope $end $scope module xs_frame $end $var wire 1 N" xs_frame_gmux_out $end $upscope $end $scope module xs_gnt1 $end $var wire 1 O" gmux_out $end $upscope $end $scope module xs_gnt2 $end $var wire 1 P" gmux_out $end $upscope $end $scope module xs_gnt3 $end $var wire 1 Q" gmux_out $end $upscope $end $scope module xs_gnt4 $end $var wire 1 R" gmux_out $end $upscope $end $scope module xs_gnt5 $end $var wire 1 S" gmux_out $end $upscope $end $scope module xs_gnt6 $end $var wire 1 T" gmux_out $end $upscope $end $scope module xs_gnt7 $end $var wire 1 U" gmux_out $end $upscope $end $scope module xs_gnt8 $end $var wire 1 V" gmux_out $end $upscope $end $scope module xs_irdy $end $var wire 1 W" xs_irdy_gmux_out $end $upscope $end $scope module xs_lock $end $var wire 1 X" xs_lock_gmux_out $end $upscope $end $scope module xs_par $end $var wire 1 Y" xs_par_gmux_out $end $upscope $end $scope module xs_perr $end $var wire 1 Z" xs_perr_gmux_out $end $upscope $end $scope module xs_stop $end $var wire 1 [" xs_stop_gmux_out $end $upscope $end $scope module xs_trdy $end $var wire 1 \" xs_trdy_gmux_out $end $upscope $end $scope module xs_gnt0 $end $var wire 1 ]" gmux_out $end $upscope $end $upscope $end $upscope $end $scope begin TDO_check $end $upscope $end $scope begin bsda_tb $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 1! x" x# x$ x% x& x' x( x) x* x+ x, x- x. x/ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x: x; x< x= x> x? x@ xA xB xC xD xE xF xG xH xI xJ xK xL xM xN xO xP xQ xR xS xT xU xV xW xX xY xZ x[ x\ x] x^ x_ x` xa xb xc xd xe xf xg xh xi xj xk xl xm xn xo xp xq xr xs xt xu xv xw xx xy xz x{ x| x} x~ x!! x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x,! x-! x.! x/! x0! x1! x2! x3! x4! x5! x6! x7! x8! x9! x:! x;! x! x?! x@! xA! xB! xC! xD! xE! xF! xG! xH! xI! xJ! xK! xL! xM! xN! xO! zP! zQ! xR! zS! zT! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" $end #10000 0! #15000 0% 0" x) x* z$ #20000 1! #30000 0! #35000 1% #40000 1! #50000 0! #60000 1! #70000 0! #80000 1! #90000 0! #95000 1I! 1H! 1G! 1F! 1E! 1D! 1C! 1B! 1A! 1@! 1N! 1( 1M! 1& 1L! 1V 1W 1Y 1Z 1' 1/ #100000 1! #110000 0! #115000 1" #120000 1! #130000 0! #135000 0" #140000 1! #150000 0! #160000 1! #170000 0! 0$ #175000 1" #180000 1! #190000 0! x$ z$ #200000 1! #210000 0! #215000 0" #220000 1! #230000 0! #235000 1" #240000 1! #250000 0! #260000 1! #270000 0! #275000 0" #280000 1! #290000 0! #300000 1! #310000 0! 1$ #315000 1# #320000 1! #330000 0! 0$ #340000 1! #350000 0! #360000 1! #370000 0! #380000 1! #390000 0! #395000 1" #400000 1! #410000 0! 1$ z$ #415000 0# #420000 1! #430000 0! #435000 0" #440000 1! #450000 0! #455000 1" #460000 1! #470000 0! #480000 1! #490000 0! #500000 1! #510000 0! #520000 1! #530000 0! #540000 1! #550000 0! #560000 1! #570000 0! #575000 0" #580000 1! #590000 0! #600000 1! #610000 0! #615000 1" #620000 1! #630000 0! #640000 1! #650000 0! #655000 0" #660000 1! #670000 0! #680000 1! #690000 0! 1$ #695000 1# #700000 1! #710000 0! 0$ #720000 1! #730000 0! #740000 1! #750000 0! #755000 0# #760000 1! #770000 0! #780000 1! #790000 0! 1$ #795000 1# #800000 1! #810000 0! #815000 0# 1" #820000 1! #830000 0! z$ #835000 0" #840000 1! #850000 0! #860000 1! #870000 0! #880000 1! #890000 0! #900000 1! #910000 0! #920000 1! #930000 0! #940000 1! #950000 0! #955000 1" #960000 1! #970000 0! #975000 0" #980000 1! #990000 0! 1$ #995000 1# #1000000 1! #1010000 0! 0$ #1015000 0# #1020000 1! #1030000 0! #1040000 1! #1050000 0! 1$ #1060000 1! #1070000 0! 0$ #1080000 1! #1090000 0! 1$ #1100000 1! #1110000 0! 0$ #1115000 1" #1120000 1! #1130000 0! z$ #1140000 1! #1150000 0! 0U! 0V! 0W! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0f! 0g! 0h! 0i! 0j! 0k! 0l! 0m! 0n! 0o! 0p! 0q! 0r! 0s! 0t! 0u! 0v! 0w! 0x! 0y! 0z! 0{! 0|! 0}! 0~! 0!" 0"" 0#" 0$" 0%" 0&" 0'" 0(" 0)" 0*" 0+" 0," 0-" 0." 0/" 00" 01" 02" 03" 04" 05" 06" 07" 08" 09" 0:" 0;" 0<" 0=" 0>" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" x]" x\" x[" xZ" xY" xX" xW" xV" xU" xT" xS" xR" xQ" xP" xO" xN" xM" xL" xK" xJ" xI" xH" xG" xF" xE" xD" xC" xB" xA" x@" x?" x>" x=" x<" x;" x:" x9" x8" x7" x6" x5" x4" x3" x2" x1" x0" x/" x." x-" x," x+" x*" x)" x(" x'" x&" x%" x$" x#" x"" x!" x~! x}! x|! x{! xz! xy! xx! xw! xv! xu! xt! xs! xr! xq! xp! xo! xn! xm! xl! xk! xj! xi! xh! xg! xf! xe! xd! xc! xb! xa! x`! x_! x^! x]! x\! x[! xZ! xY! xX! xW! xV! xU! x) x* #1160000 1! #1170000 0! #1180000 1! #1190000 0! #1195000 0" #1200000 1! #1210000 0! #1215000 1" #1220000 1! #1230000 0! #1235000 0" #1240000 1! #1250000 0! #1260000 1! #1270000 0! #1275000 1" #1280000 1! #1290000 0! #1295000 0" #1300000 1! #1310000 0! 1$ #1320000 1! #1330000 0! 0$ #1340000 1! #1350000 0! #1360000 1! #1370000 0! #1380000 1! #1390000 0! #1395000 1" #1400000 1! #1410000 0! z$ #1415000 0" #1420000 1! #1430000 0! #1435000 1" #1440000 1! #1450000 0! #1460000 1! #1470000 0! #1475000 0" #1480000 1! #1490000 0! #1500000 1! #1510000 0! #1515000 1" #1520000 1! #1530000 0! #1535000 0" #1540000 1! #1550000 0! #1560000 1! #1570000 0! x$ #1575000 1# #1580000 1! #1590000 0! #1600000 1! #1610000 0! #1620000 1! #1630000 0! #1635000 0# #1640000 1! #1650000 0! #1660000 1! #1670000 0! #1675000 1# #1680000 1! #1690000 0! #1695000 0# #1700000 1! #1710000 0! #1715000 1# #1720000 1! #1730000 0! #1735000 0# #1740000 1! #1750000 0! #1760000 1! #1770000 0! #1780000 1! #1790000 0! 0$ #1800000 1! #1810000 0! x$ #1820000 1! #1830000 0! #1840000 1! #1850000 0! #1860000 1! #1870000 0! #1880000 1! #1890000 0! #1900000 1! #1910000 0! #1920000 1! #1930000 0! #1940000 1! #1950000 0! #1960000 1! #1970000 0! #1980000 1! #1990000 0! 1$ #2000000 1! #2010000 0! x$ #2020000 1! #2030000 0! #2040000 1! #2050000 0! #2060000 1! #2070000 0! #2080000 1! #2090000 0! #2100000 1! #2110000 0! #2120000 1! #2130000 0! #2140000 1! #2150000 0! #2160000 1! #2170000 0! #2180000 1! #2190000 0! #2200000 1! #2210000 0! #2220000 1! #2230000 0! #2240000 1! #2250000 0! #2260000 1! #2270000 0! #2280000 1! #2290000 0! #2300000 1! #2310000 0! #2320000 1! #2330000 0! #2340000 1! #2350000 0! #2360000 1! #2370000 0! #2380000 1! #2390000 0! #2400000 1! #2410000 0! #2420000 1! #2430000 0! #2440000 1! #2450000 0! #2460000 1! #2470000 0! #2480000 1! #2490000 0! #2500000 1! #2510000 0! #2520000 1! #2530000 0! #2540000 1! #2550000 0! 1$ #2560000 1! #2570000 0! #2580000 1! #2590000 0! #2600000 1! #2610000 0! #2620000 1! #2630000 0! #2640000 1! #2650000 0! #2660000 1! #2670000 0! #2680000 1! #2690000 0! #2700000 1! #2710000 0! #2720000 1! #2730000 0! x$ #2740000 1! #2750000 0! #2760000 1! #2770000 0! #2780000 1! #2790000 0! #2800000 1! #2810000 0! #2820000 1! #2830000 0! #2840000 1! #2850000 0! #2860000 1! #2870000 0! #2880000 1! #2890000 0! #2900000 1! #2910000 0! #2920000 1! #2930000 0! 1$ #2940000 1! #2950000 0! x$ #2960000 1! #2970000 0! 1$ #2980000 1! #2990000 0! x$ #3000000 1! #3010000 0! #3020000 1! #3030000 0! #3040000 1! #3050000 0! #3060000 1! #3070000 0! #3080000 1! #3090000 0! #3100000 1! #3110000 0! #3120000 1! #3130000 0! #3140000 1! #3150000 0! #3160000 1! #3170000 0! #3180000 1! #3190000 0! #3200000 1! #3210000 0! #3220000 1! #3230000 0! #3240000 1! #3250000 0! #3260000 1! #3270000 0! #3280000 1! #3290000 0! 1$ #3300000 1! #3310000 0! #3320000 1! #3330000 0! #3340000 1! #3350000 0! #3360000 1! #3370000 0! x$ #3380000 1! #3390000 0! #3400000 1! #3410000 0! #3420000 1! #3430000 0! #3440000 1! #3450000 0! #3460000 1! #3470000 0! #3480000 1! #3490000 0! #3500000 1! #3510000 0! #3520000 1! #3530000 0! #3540000 1! #3550000 0! #3560000 1! #3570000 0! #3580000 1! #3590000 0! 1$ #3600000 1! #3610000 0! x$ #3620000 1! #3630000 0! #3640000 1! #3650000 0! #3660000 1! #3670000 0! #3680000 1! #3690000 0! #3700000 1! #3710000 0! #3720000 1! #3730000 0! #3740000 1! #3750000 0! #3760000 1! #3770000 0! #3780000 1! #3790000 0! #3800000 1! #3810000 0! #3820000 1! #3830000 0! #3840000 1! #3850000 0! #3860000 1! #3870000 0! #3880000 1! #3890000 0! #3900000 1! #3910000 0! #3920000 1! #3930000 0! 1$ #3940000 1! #3950000 0! x$ #3960000 1! #3970000 0! 0$ #3980000 1! #3990000 0! x$ #4000000 1! #4010000 0! #4020000 1! #4030000 0! #4040000 1! #4050000 0! #4060000 1! #4070000 0! #4080000 1! #4090000 0! #4100000 1! #4110000 0! #4120000 1! #4130000 0! #4140000 1! #4150000 0! 1$ #4160000 1! #4170000 0! x$ #4180000 1! #4190000 0! #4200000 1! #4210000 0! #4220000 1! #4230000 0! #4240000 1! #4250000 0! #4260000 1! #4270000 0! #4280000 1! #4290000 0! #4300000 1! #4310000 0! #4320000 1! #4330000 0! #4340000 1! #4350000 0! #4360000 1! #4370000 0! #4380000 1! #4390000 0! #4400000 1! #4410000 0! 1$ #4420000 1! #4430000 0! #4440000 1! #4450000 0! #4460000 1! #4470000 0! #4475000 1" #4480000 1! #4490000 0! z$ #4495000 0" #4500000 1! #4510000 0! #4520000 1! #4530000 0! #4540000 1! #4550000 0! #4560000 1! #4570000 0! #4580000 1! #4590000 0! #4600000 1! #4610000 0! #4615000 1" #4620000 1! #4630000 0! #4635000 0" #4640000 1! #4650000 0! 1$ #4660000 1! #4670000 0! 0$ #4680000 1! #4690000 0! #4700000 1! #4710000 0! 1$ #4720000 1! #4730000 0! 0$ #4740000 1! #4750000 0! 1$ #4760000 1! #4770000 0! 0$ #4775000 1" #4780000 1! #4790000 0! z$ #4800000 1! #4810000 0! 0&" 0(" 0'" 0%" 0#" 0"" 0!" 0U! 0Z! 0Y! 0X! 0W! 0V" 0]" 0U" 0T" 0S" 0R" 0Q" 0P" 0O" 0\" 0[" 0Z" 0X" 0W" 0N" 0M" 0]! 0\! 0[! 0{! 0d! 0c! 0b! 0a! 0`! 0_! 0^! 0$" 0|! 0j! 0i! 0h! 0g! 0f! 0e! 0}! 0k! 0~! 0r! 0q! 0p! 0o! 0n! 0m! 0l! 0z! 0y! 0x! 0w! 0v! 0u! 0t! 0s! 0H" 0G" 0L" 0F" 0E" 0D" 0C" 0B" 0A" 0@" 0K" 0?" 0>" 0=" 0<" 0;" 0:" 09" 0Y" 0J" 08" 07" 0I" 06" 05" 04" 03" 02" 01" 0V! 00" 0/" 0." 0-" 0," 0+" 0*" 0)" 0) 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 0* 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* x) xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" x]" x\" x[" xZ" xY" xX" xW" xV" xU" xT" xS" xR" xQ" xP" xO" xN" xM" xL" xK" xJ" xI" xH" xG" xF" xE" xD" xC" xB" xA" x@" x?" x>" x=" x<" x;" x:" x9" x8" x7" x6" x5" x4" x3" x2" x1" x0" x/" x." x-" x," x+" x*" x)" x(" x'" x&" x%" x$" x#" x"" x!" x~! x}! x|! x{! xz! xy! xx! xw! xv! xu! xt! xs! xr! xq! xp! xo! xn! xm! xl! xk! xj! xi! xh! xg! xf! xe! xd! xc! xb! xa! x`! x_! x^! x]! x\! x[! xZ! xY! xX! xW! xV! xU! x) x* #18375000 0" #18380000 1! #18390000 0! #18395000 1" #18400000 1! #18410000 0! #18415000 0" #18420000 1! #18430000 0! #18440000 1! #18450000 0! x$ #18460000 1! #18470000 0! #18480000 1! #18490000 0! #18500000 1! #18510000 0! #18520000 1! #18530000 0! #18540000 1! #18550000 0! #18560000 1! #18570000 0! #18580000 1! #18590000 0! #18600000 1! #18610000 0! #18620000 1! #18630000 0! #18640000 1! #18650000 0! #18660000 1! #18670000 0! 0$ #18680000 1! #18690000 0! x$ #18700000 1! #18710000 0! #18720000 1! #18730000 0! #18740000 1! #18750000 0! #18760000 1! #18770000 0! #18780000 1! #18790000 0! #18800000 1! #18810000 0! #18815000 1# #18820000 1! #18830000 0! #18835000 0# #18840000 1! #18850000 0! #18860000 1! #18870000 0! 1$ #18880000 1! #18890000 0! x$ #18900000 1! #18910000 0! #18920000 1! #18930000 0! #18940000 1! #18950000 0! #18955000 1# #18960000 1! #18970000 0! #18975000 0# #18980000 1! #18990000 0! #19000000 1! #19010000 0! #19020000 1! #19030000 0! #19040000 1! #19050000 0! #19060000 1! #19070000 0! #19080000 1! #19090000 0! #19100000 1! #19110000 0! #19120000 1! #19130000 0! #19140000 1! #19150000 0! #19160000 1! #19170000 0! #19180000 1! #19190000 0! #19200000 1! #19210000 0! #19220000 1! #19230000 0! #19240000 1! #19250000 0! #19260000 1! #19270000 0! #19280000 1! #19290000 0! #19300000 1! #19310000 0! #19320000 1! #19330000 0! #19340000 1! #19350000 0! #19360000 1! #19370000 0! #19380000 1! #19390000 0! #19395000 1# #19400000 1! #19410000 0! #19415000 0# #19420000 1! #19430000 0! 0$ #19440000 1! #19450000 0! 1$ #19460000 1! #19470000 0! 0$ #19480000 1! #19490000 0! 1$ #19500000 1! #19510000 0! 0$ #19520000 1! #19530000 0! 1$ #19540000 1! #19550000 0! 0$ #19560000 1! #19570000 0! 1$ #19580000 1! #19590000 0! 0$ #19600000 1! #19610000 0! x$ #19620000 1! #19630000 0! #19640000 1! #19650000 0! #19655000 1# #19660000 1! #19670000 0! #19675000 0# #19680000 1! #19690000 0! #19700000 1! #19710000 0! #19720000 1! #19730000 0! #19740000 1! #19750000 0! #19760000 1! #19770000 0! #19780000 1! #19790000 0! #19800000 1! #19810000 0! 1$ #19820000 1! #19830000 0! x$ #19840000 1! #19850000 0! 0$ #19860000 1! #19870000 0! x$ #19880000 1! #19890000 0! #19900000 1! #19910000 0! #19920000 1! #19930000 0! #19940000 1! #19950000 0! #19960000 1! #19970000 0! #19980000 1! #19990000 0! #19995000 1# #20000000 1! #20010000 0! #20015000 0# #20020000 1! #20030000 0! #20040000 1! #20050000 0! #20060000 1! #20070000 0! #20080000 1! #20090000 0! #20100000 1! #20110000 0! #20120000 1! #20130000 0! #20140000 1! #20150000 0! #20160000 1! #20170000 0! 1$ #20180000 1! #20190000 0! 0$ #20200000 1! #20210000 0! 1$ #20220000 1! #20230000 0! 0$ #20240000 1! #20250000 0! x$ #20260000 1! #20270000 0! #20275000 1# #20280000 1! #20290000 0! #20295000 0# #20300000 1! #20310000 0! #20320000 1! #20330000 0! #20340000 1! #20350000 0! #20360000 1! #20370000 0! #20380000 1! #20390000 0! #20400000 1! #20410000 0! #20420000 1! #20430000 0! #20440000 1! #20450000 0! #20460000 1! #20470000 0! 1$ #20480000 1! #20490000 0! x$ #20500000 1! #20510000 0! #20520000 1! #20530000 0! #20540000 1! #20550000 0! #20560000 1! #20570000 0! #20580000 1! #20590000 0! #20600000 1! #20610000 0! #20620000 1! #20630000 0! #20640000 1! #20650000 0! #20655000 1# #20660000 1! #20670000 0! #20675000 0# #20680000 1! #20690000 0! #20700000 1! #20710000 0! #20720000 1! #20730000 0! #20740000 1! #20750000 0! #20760000 1! #20770000 0! #20780000 1! #20790000 0! #20795000 1# #20800000 1! #20810000 0! 0$ #20815000 0# #20820000 1! #20830000 0! x$ #20840000 1! #20850000 0! 0$ #20860000 1! #20870000 0! x$ #20880000 1! #20890000 0! #20900000 1! #20910000 0! #20920000 1! #20930000 0! #20940000 1! #20950000 0! #20960000 1! #20970000 0! #20980000 1! #20990000 0! #21000000 1! #21010000 0! #21020000 1! #21030000 0! 1$ #21040000 1! #21050000 0! x$ #21060000 1! #21070000 0! #21080000 1! #21090000 0! #21100000 1! #21110000 0! #21120000 1! #21130000 0! #21140000 1! #21150000 0! #21160000 1! #21170000 0! #21180000 1! #21190000 0! #21200000 1! #21210000 0! #21220000 1! #21230000 0! #21240000 1! #21250000 0! #21260000 1! #21270000 0! #21275000 1# #21280000 1! #21290000 0! 0$ #21295000 0# #21300000 1! #21310000 0! 1$ #21315000 1" #21320000 1! #21330000 0! 0$ z$ #21340000 1! #21350000 0! 1&" 1\" 1[" 1Z" 1X" 1W" 1N" 1M" 1V" 1]" 1U" 1T" 1S" 1R" 1Q" 1P" 1O" 1Z! 1Y! 1X! 1W! 1(" 1'" 1%" 1#" 1"" 1!" 1U! 1Y" 1J" 18" 17" 1I" 16" 15" 14" 13" 12" 11" 1V! 10" 1/" 1." 1-" 1," 1+" 1*" 1)" 1H" 1G" 1L" 1F" 1E" 1D" 1C" 1B" 1A" 1@" 1K" 1?" 1>" 1=" 1<" 1;" 1:" 19" 1}! 1k! 1~! 1r! 1q! 1p! 1o! 1n! 1m! 1l! 1z! 1y! 1x! 1w! 1v! 1u! 1t! 1s! 1]! 1\! 1[! 1{! 1d! 1c! 1b! 1a! 1`! 1_! 1^! 1$" 1|! 1j! 1i! 1h! 1g! 1f! 1e! z* z:! z9! z8! z7! z6! z5! z4! z3! z2! z>! 0+! 0*! 0)! 0(! 0'! 0&! 0%! 0$! 0#! 0"! z] z) z!! z~ z} z| z{ zz zy zx z/! zw zv zu zt zs zr zq zp z.! z=! z?! z z? zQ zU zX z_ zT z^ z\ z[ zR z@ zA zB zC zD zE zF zG zS zH zI zJ zK zL zM zN zO #21355000 0" #21360000 1! #21370000 0! #21375000 0!! 1~ 0} 1| 0{ 1z 0y 1x 0/! 1w 0v 1u 0t 1s 0r 1q 0p 1.! 0=! 0?! 1 1? 0Q 1U 0X 1_ 0T 1^ 1\ 0[ 1R 0@ 1A 0B 1C 0D 1E 0Z 1F 0G 1S 0H 1I 0J 1K 0L 1M 0N 1O 1" #21380000 1! #21390000 0! #21395000 0" #21400000 1! #21410000 0! #21420000 1! #21430000 0! 0$ #21435000 x# #21440000 1! #21450000 0! 1$ #21460000 1! #21470000 0! 0$ #21480000 1! #21490000 0! 1$ #21500000 1! #21510000 0! 0$ #21520000 1! #21530000 0! 1$ #21540000 1! #21550000 0! 0$ #21560000 1! #21570000 0! 1$ #21580000 1! #21590000 0! 0$ #21600000 1! #21610000 0! 1$ #21620000 1! #21630000 0! 0$ #21640000 1! #21650000 0! #21660000 1! #21670000 0! 1$ #21680000 1! #21690000 0! 0$ #21700000 1! #21710000 0! 1$ #21720000 1! #21730000 0! 0$ #21740000 1! #21750000 0! 1$ #21760000 1! #21770000 0! 0$ #21780000 1! #21790000 0! 1$ #21800000 1! #21810000 0! #21820000 1! #21830000 0! 0$ #21840000 1! #21850000 0! 1$ #21860000 1! #21870000 0! 0$ #21880000 1! #21890000 0! 1$ #21900000 1! #21910000 0! 0$ #21920000 1! #21930000 0! 1$ #21940000 1! #21950000 0! #21960000 1! #21970000 0! 0$ #21980000 1! #21990000 0! 1$ #22000000 1! #22010000 0! 0$ #22020000 1! #22030000 0! 1$ #22040000 1! #22050000 0! 0$ #22060000 1! #22070000 0! 1$ #22080000 1! #22090000 0! 0$ #22100000 1! #22110000 0! 1$ #22120000 1! #22130000 0! 0$ #22140000 1! #22150000 0! 1$ #22160000 1! #22170000 0! 0$ #22180000 1! #22190000 0! 1$ #22200000 1! #22210000 0! 0$ #22220000 1! #22230000 0! 1$ #22240000 1! #22250000 0! 0$ #22260000 1! #22270000 0! 1$ #22280000 1! #22290000 0! 0$ #22300000 1! #22310000 0! 1$ #22320000 1! #22330000 0! 0$ #22340000 1! #22350000 0! 1$ #22360000 1! #22370000 0! #22380000 1! #22390000 0! 0$ #22400000 1! #22410000 0! 1$ #22420000 1! #22430000 0! 0$ #22440000 1! #22450000 0! 1$ #22460000 1! #22470000 0! 0$ #22480000 1! #22490000 0! 1$ #22500000 1! #22510000 0! 0$ #22520000 1! #22530000 0! 1$ #22540000 1! #22550000 0! 0$ #22560000 1! #22570000 0! 1$ #22580000 1! #22590000 0! x$ #22600000 1! #22610000 0! #22620000 1! #22630000 0! #22640000 1! #22650000 0! #22660000 1! #22670000 0! #22680000 1! #22690000 0! #22700000 1! #22710000 0! #22720000 1! #22730000 0! #22740000 1! #22750000 0! #22760000 1! #22770000 0! #22780000 1! #22790000 0! 0$ #22800000 1! #22810000 0! x$ #22820000 1! #22830000 0! 1$ #22840000 1! #22850000 0! 0$ #22860000 1! #22870000 0! 1$ #22880000 1! #22890000 0! 0$ #22900000 1! #22910000 0! 1$ #22920000 1! #22930000 0! x$ #22940000 1! #22950000 0! #22960000 1! #22970000 0! 1$ #22980000 1! #22990000 0! x$ #23000000 1! #23010000 0! #23020000 1! #23030000 0! #23040000 1! #23050000 0! #23060000 1! #23070000 0! #23080000 1! #23090000 0! #23100000 1! #23110000 0! #23120000 1! #23130000 0! #23140000 1! #23150000 0! 0$ #23160000 1! #23170000 0! 1$ #23180000 1! #23190000 0! 0$ #23200000 1! #23210000 0! 1$ #23220000 1! #23230000 0! x$ #23240000 1! #23250000 0! #23260000 1! #23270000 0! 0$ #23280000 1! #23290000 0! 1$ #23300000 1! #23310000 0! 0$ #23320000 1! #23330000 0! 1$ #23340000 1! #23350000 0! 0$ #23360000 1! #23370000 0! 1$ #23380000 1! #23390000 0! 0$ #23400000 1! #23410000 0! 1$ #23420000 1! #23430000 0! 0$ #23440000 1! #23450000 0! 1$ #23460000 1! #23470000 0! 0$ #23480000 1! #23490000 0! 1$ #23500000 1! #23510000 0! 0$ #23520000 1! #23530000 0! 1$ #23540000 1! #23550000 0! 0$ #23560000 1! #23570000 0! 1$ #23580000 1! #23590000 0! 0$ #23600000 1! #23610000 0! 1$ #23620000 1! #23630000 0! #23640000 1! #23650000 0! 0$ #23660000 1! #23670000 0! 1$ #23680000 1! #23690000 0! 0$ #23700000 1! #23710000 0! 1$ #23720000 1! #23730000 0! 0$ #23740000 1! #23750000 0! 1$ #23760000 1! #23770000 0! #23780000 1! #23790000 0! 0$ #23800000 1! #23810000 0! 1$ #23820000 1! #23830000 0! 0$ #23840000 1! #23850000 0! #23860000 1! #23870000 0! 1$ #23880000 1! #23890000 0! 0$ #23900000 1! #23910000 0! 1$ #23920000 1! #23930000 0! 0$ #23940000 1! #23950000 0! 1$ #23960000 1! #23970000 0! 0$ #23980000 1! #23990000 0! 1$ #24000000 1! #24010000 0! 0$ #24020000 1! #24030000 0! 1$ #24040000 1! #24050000 0! 0$ #24060000 1! #24070000 0! 1$ #24080000 1! #24090000 0! 0$ #24100000 1! #24110000 0! 1$ #24120000 1! #24130000 0! 0$ #24140000 1! #24150000 0! 1$ #24160000 1! #24170000 0! 0$ #24180000 1! #24190000 0! 1$ #24200000 1! #24210000 0! 0$ #24220000 1! #24230000 0! 1$ #24240000 1! #24250000 0! #24260000 1! #24270000 0! 0$ #24280000 1! #24290000 0! 1$ #24295000 1" #24300000 1! #24310000 0! x$ z$ #24320000 1! #24330000 0! x&" x(" x'" x%" x#" x"" x!" xU! xZ! xY! xX! xW! xV" x]" xU" xT" xS" xR" xQ" xP" xO" x\" x[" xZ" xX" xW" xN" xM" x]! x\! x[! x{! xd! xc! xb! xa! x`! x_! x^! x$" x|! xj! xi! xh! xg! xf! xe! x}! xk! x~! xr! xq! xp! xo! xn! xm! xl! xz! xy! xx! xw! xv! xu! xt! xs! xH" xG" xL" xF" xE" xD" xC" xB" xA" x@" xK" x?" x>" x=" x<" x;" x:" x9" xY" xJ" x8" x7" xI" x6" x5" x4" x3" x2" x1" xV! x0" x/" x." x-" x," x+" x*" x)" x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x* x9! x8! x7! x6! x5! x4! x3! x:! x2! x>! x) x] x!! x~ x} x| x{ xz xy xx xw xv xu xt xs xr x/! xq xp x.! x=! xo xn xm xl xk xj xi x-! xh xg xf xe xd xc xb x,! xa x` x7 x6 x5 x4 x3 x2 x1 x0 x> x= x< x; x: x9 x8 xP x? xQ xE xD xC xB xA x@ xR x[ xL xK xJ xI xH xG xF xS xO xN xM x0! x1! x;! x" 1=" 1<" 1;" 1:" 19" 1}! 1k! 1~! 1r! 1q! 1p! 1o! 1n! 1m! 1l! 1z! 1y! 1x! 1w! 1v! 1u! 1t! 1s! 1]! 1\! 1[! 1{! 1d! 1c! 1b! 1a! 1`! 1_! 1^! 1$" 1|! 1j! 1i! 1h! 1g! 1f! 1e! z* z:! z9! z8! z7! z6! z5! z4! z3! z2! z>! 0+! 0*! 0)! 0(! 0'! 0&! 0%! 0$! 0#! 0"! z] z) z!! z~ z} z| z{ zz zy zx z/! zw zv zu zt zs zr zq zp z.! z=! z?! z z? zQ zU zX z_ zT z^ z\ z[ zR z@ zA zB zC zD zE zF zG zS zH zI zJ zK zL zM zN zO #27535000 0" #27540000 1! #27550000 0! #27555000 1!! 0~ 1} 0| 1{ 0z 1y 0x 1/! 0w 1v 0u 1t 0s 1r 0q 1p 0.! 1=! 0I! 1?! 0 0? 1Q 0U 1X 0_ 1T 0^ 1Y 0\ 1[ 0R 1@ 0A 1B 0C 1D 0E 1Z 0F 1G 0S 1H 0I 1J 0K 1L 0M 1N 0O 1' 0/ 1" #27560000 1! #27570000 0! #27575000 0" #27580000 1! #27590000 0! #27600000 1! #27610000 0! 1$ #27615000 x# #27620000 1! #27630000 0! 0$ #27640000 1! #27650000 0! 1$ #27660000 1! #27670000 0! 0$ #27680000 1! #27690000 0! 1$ #27700000 1! #27710000 0! 0$ #27720000 1! #27730000 0! 1$ #27740000 1! #27750000 0! 0$ #27760000 1! #27770000 0! 1$ #27780000 1! #27790000 0! 0$ #27800000 1! #27810000 0! 1$ #27820000 1! #27830000 0! 0$ #27840000 1! #27850000 0! #27860000 1! #27870000 0! 1$ #27880000 1! #27890000 0! 0$ #27900000 1! #27910000 0! 1$ #27920000 1! #27930000 0! 0$ #27940000 1! #27950000 0! 1$ #27960000 1! #27970000 0! #27980000 1! #27990000 0! 0$ #28000000 1! #28010000 0! 1$ #28020000 1! #28030000 0! 0$ #28040000 1! #28050000 0! 1$ #28060000 1! #28070000 0! 0$ #28080000 1! #28090000 0! 1$ #28100000 1! #28110000 0! #28120000 1! #28130000 0! 0$ #28140000 1! #28150000 0! 1$ #28160000 1! #28170000 0! 0$ #28180000 1! #28190000 0! 1$ #28200000 1! #28210000 0! 0$ #28220000 1! #28230000 0! 1$ #28240000 1! #28250000 0! 0$ #28260000 1! #28270000 0! 1$ #28280000 1! #28290000 0! 0$ #28300000 1! #28310000 0! 1$ #28320000 1! #28330000 0! 0$ #28340000 1! #28350000 0! 1$ #28360000 1! #28370000 0! 0$ #28380000 1! #28390000 0! 1$ #28400000 1! #28410000 0! 0$ #28420000 1! #28430000 0! 1$ #28440000 1! #28450000 0! 0$ #28460000 1! #28470000 0! 1$ #28480000 1! #28490000 0! 0$ #28500000 1! #28510000 0! 1$ #28520000 1! #28530000 0! 0$ #28540000 1! #28550000 0! 1$ #28560000 1! #28570000 0! #28580000 1! #28590000 0! 0$ #28600000 1! #28610000 0! 1$ #28620000 1! #28630000 0! 0$ #28640000 1! #28650000 0! 1$ #28660000 1! #28670000 0! 0$ #28680000 1! #28690000 0! 1$ #28700000 1! #28710000 0! 0$ #28720000 1! #28730000 0! 1$ #28740000 1! #28750000 0! 0$ #28760000 1! #28770000 0! x$ #28780000 1! #28790000 0! #28800000 1! #28810000 0! #28820000 1! #28830000 0! #28840000 1! #28850000 0! #28860000 1! #28870000 0! #28880000 1! #28890000 0! #28900000 1! #28910000 0! #28920000 1! #28930000 0! #28940000 1! #28950000 0! #28960000 1! #28970000 0! 1$ #28980000 1! #28990000 0! x$ #29000000 1! #29010000 0! 0$ #29020000 1! #29030000 0! 1$ #29040000 1! #29050000 0! 0$ #29060000 1! #29070000 0! 1$ #29080000 1! #29090000 0! 0$ #29100000 1! #29110000 0! x$ #29120000 1! #29130000 0! #29140000 1! #29150000 0! 1$ #29160000 1! #29170000 0! x$ #29180000 1! #29190000 0! #29200000 1! #29210000 0! #29220000 1! #29230000 0! #29240000 1! #29250000 0! #29260000 1! #29270000 0! #29280000 1! #29290000 0! #29300000 1! #29310000 0! #29320000 1! #29330000 0! 1$ #29340000 1! #29350000 0! 0$ #29360000 1! #29370000 0! 1$ #29380000 1! #29390000 0! 0$ #29400000 1! #29410000 0! x$ #29420000 1! #29430000 0! #29440000 1! #29450000 0! 1$ #29460000 1! #29470000 0! 0$ #29480000 1! #29490000 0! 1$ #29500000 1! #29510000 0! 0$ #29520000 1! #29530000 0! 1$ #29540000 1! #29550000 0! 0$ #29560000 1! #29570000 0! 1$ #29580000 1! #29590000 0! 0$ #29600000 1! #29610000 0! 1$ #29620000 1! #29630000 0! 0$ #29640000 1! #29650000 0! 1$ #29660000 1! #29670000 0! 0$ #29680000 1! #29690000 0! 1$ #29700000 1! #29710000 0! 0$ #29720000 1! #29730000 0! 1$ #29740000 1! #29750000 0! 0$ #29760000 1! #29770000 0! 1$ #29780000 1! #29790000 0! 0$ #29800000 1! #29810000 0! 1$ #29820000 1! #29830000 0! #29840000 1! #29850000 0! 0$ #29860000 1! #29870000 0! 1$ #29880000 1! #29890000 0! 0$ #29900000 1! #29910000 0! 1$ #29920000 1! #29930000 0! 0$ #29940000 1! #29950000 0! 1$ #29960000 1! #29970000 0! #29980000 1! #29990000 0! 0$ #30000000 1! #30010000 0! #30020000 1! #30030000 0! 1$ #30040000 1! #30050000 0! 0$ #30060000 1! #30070000 0! 1$ #30080000 1! #30090000 0! 0$ #30100000 1! #30110000 0! 1$ #30120000 1! #30130000 0! 0$ #30140000 1! #30150000 0! 1$ #30160000 1! #30170000 0! 0$ #30180000 1! #30190000 0! 1$ #30200000 1! #30210000 0! 0$ #30220000 1! #30230000 0! 1$ #30240000 1! #30250000 0! 0$ #30260000 1! #30270000 0! 1$ #30280000 1! #30290000 0! 0$ #30300000 1! #30310000 0! 1$ #30320000 1! #30330000 0! 0$ #30340000 1! #30350000 0! 1$ #30360000 1! #30370000 0! 0$ #30380000 1! #30390000 0! 1$ #30400000 1! #30410000 0! 0$ #30420000 1! #30430000 0! 1$ #30440000 1! #30450000 0! #30460000 1! #30470000 0! 0$ #30475000 1" #30480000 1! #30490000 0! x$ z$ #30500000 1! #30510000 0! x&" x(" x'" x%" x#" x"" x!" xU! xZ! xY! xX! xW! xV" x]" xU" xT" xS" xR" xQ" xP" xO" x\" x[" xZ" xX" xW" xN" xM" x]! x\! x[! x{! xd! xc! xb! xa! x`! x_! x^! x$" x|! xj! xi! xh! xg! xf! xe! x}! xk! x~! xr! xq! xp! xo! xn! xm! xl! xz! xy! xx! xw! xv! xu! xt! xs! xH" xG" xL" xF" xE" xD" xC" xB" xA" x@" xK" x?" x>" x=" x<" x;" x:" x9" xY" xJ" x8" x7" xI" x6" x5" x4" x3" x2" x1" xV! x0" x/" x." x-" x," x+" x*" x)" x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x* x9! x8! x7! x6! x5! x4! x3! x:! x2! x>! x) x] x!! x~ x} x| x{ xz xy xx xw xv xu xt xs xr x/! xq xp x.! x=! xo xn xm xl xk xj xi x-! xh xg xf xe xd xc xb x,! xa x` x7 x6 x5 x4 x3 x2 x1 x0 x> x= x< x; x: x9 x8 xP x? xQ xE xD xC xB xA x@ xR x[ xL xK xJ xI xH xG xF xS xO xN xM x0! x1! x;! x" 1?" 1@" 1A" 1B" 1C" 1D" 1E" 1F" 1G" 1H" 1I" 1J" 1K" 1L" 1M" 1N" 1O" 1P" 1Q" 1R" 1S" 1T" 1U" 1V" 1W" 1X" 1Y" 1Z" 1[" 1\" 1]" z#! z$! z%! z&! z'! z(! z)! z*! z+! z) z* z:! z>! z2! z3! z4! z5! z6! z7! z8! z9! z"! z] zK! zJ! z?! z=! z z? z@ zA zB zC zD zE zF zG zH zI zJ zK zL zM zN zO z+ z, z- z. #30955000 0" #30960000 1! #30970000 0! #30975000 1" #30980000 1! #30990000 0! #30995000 0" #31000000 1! #31010000 0! #31020000 1! #31030000 0! 0$ #31035000 1# #31040000 1! #31050000 0! 1$ #31060000 1! #31070000 0! #31080000 1! #31090000 0! #31100000 1! #31110000 0! #31120000 1! #31130000 0! #31135000 0# #31140000 1! #31150000 0! 0$ #31160000 1! #31170000 0! #31175000 1# #31180000 1! #31190000 0! 1$ #31200000 1! #31210000 0! #31220000 1! #31230000 0! #31240000 1! #31250000 0! #31255000 0# 1" #31260000 1! #31270000 0! 0$ z$ #31280000 1! #31290000 0! #31295000 0" #31300000 1! #31310000 0! #31315000 1" #31320000 1! #31330000 0! #31340000 1! #31350000 0! #31355000 0" #31360000 1! #31370000 0! #31380000 1! #31390000 0! 1$ #31395000 1# #31400000 1! #31410000 0! 0$ #31415000 0# #31420000 1! #31430000 0! #31440000 1! #31450000 0! #31460000 1! #31470000 0! #31475000 1" #31480000 1! #31490000 0! 1$ z$ #31500000 1! #31510000 0! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x#! x$! x%! x&! x'! x(! x)! x*! x+! x:! x>! x2! x3! x4! x5! x6! x7! x8! x9! x"! x] x* x) xK! xJ! x?! x=! x x? x@ xA xB xC xD xE xF xG xH xI xJ xK xL xM xN xO x+ x, x- x. #31515000 0" #31520000 1! #31530000 0! #31535000 1" #31540000 1! #31550000 0! #31555000 0" #31560000 1! #31570000 0! #31580000 1! #31590000 0! x$ #31600000 1! #31610000 0! #31620000 1! #31630000 0! #31640000 1! #31650000 0! #31660000 1! #31670000 0! #31680000 1! #31690000 0! #31700000 1! #31710000 0! #31720000 1! #31730000 0! #31740000 1! #31750000 0! #31760000 1! #31770000 0! #31780000 1! #31790000 0! #31800000 1! #31810000 0! 0$ #31820000 1! #31830000 0! x$ #31840000 1! #31850000 0! #31860000 1! #31870000 0! #31880000 1! #31890000 0! #31900000 1! #31910000 0! #31920000 1! #31930000 0! #31940000 1! #31950000 0! #31960000 1! #31970000 0! #31980000 1! #31990000 0! #32000000 1! #32010000 0! 0$ #32015000 1# #32020000 1! #32030000 0! x$ #32035000 0# #32040000 1! #32050000 0! #32060000 1! #32070000 0! #32080000 1! #32090000 0! #32100000 1! #32110000 0! #32120000 1! #32130000 0! #32140000 1! #32150000 0! #32160000 1! #32170000 0! #32180000 1! #32190000 0! #32200000 1! #32210000 0! #32220000 1! #32230000 0! #32240000 1! #32250000 0! #32260000 1! #32270000 0! #32280000 1! #32290000 0! #32300000 1! #32310000 0! #32320000 1! #32330000 0! #32340000 1! #32350000 0! #32360000 1! #32370000 0! #32380000 1! #32390000 0! #32400000 1! #32410000 0! #32420000 1! #32430000 0! #32440000 1! #32450000 0! #32460000 1! #32470000 0! #32480000 1! #32490000 0! #32500000 1! #32510000 0! #32520000 1! #32530000 0! #32540000 1! #32550000 0! #32560000 1! #32570000 0! 0$ #32575000 1# #32580000 1! #32590000 0! 1$ #32600000 1! #32610000 0! 0$ #32620000 1! #32630000 0! 1$ #32640000 1! #32650000 0! 0$ #32660000 1! #32670000 0! 1$ #32680000 1! #32690000 0! 0$ #32700000 1! #32710000 0! 1$ #32720000 1! #32730000 0! 0$ #32740000 1! #32750000 0! x$ #32755000 0# #32760000 1! #32770000 0! #32780000 1! #32790000 0! #32800000 1! #32810000 0! #32820000 1! #32830000 0! #32840000 1! #32850000 0! #32860000 1! #32870000 0! #32880000 1! #32890000 0! #32900000 1! #32910000 0! #32920000 1! #32930000 0! #32940000 1! #32950000 0! 1$ #32955000 1# #32960000 1! #32970000 0! x$ #32975000 0# #32980000 1! #32990000 0! 0$ #32995000 1# #33000000 1! #33010000 0! x$ #33015000 0# #33020000 1! #33030000 0! #33040000 1! #33050000 0! #33060000 1! #33070000 0! #33080000 1! #33090000 0! #33100000 1! #33110000 0! #33120000 1! #33130000 0! #33140000 1! #33150000 0! #33160000 1! #33170000 0! #33180000 1! #33190000 0! #33200000 1! #33210000 0! #33220000 1! #33230000 0! #33240000 1! #33250000 0! #33260000 1! #33270000 0! #33280000 1! #33290000 0! #33300000 1! #33310000 0! 1$ #33315000 1# #33320000 1! #33330000 0! 0$ #33340000 1! #33350000 0! 1$ #33360000 1! #33370000 0! 0$ #33380000 1! #33390000 0! x$ #33395000 0# #33400000 1! #33410000 0! #33420000 1! #33430000 0! #33440000 1! #33450000 0! #33460000 1! #33470000 0! #33480000 1! #33490000 0! #33500000 1! #33510000 0! #33520000 1! #33530000 0! #33540000 1! #33550000 0! #33560000 1! #33570000 0! #33580000 1! #33590000 0! #33600000 1! #33610000 0! 0$ #33615000 1# #33620000 1! #33630000 0! x$ #33635000 0# #33640000 1! #33650000 0! #33660000 1! #33670000 0! #33680000 1! #33690000 0! #33700000 1! #33710000 0! #33720000 1! #33730000 0! #33740000 1! #33750000 0! #33760000 1! #33770000 0! #33780000 1! #33790000 0! #33800000 1! #33810000 0! #33820000 1! #33830000 0! #33840000 1! #33850000 0! #33860000 1! #33870000 0! #33880000 1! #33890000 0! #33900000 1! #33910000 0! #33920000 1! #33930000 0! #33940000 1! #33950000 0! 1$ #33955000 1# #33960000 1! #33970000 0! x$ #33975000 0# #33980000 1! #33990000 0! 0$ #34000000 1! #34010000 0! x$ #34020000 1! #34030000 0! #34040000 1! #34050000 0! #34060000 1! #34070000 0! #34080000 1! #34090000 0! #34100000 1! #34110000 0! #34120000 1! #34130000 0! #34140000 1! #34150000 0! #34160000 1! #34170000 0! 1$ #34175000 1# #34180000 1! #34190000 0! x$ #34195000 0# #34200000 1! #34210000 0! #34220000 1! #34230000 0! #34240000 1! #34250000 0! #34260000 1! #34270000 0! #34280000 1! #34290000 0! #34300000 1! #34310000 0! #34320000 1! #34330000 0! #34340000 1! #34350000 0! #34360000 1! #34370000 0! #34380000 1! #34390000 0! #34400000 1! #34410000 0! #34420000 1! #34430000 0! 1$ #34435000 1# #34440000 1! #34450000 0! 0$ #34455000 1" #34460000 1! #34470000 0! z$ #34480000 1! #34490000 0! #34495000 0" #34500000 1! #34510000 0! #34515000 1" #34520000 1! #34530000 0! #34540000 1! #34550000 0! #34555000 0" #34560000 1! #34570000 0! #34580000 1! #34590000 0! 1$ #34595000 0# #34600000 1! #34610000 0! 0$ #34620000 1! #34630000 0! #34635000 1# #34640000 1! #34650000 0! #34655000 0# #34660000 1! #34670000 0! #34675000 1" #34680000 1! #34690000 0! z$ #34700000 1! #34710000 0! 0U! 0V! 0W! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0f! 0g! 0h! 0i! 0j! 0k! 0l! 0m! 0n! 0o! 0p! 0q! 0r! 0s! 0t! 0u! 0v! 0w! 0x! 0y! 0z! 0{! 0|! 0}! 0~! 0!" 0"" 0#" 0$" 0%" 0&" 0'" 0(" 0)" 0*" 0+" 0," 0-" 0." 0/" 00" 01" 02" 03" 04" 05" 06" 07" 08" 09" 0:" 0;" 0<" 0=" 0>" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 0* 0) 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* x) xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 1* 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x) x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 1] 1"! 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1:! 1* 1O 1N 1M 1L 1K 1J 1I 1H 1S 1G 1F 1E 1D 1C 1B 1A 1@ 1R 1[ 1\ 1^ 1T 1_ 1X 1U 1Q 1? 1> 1= 1< 1; 1: 19 18 1P 17 16 15 14 13 12 11 10 1. 1- 1, 1+ 1` 1a 1b 1c 1d 1e 1f 1g 1,! 1h 1i 1j 1k 1l 1m 1n 1o 1-! 11! 1;! 1K! 10! 1J! 1" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" 1U! 1V! 1W! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1d! 1e! 1f! 1g! 1h! 1i! 1j! 1k! 1l! 1m! 1n! 1o! 1p! 1q! 1r! 1s! 1t! 1u! 1v! 1w! 1x! 1y! 1z! 1{! 1|! 1}! 1~! 1!" 1"" 1#" 1$" 1%" 1&" 1'" 1(" 1)" 1*" 1+" 1," 1-" 1." 1/" 10" 11" 12" 13" 14" 15" 16" 17" 18" 19" 1:" 1;" 1<" 1=" 1>" 1?" 1@" 1A" 1B" 1C" 1D" 1E" 1F" 1G" 1H" 1I" 1J" 1K" 1L" 1M" 1N" 1O" 1P" 1Q" 1R" 1S" 1T" 1U" 1V" 1W" 1X" 1Y" 1Z" 1[" 1\" 1]" z) z] z"! z#! z$! z%! z&! z'! z(! z)! z*! z+! z>! z2! z3! z4! z5! z6! z7! z8! z9! z:! z* zO zN zM zL zK zJ zI zH zS zG zF zE zD zC zB zA z@ zR z[ z\ z^ zT z_ zX zU zQ z? z> z= z< z; z: z9 z8 zP z7 z6 z5 z4 z3 z2 z1 z0 z. z- z, z+ z` za zb zc zd ze zf zg z,! zh zi zj zk zl zm zn zo z-! z1! z;! zK! z0! zJ! z" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1:! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1"! 1] 1* 1) 1K! 1J! 1?! 1=! 1 1? 1@ 1A 1B 1C 1D 1E 1F 1G 1H 1I 1J 1K 1L 1M 1N 1O 1+ 1, 1- 1. #66735000 0" #66740000 1! #66750000 0! #66760000 1! #66770000 0! #66775000 1" #66780000 1! #66790000 0! #66800000 1! #66810000 0! #66815000 0" #66820000 1! #66830000 0! #66840000 1! #66850000 0! 1$ #66860000 1! #66870000 0! 0$ #66880000 1! #66890000 0! #66895000 1# #66900000 1! #66910000 0! #66915000 0# #66920000 1! #66930000 0! #66935000 1" #66940000 1! #66950000 0! z$ #66960000 1! #66970000 0! #66975000 0" #66980000 1! #66990000 0! #66995000 1" #67000000 1! #67010000 0! #67015000 0" #67020000 1! #67030000 0! #67040000 1! #67050000 0! 0$ #67060000 1! #67070000 0! #67080000 1! #67090000 0! #67100000 1! #67110000 0! #67120000 1! #67130000 0! #67140000 1! #67150000 0! #67160000 1! #67170000 0! #67180000 1! #67190000 0! #67200000 1! #67210000 0! #67220000 1! #67230000 0! #67240000 1! #67250000 0! #67260000 1! #67270000 0! #67280000 1! #67290000 0! #67300000 1! #67310000 0! #67320000 1! #67330000 0! #67340000 1! #67350000 0! #67360000 1! #67370000 0! #67380000 1! #67390000 0! #67400000 1! #67410000 0! #67420000 1! #67430000 0! #67440000 1! #67450000 0! #67460000 1! #67470000 0! #67480000 1! #67490000 0! #67500000 1! #67510000 0! #67520000 1! #67530000 0! #67540000 1! #67550000 0! #67560000 1! #67570000 0! #67580000 1! #67590000 0! #67600000 1! #67610000 0! #67620000 1! #67630000 0! #67640000 1! #67650000 0! #67660000 1! #67670000 0! #67680000 1! #67690000 0! #67700000 1! #67710000 0! #67720000 1! #67730000 0! #67740000 1! #67750000 0! #67760000 1! #67770000 0! #67780000 1! #67790000 0! #67800000 1! #67810000 0! #67820000 1! #67830000 0! #67840000 1! #67850000 0! #67860000 1! #67870000 0! #67880000 1! #67890000 0! #67900000 1! #67910000 0! #67920000 1! #67930000 0! #67940000 1! #67950000 0! #67960000 1! #67970000 0! #67980000 1! #67990000 0! #68000000 1! #68010000 0! #68020000 1! #68030000 0! #68040000 1! #68050000 0! #68060000 1! #68070000 0! #68080000 1! #68090000 0! #68100000 1! #68110000 0! #68120000 1! #68130000 0! #68140000 1! #68150000 0! #68160000 1! #68170000 0! #68180000 1! #68190000 0! #68200000 1! #68210000 0! #68220000 1! #68230000 0! #68240000 1! #68250000 0! #68260000 1! #68270000 0! #68280000 1! #68290000 0! #68300000 1! #68310000 0! #68320000 1! #68330000 0! #68340000 1! #68350000 0! #68360000 1! #68370000 0! #68380000 1! #68390000 0! #68400000 1! #68410000 0! #68420000 1! #68430000 0! #68440000 1! #68450000 0! #68460000 1! #68470000 0! #68480000 1! #68490000 0! #68500000 1! #68510000 0! #68520000 1! #68530000 0! #68540000 1! #68550000 0! #68560000 1! #68570000 0! #68580000 1! #68590000 0! #68600000 1! #68610000 0! #68620000 1! #68630000 0! #68640000 1! #68650000 0! #68660000 1! #68670000 0! #68680000 1! #68690000 0! #68700000 1! #68710000 0! #68720000 1! #68730000 0! #68740000 1! #68750000 0! #68760000 1! #68770000 0! #68780000 1! #68790000 0! #68800000 1! #68810000 0! #68820000 1! #68830000 0! #68840000 1! #68850000 0! #68860000 1! #68870000 0! #68880000 1! #68890000 0! #68900000 1! #68910000 0! #68920000 1! #68930000 0! #68940000 1! #68950000 0! #68960000 1! #68970000 0! #68980000 1! #68990000 0! #69000000 1! #69010000 0! #69020000 1! #69030000 0! #69040000 1! #69050000 0! #69060000 1! #69070000 0! #69080000 1! #69090000 0! #69100000 1! #69110000 0! #69120000 1! #69130000 0! #69140000 1! #69150000 0! #69160000 1! #69170000 0! #69180000 1! #69190000 0! #69200000 1! #69210000 0! #69220000 1! #69230000 0! #69240000 1! #69250000 0! #69260000 1! #69270000 0! #69280000 1! #69290000 0! #69300000 1! #69310000 0! #69320000 1! #69330000 0! #69340000 1! #69350000 0! #69360000 1! #69370000 0! #69380000 1! #69390000 0! #69400000 1! #69410000 0! #69420000 1! #69430000 0! #69440000 1! #69450000 0! #69460000 1! #69470000 0! #69480000 1! #69490000 0! #69500000 1! #69510000 0! #69520000 1! #69530000 0! #69540000 1! #69550000 0! #69560000 1! #69570000 0! #69580000 1! #69590000 0! #69600000 1! #69610000 0! #69620000 1! #69630000 0! #69640000 1! #69650000 0! #69660000 1! #69670000 0! #69680000 1! #69690000 0! #69700000 1! #69710000 0! #69720000 1! #69730000 0! #69740000 1! #69750000 0! #69760000 1! #69770000 0! #69780000 1! #69790000 0! #69800000 1! #69810000 0! #69820000 1! #69830000 0! #69840000 1! #69850000 0! #69860000 1! #69870000 0! #69880000 1! #69890000 0! #69900000 1! #69910000 0! #69915000 1" #69920000 1! #69930000 0! z$ #69940000 1! #69950000 0! #69955000 0" #69960000 1! #69970000 0! #69975000 1" #69980000 1! #69990000 0! #70000000 1! #70010000 0! #70015000 0" #70020000 1! #70030000 0! #70040000 1! #70050000 0! 1$ #70060000 1! #70070000 0! 0$ #70080000 1! #70090000 0! #70095000 1# #70100000 1! #70110000 0! #70115000 0# #70120000 1! #70130000 0! #70135000 1" #70140000 1! #70150000 0! z$ #70160000 1! #70170000 0! #70175000 0" #70180000 1! #70190000 0! #70200000 1! #70210000 0! #70215000 1" #70220000 1! #70230000 0! #70240000 1! #70250000 0! #70255000 0" #70260000 1! #70270000 0! #70280000 1! #70290000 0! 1$ #70295000 1# #70300000 1! #70310000 0! 0$ #70320000 1! #70330000 0! #70335000 0# #70340000 1! #70350000 0! #70360000 1! #70370000 0! #70375000 1" #70380000 1! #70390000 0! 1$ z$ #70400000 1! #70410000 0! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x) x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 1] 1"! 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1:! 1* 1O 1N 1M 1L 1K 1J 1I 1H 1S 1G 1F 1E 1D 1C 1B 1A 1@ 1R 1[ 1\ 1^ 1T 1_ 1X 1U 1Q 1? 1> 1= 1< 1; 1: 19 18 1P 17 16 15 14 13 12 11 10 1. 1- 1, 1+ 1` 1a 1b 1c 1d 1e 1f 1g 1,! 1h 1i 1j 1k 1l 1m 1n 1o 1-! 11! 1;! 1K! 10! 1J! 1 STIL # # Original File: "exp1.vcd" # # Target File: "exp2.stil " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.vcd"; {#### INPUT VECTOR FILE ####} tabular_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} inputs BPCCE, CFG66, S_CFN_L, MSK_IN, P_GNT_L, P_IDSEL, P_LOCK_L, P_M66EN, S_SERR_L, P_CLK, P_RESET_L, S_CLKIN, TDI, TMS, TCK, TRST_L, P_VIO, S_VIO, MS0, MS1; inputs S_REQ_L[8:0]; outputs P_SERR_L, P_REQ_L, S_RESET_L, TDO, ENUM_L, LOO; outputs S_GNT_L[8:0]; outputs S_CLKOUT[9:0]; bidirects S_M66EN, P_DEVSEL_L, P_FRAME_L, P_IRDY_L, P_PAR, P_PERR_L, P_STOP_L, P_TRDY_L, S_DEVSEL_L, S_FRAME_L, S_IRDY_L, S_LOCK_L, S_PAR, S_PERR_L, S_STOP_L, S_TRDY_L; bidirects GPIO[3:0]; bidirects P_AD[31:0]; bidirects P_CBE[3:0]; bidirects S_AD[31:0]; bidirects S_CBE[3:0]; outputs { #### These are actually bidirect control signals #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'VCD'->'STIL'#### } STATE_TRANS 'x'->'N', 'X'->'N', 'z'->'Z' ; STATE_TRANS outputs '0'->'L', '1'->'H', 'Z'->'T', 'z'->'T'; { #### tell vtran how to determine bidirect signal direction #### } bidirect_control S_M66EN = output when xs_m66en_gmux_out = 0; bidirect_control P_DEVSEL_L = output when xp_devsel_gmux_out = 0; bidirect_control P_FRAME_L = output when xp_frame_gmux_out = 0; bidirect_control P_IRDY_L = output when xp_irdy_gmux_out = 0; bidirect_control P_PAR = output when xp_par_gmux_out = 0; bidirect_control P_PERR_L = output when xp_perr_gmux_out = 0; bidirect_control P_STOP_L = output when xp_stop_gmux_out = 0; bidirect_control P_TRDY_L = output when xp_trdy_gmux_out = 0; bidirect_control S_DEVSEL_L = output when xs_devsel_gmux_out = 0; bidirect_control S_FRAME_L = output when xs_frame_gmux_out = 0; bidirect_control S_IRDY_L = output when xs_irdy_gmux_out = 0; bidirect_control S_LOCK_L = output when xs_lock_gmux_out = 0; bidirect_control S_PAR = output when xs_par_gmux_out = 0; bidirect_control S_PERR_L = output when xs_perr_gmux_out = 0; bidirect_control S_STOP_L = output when xs_stop_gmux_out = 0; bidirect_control S_TRDY_L = output when xs_trdy_gmux_out = 0; bidirect_control GPIO[3] = output when x_gpio_3_gmux_out = 0; bidirect_control GPIO[2] = output when x_gpio_2_gmux_out = 0; bidirect_control GPIO[1] = output when x_gpio_1_gmux_out = 0; bidirect_control GPIO[0] = output when x_gpio_0_gmux_out = 0; bidirect_control P_AD[31] = output when xp_ad31_gmux_out = 0; bidirect_control P_AD[30] = output when xp_ad30_gmux_out = 0; bidirect_control P_AD[29] = output when xp_ad29_gmux_out = 0; bidirect_control P_AD[28] = output when xp_ad28_gmux_out = 0; bidirect_control P_AD[27] = output when xp_ad27_gmux_out = 0; bidirect_control P_AD[26] = output when xp_ad26_gmux_out = 0; bidirect_control P_AD[25] = output when xp_ad25_gmux_out = 0; bidirect_control P_AD[24] = output when xp_ad24_gmux_out = 0; bidirect_control P_AD[23] = output when xp_ad23_gmux_out = 0; bidirect_control P_AD[22] = output when xp_ad22_gmux_out = 0; bidirect_control P_AD[21] = output when xp_ad21_gmux_out = 0; bidirect_control P_AD[20] = output when xp_ad20_gmux_out = 0; bidirect_control P_AD[19] = output when xp_ad19_gmux_out = 0; bidirect_control P_AD[18] = output when xp_ad18_gmux_out = 0; bidirect_control P_AD[17] = output when xp_ad17_gmux_out = 0; bidirect_control P_AD[16] = output when xp_ad16_gmux_out = 0; bidirect_control P_AD[15] = output when xp_ad15_gmux_out = 0; bidirect_control P_AD[14] = output when xp_ad14_gmux_out = 0; bidirect_control P_AD[13] = output when xp_ad13_gmux_out = 0; bidirect_control P_AD[12] = output when xp_ad12_gmux_out = 0; bidirect_control P_AD[11] = output when xp_ad11_gmux_out = 0; bidirect_control P_AD[10] = output when xp_ad10_gmux_out = 0; bidirect_control P_AD[9] = output when xp_ad9_gmux_out = 0; bidirect_control P_AD[8] = output when xp_ad8_gmux_out = 0; bidirect_control P_AD[7] = output when xp_ad7_gmux_out = 0; bidirect_control P_AD[6] = output when xp_ad6_gmux_out = 0; bidirect_control P_AD[5] = output when xp_ad5_gmux_out = 0; bidirect_control P_AD[4] = output when xp_ad4_gmux_out = 0; bidirect_control P_AD[3] = output when xp_ad3_gmux_out = 0; bidirect_control P_AD[2] = output when xp_ad2_gmux_out = 0; bidirect_control P_AD[1] = output when xp_ad1_gmux_out = 0; bidirect_control P_AD[0] = output when xp_ad0_gmux_out = 0; bidirect_control P_CBE[3] = output when xp_cbe3_gmux_out = 0; bidirect_control P_CBE[2] = output when xp_cbe2_gmux_out = 0; bidirect_control P_CBE[1] = output when xp_cbe1_gmux_out = 0; bidirect_control P_CBE[0] = output when xp_cbe0_gmux_out = 0; bidirect_control S_AD[31] = output when xs_ad31_gmux_out = 0; bidirect_control S_AD[30] = output when xs_ad30_gmux_out = 0; bidirect_control S_AD[29] = output when xs_ad29_gmux_out = 0; bidirect_control S_AD[28] = output when xs_ad28_gmux_out = 0; bidirect_control S_AD[27] = output when xs_ad27_gmux_out = 0; bidirect_control S_AD[26] = output when xs_ad26_gmux_out = 0; bidirect_control S_AD[25] = output when xs_ad25_gmux_out = 0; bidirect_control S_AD[24] = output when xs_ad24_gmux_out = 0; bidirect_control S_AD[23] = output when xs_ad23_gmux_out = 0; bidirect_control S_AD[22] = output when xs_ad22_gmux_out = 0; bidirect_control S_AD[21] = output when xs_ad21_gmux_out = 0; bidirect_control S_AD[20] = output when xs_ad20_gmux_out = 0; bidirect_control S_AD[19] = output when xs_ad19_gmux_out = 0; bidirect_control S_AD[18] = output when xs_ad18_gmux_out = 0; bidirect_control S_AD[17] = output when xs_ad17_gmux_out = 0; bidirect_control S_AD[16] = output when xs_ad16_gmux_out = 0; bidirect_control S_AD[15] = output when xs_ad15_gmux_out = 0; bidirect_control S_AD[14] = output when xs_ad14_gmux_out = 0; bidirect_control S_AD[13] = output when xs_ad13_gmux_out = 0; bidirect_control S_AD[12] = output when xs_ad12_gmux_out = 0; bidirect_control S_AD[11] = output when xs_ad11_gmux_out = 0; bidirect_control S_AD[10] = output when xs_ad10_gmux_out = 0; bidirect_control S_AD[9] = output when xs_ad9_gmux_out = 0; bidirect_control S_AD[8] = output when xs_ad8_gmux_out = 0; bidirect_control S_AD[7] = output when xs_ad7_gmux_out = 0; bidirect_control S_AD[6] = output when xs_ad6_gmux_out = 0; bidirect_control S_AD[5] = output when xs_ad5_gmux_out = 0; bidirect_control S_AD[4] = output when xs_ad4_gmux_out = 0; bidirect_control S_AD[3] = output when xs_ad3_gmux_out = 0; bidirect_control S_AD[2] = output when xs_ad2_gmux_out = 0; bidirect_control S_AD[1] = output when xs_ad1_gmux_out = 0; bidirect_control S_AD[0] = output when xs_ad0_gmux_out = 0; bidirect_control S_CBE[3] = output when xs_cbe3_gmux_out = 0; bidirect_control S_CBE[2] = output when xs_cbe2_gmux_out = 0; bidirect_control S_CBE[1] = output when xs_cbe1_gmux_out = 0; bidirect_control S_CBE[0] = output when xs_cbe0_gmux_out = 0; bidirect_control S_CLKOUT[9] = output when 0; {################################################################## The vector data in the VCD file is in a print-on-change format. The vector data for the STIL file needs to be in cycle-based format. Now define some timing for the STIL file, since VCD file does not contain this info separately. ######################################################################} TEMPLATE_CYCLIZATION TERMINATE_ON_DEFAULTS = "-1" MATCH_REPORT = "exp1.rpt", MATCH_TRACE_START = 1, MATCH_TRACE_STOP = 99; TIMESET tpDefault CYCLE = 50; PINTYPE NRZ * @ 0; PINTYPE RZ P_CLK @ 10, 25; PINTYPE RZ S_CLKIN @ 10, 35; PINTYPE STB * @ 48 ; ENDTIMESET; TIMESET tp1 CYCLE = 250; PINTYPE NRZ * @ 2; PINTYPE RZ P_CLK @ 15, 45; PINTYPE RZ S_CLKIN @ 10, 60; PINTYPE STB * @ 98 ; IDENTIFIER (xs_m66en_gmux_out=0); ENDTIMESET; TIMESET tp2 WEIGHT 3; CYCLE = 250; PINTYPE NRZ * @ 0; PINTYPE RZ P_CLK @ 15, 35; PINTYPE RZ S_CLKIN @ 10, 40; PINTYPE STB * @ 98 ; IDENTIFIER (xs_m66en_gmux_out=1); ENDTIMESET; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin TESTER_FORMAT STIL {#### OUTPUT FORMAT ####} -quote_names, INPUT_GROUP = "S_AD", { #### make separate group to reduce file size #### } INPUT_GROUP = "P_AD", { #### make separate group to reduce file size #### } ; DELETE_PINS { #### don't want these controls in STIL file #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; target_file "exp2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/STIL/STILVCD/000075500001440000012000000000001103104161000151775ustar00jcosleystaff00000400000023INTERFACES/STIL/STILVCD/exp1.stil000064400001440000012000004337141103104161000167650ustar00jcosleystaff00000400000023STIL 1.0 { Design P2000.9; } Header { Title " TetraMAX (TM) 2001.08-i010807_230004 STIL output"; Date "Tue Mar 25 11:07:23 2003"; Source " TetraMAX (TM) 2001.08-i010807_230004 STIL output"; History { Ann {* Thu Aug 29 11:07:46 2002 *} Ann {* Uncollapsed Stuck Fault Summary Report *} Ann {* ----------------------------------------------- *} Ann {* fault class code #faults *} Ann {* ------------------------------ ---- --------- *} Ann {* Detected DT 17775 *} Ann {* Possibly detected PT 96 *} Ann {* Undetectable UD 29 *} Ann {* ATPG untestable AU 8180 *} Ann {* Not detected ND 0 *} Ann {* ----------------------------------------------- *} Ann {* total faults 26080 *} Ann {* test coverage 68.42% *} Ann {* ----------------------------------------------- *} Ann {* *} Ann {* Pattern Summary Report *} Ann {* ----------------------------------------------- *} Ann {* #internal patterns 35 *} Ann {* #basic_scan patterns 35 *} Ann {* ----------------------------------------------- *} Ann {* *} Ann {* rule severity #fails description *} Ann {* ---- -------- ------ --------------------------------- *} Ann {* N2 warning 4 unsupported construct *} Ann {* N5 warning 11 redefined module *} Ann {* N20 warning 4 underspecified UDP *} Ann {* B6 warning 35 undriven module inout pin *} Ann {* B7 warning 353 undriven module output pin *} Ann {* B8 warning 1145 unconnected module input pin *} Ann {* B9 warning 2 undriven module internal net *} Ann {* B10 warning 1563 unconnected module internal net *} Ann {* B12 warning 48 undriven instance input pin *} Ann {* B18 warning 3 tristate and non-tristate drivers combined *} Ann {* B22 warning 58 dropped design view *} Ann {* B23 warning 7 feedback path *} Ann {* S19 warning 117 nonscan cell disturb *} Ann {* S29 warning 1 invalid dependent slave operation (mask) *} Ann {* C2 warning 7 unstable nonscan DFF when clocks off *} Ann {* C6 warning 1 TE port captured data affected by new capture (nomask) *} Ann {* C16 warning 71 nonscan cell port unable to capture *} Ann {* V11 warning 1 repeated entry *} Ann {* V14 warning 8 missing state *} Ann {* V16 warning 2 miscounted arguments *} Ann {* V20 warning 2 unsupported event *} Ann {* X1 warning 2 sensitizable feedback path *} Ann {* Z1 warning 14 bus capable of contention *} Ann {* Z2 warning 14 bus capable of holding Z state *} Ann {* Z4 warning 14 bus contention in test procedure *} Ann {* Z5 warning 30 bidi pin not at input mode *} Ann {* *} Ann {* clock_name off usage *} Ann {* ---------------- --- -------------------------- *} Ann {* TCK 0 master shadow shift nonscan_DFF *} Ann {* *} Ann {* port_name constraint_value *} Ann {* ---------------- --------------- *} Ann {* VLRTC0 0 *} Ann {* ITWAKEUP 0 *} Ann {* RPWON 1 *} Ann {* DBBSRST 0 *} Ann {* VDR 1 *} Ann {* PWON 1 *} Ann {* TESTRESET 0 *} Ann {* DBBSCK 0 *} Ann {* TEN 1 *} Ann {* VBAT 1 *} Ann {* BDR 0 *} Ann {* UEN 1 *} Ann {* RPWON2 1 *} Ann {* TDR 0 *} Ann {* UDR 0 *} Ann {* CK13M 0 *} Ann {* AUDR 0 *} Ann {* BFSR 0 *} Ann {* TMS 0 *} Ann {* VLMEM 0 *} Ann {* CK32K 0 *} Ann {* VLRTC 1 *} Ann {* TEST4 Z *} Ann {* INT2 Z *} Ann {* INT1 Z *} Ann {* SIMIO 0 *} Ann {* DBBSIO 0 *} Ann {* TEST3 Z *} Ann {* *} Ann {* There are no equivalent pins *} Ann {* Net Connection TIEX AUXI -remove *} Ann {* Net Connection TIEX BDLIM -remove *} Ann {* Net Connection TIEX BDLIP -remove *} Ann {* Net Connection TIEX BDLQM -remove *} Ann {* Net Connection TIEX BDLQP -remove *} Ann {* Net Connection TIEX GNDA -remove *} Ann {* Net Connection TIEX GNDA2 -remove *} Ann {* Net Connection TIEX GNDD -remove *} Ann {* Net Connection TIEX GNDSPK -remove *} Ann {* Net Connection TIEX GNDSPK2 -remove *} Ann {* Net Connection TIEX HSMICIP -remove *} Ann {* Net Connection TIEX IBIAS -remove *} Ann {* Net Connection TIEX LEDC -remove *} Ann {* Net Connection TIEX MICIN -remove *} Ann {* Net Connection TIEX MICIP -remove *} Ann {* Net Connection TIEX REFGND -remove *} Ann {* Net Connection TIEX VBACK -remove *} Ann {* Net Connection TIEX VBATS -remove *} Ann {* Net Connection TIEX VCABB -remove *} Ann {* Net Connection TIEX VCCS -remove *} Ann {* Net Connection TIEX VCCSPK -remove *} Ann {* Net Connection TIEX VCDBB -remove *} Ann {* Net Connection TIEX VCHG -remove *} Ann {* Net Connection TIEX VCIO -remove *} Ann {* Net Connection TIEX VCMEM -remove *} Ann {* Net Connection TIEX VCRAM -remove *} Ann {* Net Connection TIEX VCUSB -remove *} Ann {* Net Connection TIEX VSDBB -remove *} Ann {* Net Connection PO AFC -remove *} Ann {* Net Connection PO APC -remove *} Ann {* Net Connection PO AUVMID -remove *} Ann {* Net Connection PO AUXO -remove *} Ann {* Net Connection PO BULIM -remove *} Ann {* Net Connection PO BULIP -remove *} Ann {* Net Connection PO BULQM -remove *} Ann {* Net Connection PO BULQP -remove *} Ann {* Net Connection PO DAC -remove *} Ann {* Net Connection PO EARN -remove *} Ann {* Net Connection PO EARP -remove *} Ann {* Net Connection PO HSMICBIAS -remove *} Ann {* Net Connection PO HSOL -remove *} Ann {* Net Connection PO HSOR -remove *} Ann {* Net Connection PO HSOVMID -remove *} Ann {* Net Connection PO ICTL -remove *} Ann {* Net Connection PO MICBIAS -remove *} Ann {* Net Connection PO PCHG -remove *} Ann {* Net Connection PO SPKN -remove *} Ann {* Net Connection PO SPKP -remove *} Ann {* Net Connection PO TESTV -remove *} Ann {* Net Connection PO UPR -remove *} Ann {* Net Connection PO VRABB -remove *} Ann {* Net Connection PO VRDBB -remove *} Ann {* Net Connection PO VREF -remove *} Ann {* Net Connection PO VRIO -remove *} Ann {* Net Connection PO VRMEM -remove *} Ann {* Net Connection PO VRRAM -remove *} Ann {* Net Connection PO VRRTC -remove *} Ann {* Net Connection PO VRSIM -remove *} Ann {* Net Connection PO VRUSB -remove *} Ann {* Net Connection PO BDX -remove *} Ann {* Net Connection PO BFSX -remove *} Ann {* Net Connection TIEZ ADIN1 -remove *} Ann {* Net Connection TIEZ ADIN2 -remove *} Ann {* Net Connection TIEZ ADIN3 -remove *} Ann {* Net Connection TIEZ ADIN4 -remove *} Ann {* Net Connection TIEZ ADIN5 -remove *} } } Signals { "VLRTC0" In; "ITWAKEUP" In; "RPWON" In; "DBBSRST" In; "VDR" In; "TDI" In { ScanIn; } "PWON" In; "TESTRESET" In; "DBBSCK" In; "TEN" In; "TCK" In; "VBAT" In; "BDR" In; "UEN" In; "RPWON2" In; "TDR" In; "UDR" In; "CK13M" In; "AUDR" In; "BFSR" In; "TMS" In; "VLMEM" In; "CK32K" In; "VLRTC" In; "TEST4" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "INT2" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "INT1" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "SIMIO" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "DBBSIO" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "TEST3" InOut { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } "AUPLL" Out; "ONNOFF" Out; "UDX" Out; "SIMCK" Out; "TDO" Out { ScanOut; } "VDX" Out; "AUCK" Out; "VFS" Out; "REGEN" Out; "RESPWRONZ" Out; "SIMRST" Out; "VCK" Out; "AUFS" Out; } SignalGroups { "_pi" = '"VBAT" + "TDI" + "INT2" + "TMS" + "TDR" + "TEN" + "BFSR" + "TEST4" + "UDR" + "RPWON" + "BDR" + "VDR" + "UEN" + "TEST3" + "PWON" + "AUDR" + "RPWON2" + "DBBSRST" + "DBBSCK" + "DBBSIO" + "VLRTC" + "CK32K" + "VLMEM" + "INT1" + "CK13M" + "SIMIO" + "ITWAKEUP" + "TESTRESET" + "TCK" + "VLRTC0"'; // #signals=30 "_default_In_Timing_" = '"VBAT" + "TDI" + "INT2" + "TMS" + "TDR" + "TEN" + "BFSR" + "TEST4" + "UDR" + "RPWON" + "BDR" + "VDR" + "UEN" + "TEST3" + "PWON" + "AUDR" + "RPWON2" + "DBBSRST" + "DBBSCK" + "DBBSIO" + "VLRTC" + "CK32K" + "VLMEM" + "INT1" + "CK13M" + "SIMIO" + "ITWAKEUP" + "TESTRESET" + "TCK" + "VLRTC0"'; // #signals=30 "_io" = '"INT2" + "TEST4" + "TEST3" + "DBBSIO" + "INT1" + "SIMIO"' { WFCMap 0X->0; WFCMap 1X->1; WFCMap ZX->Z; WFCMap NX->N; } // #signals=6 "_default_Out_Timing_" = '"VCK" + "INT2" + "ONNOFF" + "TEST4" + "TDO" + "UDX" + "VDX" + "TEST3" + "VFS" + "AUPLL" + "AUFS" + "AUCK" + "DBBSIO" + "SIMCK" + "SIMRST" + "RESPWRONZ" + "REGEN" + "INT1" + "SIMIO"'; // #signals=19 "_po" = '"VCK" + "INT2" + "ONNOFF" + "TEST4" + "TDO" + "UDX" + "VDX" + "TEST3" + "VFS" + "AUPLL" + "AUFS" + "AUCK" + "DBBSIO" + "SIMCK" + "SIMRST" + "RESPWRONZ" + "REGEN" + "INT1" + "SIMIO"'; // #signals=19 "_default_Clk0_Timing_" = '"TCK"'; // #signals=1 } ScanStructures { ScanChain "Damien" { ScanLength 731; ScanIn "TDI"; ScanOut "TDO"; ScanInversion 1; ScanCells "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P1_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P1_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P2_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P2_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P5_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P5_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P5_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P7_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P7_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.P7_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.Y1_EXTENDED_REG0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.Y1_EXTENDED_REG1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.Y2_EXTENDED_REG0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SI.Y2_EXTENDED_REG1" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.CKDIV2_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.DCOUNT1_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.DCOUNT1_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.DCOUNT1_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.DCOUNT1_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X20" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X21" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X22" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X23" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X24" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X25" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X26" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X27" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X28" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2X29" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X30" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X31" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X32" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X33" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X34" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X35" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X36" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X37" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X38" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3X39" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X40" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X41" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X42" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X43" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X44" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X45" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X46" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X47" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X48" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4X49" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4410" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4411" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4412" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4413" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4414" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4415" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG4416" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X50" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X51" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X52" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X53" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X54" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X55" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X56" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X57" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X58" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5X59" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5510" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5511" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5512" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5513" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5514" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5515" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG5516" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X60" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X61" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X62" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X63" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X64" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X65" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X66" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X67" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X68" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6X69" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6610" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6611" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6612" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6613" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6614" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6615" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG6616" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X70" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X71" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X72" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X73" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X74" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X75" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X76" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X77" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X78" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7X79" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7710" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7711" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7712" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7713" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7714" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7715" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REG7716" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX1X9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SDND_XID_REGX116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SELDIFF_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG220" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG221" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG222" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG223" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG224" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG225" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG226" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG227" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG228" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG229" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG330" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG331" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG332" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG333" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG334" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG335" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG336" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG337" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG338" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG339" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_RE3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID1_REG116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG220" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG221" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG222" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG223" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG224" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG225" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG226" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG227" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG228" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG229" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG330" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG331" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG332" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG333" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG334" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG335" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG336" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG337" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG338" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG339" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_RE3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.SI2D_XID2_REG116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.DIVNENI_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCI.Y_REGX16" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.B_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.E_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.ALUOUTA2D_REGX0" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.A_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUI.C_REGX0" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLACTIVI_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLASTATE_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLASTATE_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLASTATE_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLCALS_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.BDLENAS_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DATAREADYD_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGCNTER_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMCPT_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMCPT_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMCPT_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMCPT_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMCPT_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.RAMRWSCAN_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DATAREADY_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.DREGS_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.LOADS_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDCTRL.FILTERON_REG" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P1_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P1_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P2_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P2_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P5_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P5_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P5_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P7_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P7_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.P7_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.Y1_EXTENDED_REG0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.Y1_EXTENDED_REG1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.Y2_EXTENDED_REG0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDDS2SQ.Y2_EXTENDED_REG1" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.CKDIV2_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.DCOUNT1_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.DCOUNT1_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.DCOUNT1_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.DCOUNT1_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X20" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X21" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X22" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X23" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X24" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X25" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X26" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X27" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X28" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2X29" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X30" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X31" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X32" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X33" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X34" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X35" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X36" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X37" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X38" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3X39" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X40" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X41" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X42" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X43" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X44" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X45" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X46" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X47" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X48" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4X49" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4410" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4411" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4412" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4413" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4414" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4415" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG4416" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X50" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X51" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X52" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X53" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X54" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X55" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X56" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X57" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X58" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5X59" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5510" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5511" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5512" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5513" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5514" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5515" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG5516" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X60" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X61" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X62" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X63" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X64" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X65" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X66" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X67" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X68" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6X69" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6610" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6611" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6612" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6613" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6614" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6615" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG6616" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X70" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X71" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X72" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X73" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X74" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X75" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X76" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X77" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X78" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7X79" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7710" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7711" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7712" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7713" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7714" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7715" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REG7716" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX1X9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SDND_XID_REGX116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SELDIFF_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG220" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG221" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG222" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG223" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG224" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG225" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG226" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG227" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG228" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG229" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG330" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG331" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG332" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG333" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG334" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG335" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG336" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG337" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG338" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG339" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_RE3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID1_REG116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG220" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG221" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG222" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG223" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG224" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG225" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG226" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG227" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG228" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG229" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2210" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2211" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2212" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2213" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2214" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2215" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE2216" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG330" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG331" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG332" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG333" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG334" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG335" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG336" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG337" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG338" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG339" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3310" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3311" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3312" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3313" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3314" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3315" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_RE3316" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG110" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG111" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG112" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG113" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG114" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG115" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.SI2D_XID2_REG116" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.DIVNENI_REG" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDSINCQ.Y_REGX16" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.B_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.E_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.ALUOUTA2D_REGX0" ! "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX1" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.A_REGX0" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX19" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX18" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX17" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX16" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX15" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX14" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX13" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX12" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX11" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX10" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX9" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX8" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX7" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX6" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX5" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX4" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX3" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX2" "bar.XBARCORE.XBBC.XTOP.XBDL.XTOP.XDIG.XBDLDSYN.XBDLDSCAN.XBDLDALUQ.C_REGX1" ! "bar.XBARCORE.XDIG.XTOP.XINT.XTAP.TDO_REG" ; ScanMasterClock TCK ; } } Timing { WaveformTable "_default_WFT_" { Period '100ns'; Waveforms { "_default_In_Timing_" { 0 { '0ns' D; } } "_default_In_Timing_" { 1 { '0ns' U; } } "_default_In_Timing_" { Z { '0ns' Z; } } "_default_In_Timing_" { N { '0ns' N; } } "_default_Clk0_Timing_" { 0 { '0ns' D; } } "_default_Clk0_Timing_" { P { '0ns' D; '45ns' U; '95ns' D; } } "_default_Clk0_Timing_" { 1 { '0ns' U; } } "_default_Out_Timing_" { X { '0ns' X; } } "_default_Out_Timing_" { H { '0ns' X; '40ns' H; } } "_default_Out_Timing_" { L { '0ns' X; '40ns' L; } } "_default_Out_Timing_" { T { '0ns' X; '40ns' T; } } } } } PatternBurst "_burst_" { PatList { "_pattern_" { } }} PatternExec { PatternBurst "_burst_"; } Procedures { "load_unload" { W "_default_WFT_"; C { "CK32K"=0; "DBBSIO"=Z; "INT1"=Z; "INT2"=Z; "SIMIO"=Z; "TEST3"=Z; "TEST4"=Z; "DBBSCK"=0; "DBBSRST"=0; "ITWAKEUP"=0; "PWON"=1; "RPWON"=1; "TESTRESET"=0; "VDR"=1; "TCK"=0; "CK13M"=0; "CK32K"=0; "TMS"=0; } Shift { W "_default_WFT_"; V { "TCK"=P; "TDI"=#; "TDO"=#; "TMS"=0; "TESTRESET"=0; } } W "_default_WFT_"; V { "TMS"=1; "TDI"=#; "TDO"=#; "TCK"=P; "TESTRESET"=0; } V { "TMS"=1; "TCK"=P; } V { "TMS"=1; "TCK"=P; } V { "TMS"=0; "TCK"=P; } } "capture_TCK" { W "_default_WFT_"; F { "VLRTC0"=0; "ITWAKEUP"=0; "RPWON"=1; "DBBSRST"=0; "VDR"=1; "PWON"=1; "TESTRESET"=0; "DBBSCK"=0; "TEN"=1; "VBAT"=1; "BDR"=0; "UEN"=1; "RPWON2"=1; "TDR"=0; "UDR"=0; "CK13M"=0; "AUDR"=0; "BFSR"=0; "TMS"=0; "VLMEM"=0; "CK32K"=0; "VLRTC"=1; "TEST4"=Z; "INT2"=Z; "INT1"=Z; "SIMIO"=0; "DBBSIO"=0; "TEST3"=Z; } V { "_pi"=\r30 # ; "_po"=\r19 # ; "TCK"=P; "TMS"=0; } } "capture" { W "_default_WFT_"; F { "VLRTC0"=0; "ITWAKEUP"=0; "RPWON"=1; "DBBSRST"=0; "VDR"=1; "PWON"=1; "TESTRESET"=0; "DBBSCK"=0; "TEN"=1; "VBAT"=1; "BDR"=0; "UEN"=1; "RPWON2"=1; "TDR"=0; "UDR"=0; "CK13M"=0; "AUDR"=0; "BFSR"=0; "TMS"=0; "VLMEM"=0; "CK32K"=0; "VLRTC"=1; "TEST4"=Z; "INT2"=Z; "INT1"=Z; "SIMIO"=0; "DBBSIO"=0; "TEST3"=Z; } "forcePI": V { "_pi"=\r30 # ; "_po"=\j \r19 X ; } "measurePO": V { "_po"=\r19 # ; } } } MacroDefs { "test_setup" { W "_default_WFT_"; C { "CK32K"=Z; "DBBSIO"=Z; "INT1"=Z; "INT2"=Z; "SIMIO"=Z; "TEST3"=Z; "TEST4"=Z; "VLRTC0"=0; "RPWON2"=1; "AUDR"=0; "VLMEM"=0; "VLRTC"=1; } V { "DBBSCK"=0; "DBBSRST"=0; "ITWAKEUP"=0; "PWON"=1; "RPWON"=1; "TESTRESET"=0; "VDR"=1; "TCK"=0; "CK13M"=0; "CK32K"=0; } V { "BFSR"=0; "BDR"=0; "TEN"=0; "TDR"=0; "UEN"=0; "UDR"=0; "VDR"=0; } V { "TESTRESET"=1; "VBAT"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=1; "VBAT"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "VBAT"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=1; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=0; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=1; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "CK13M"=0; "TEN"=1; "TDR"=0; } V { "CK13M"=1; "TEN"=1; "TDR"=0; } V { "CK13M"=0; "TEN"=1; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=1; } V { "CK13M"=1; "TEN"=0; "TDR"=1; } V { "CK13M"=0; "TEN"=0; "TDR"=1; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=1; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; "TDR"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=0; "TEN"=0; } V { "CK13M"=1; "TEN"=0; } V { "CK13M"=1; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "CK13M"=1; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "CK13M"=1; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "CK13M"=0; "TEN"=1; } V { "TMS"=0; "TCK"=P; } V { "TMS"=1; "TCK"=P; } V { "TMS"=1; "TCK"=P; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=P; "TDI"=0; } V { "TMS"=0; "TCK"=P; "TDI"=0; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=1; "TCK"=P; "TDI"=0; } V { "TMS"=1; "TCK"=P; "TDI"=0; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=1; "UEN"=1; "UDR"=0; } V { "TESTRESET"=0; "CK32K"=0; "CK13M"=0; "UEN"=1; "UDR"=0; } V { "TMS"=0; "TCK"=P; } V { "TMS"=1; "TCK"=P; } V { "TMS"=1; "TCK"=P; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=P; "TDI"=0; } V { "TMS"=0; "TCK"=P; "TDI"=0; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=0; "TCK"=P; "TDI"=1; } V { "TMS"=0; "TCK"=P; "TDI"=0; } V { "TMS"=1; "TCK"=P; "TDI"=1; } V { "TMS"=1; "TCK"=P; "TDI"=1; } V { "TMS"=1; "TCK"=P; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=P; } V { "TMS"=0; "TCK"=0; "VDR"=1; "SIMIO"=0; "DBBSIO"=0; } } } Pattern "_pattern_" { W "_default_WFT_"; "precondition all Signals": C { "_pi"=\r30 0 ; "_po"=\j \r19 X ; } Macro "test_setup"; "pattern 0": Call "load_unload" { "TDI"=\l730 10100101101001111011010111001110110010010001101100110000110000000001000000000110001001101010100101001111111000110100001011011101010111011101010011010110110101101000010110101111001000010101011110100111100000111111010001111010001101001000001100111110010000111111111100111011100010010001100010100110101001111110111110011100000011111111101000001110001000110110110111111111110010011111010111101000111010001011111010011110100000111100000100000011010001101101010100000111000100110001010111011010100101111100101000100010011011110111111111101110111111100010101011101111110110101011101010001011010111000111011000100100001100001001111001010100110000000101111001010000001011111100001001010010100000111111101001110001100110101111010101001110110; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 1": Call "load_unload" { "TDO"=\l730 XHLHHLHLLHLHHLLLLHLLHLHLLLHHLLLHLLHHLHHLHHHLLHLLHHLLHHHHLLHHHHHHHHHLHHHHHHHHHLLHHHLHHLLHLHLHLHHLHLHHLLLLLLLHHHLLHHLHLLHLHLLLLHHLHHHHLHLHLHLLLLHLHHLLLLHHHHHLLLLLLHLHLLLHHHHHLHLHLLHHLLHLHHHLHHLHHHLLLLHHLLLLHHHLLHLLLHLHHLLLLHLHHHLLHLHHLHHHHHLLHHLLLLLHHLHHHHLLLLLLLLLLHHLLLHLLLHHHLHHLHHHLLHHHLHLHHLLHLHLHHLLLLLLHLLLLLHHLLLHHHHHHLLLLLLLLLHLHHHLLLXLXLLHLLLHLLHHHHHLHHHHHHHHHHHHHHHHHLLLLHLHLLLLHLHHHLLLHLHHHLHLLLLLHLHHLLLLHLHHHHHLLLLHHHHHLHHHHHHLLHLHHHLLHLLHLHLHLHHHHHLLLHHHLHHLLHHHLHLHHLLLHHLLLHLLLHHHLHLHLHLLLHLLLLLLHLLHLHLHLLLHLHLHHHLHLLHLHLLLHHHLHLLLLLHHLHLHHHHHHHLHHLHHLLHLHLLLHLHHHLHHLHHLLLLHHLHHHLHHLLHLLLLHLLLLHLHHLLHHHHHHHLHLLLLHHLHLHHHHHHLHLLLLLLHHHHLHHLHLHHLHLHHHHHLLLLLLLHLHHLLLHHHLLHHLLHLHLLLHLLHHHLHHLHHHHLLLHLHXHXLHHHLLLHLH; "TDI"=\l730 00011001110001000100101000011111110100101111101011001010011000010111001000110001001011000110110110011101010101001100101011000110101111100010101111110010001010010001010000011000010111111010001100111101011011010101011100110001011100010100100000111100101110111010010111000001110000111110011001010110000000011101111000001100010110010111110010111101111111000101101110111000111000100001111100000001111111000111010110100110010101001111000010000101100100010110011010111100011001000110011100110011011100100110010111100100111000100100011110001010100010110000110011100110111011010001101111000100000000111111000100101000110010110101111101000010000110100100011010100010111101111100110110101101100111000110010000111010011010111010010111110100100; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 2": Call "load_unload" { "TDO"=\l730 XHHLLHHLLLHHHLHHHLHHLHLHHHHLLLLLLLHLHHLHLLLLLHLHLLHHLHLHHLLHHHHLHLLLHHLHHHLLHHHLHHLHLLHHHLLHLLHLLHLHHHHHLLLLLHHHHHLHHHHHLLHHHHLHLLLLLLHLHHHLLHHLLLLHLHLLHLLHLHLHLHLLLHHLHLHLLHHLHHLHLLHHHLHHLLLLLLHHHHLLLHLLHHLHHLLLLHHHLLLLLHHHLHLHLLLLLLLLHLLLHLHHLHLLLHHHHHLLLHHHHLLLLLHHLLHHLHLHLLHHHHHHHHLLLHLLLLHHHHHLLHHHLHLLHHLHLLLLLHHHLLHHHLHLLLHHHLHHLLHHLXLXHLHHLHHLHLHHHLLLLLHHLHHLHHHHHHHHLHHLLLLLHHHHHHHLLLLLLLHHHLLLHLHLLHLHHLLHHLHLHLHHLLLLHHHHLHHHHLHLLHHLHHHLHLLHHLLHLHLLLLHHHLLHHLHHHLLHHLLLHHLLHHLLHLHLLHHHHLLHHLLLHHLLHLLLHLLHLHHHLLHLLLLHHHLHHHHHHHHLLLLHHLHHLLHHLLHHLHLHHLLLLLLHLLLHLLHHLHLLHLHLHLHLHLHLLLLLHHHLHHLHLHHHLLHHLHLLHLHLLLLLHLHHHHLHHHHLLHLHHLHHHLLHLHLHHHLHLLLLHLLLLLHHLLHLLHLHLLHLLHHLLLHHHLLHHLHHHHLLLHLHHLLHLHLLLHHLLHXHXHHLHLLHHLL; "TDI"=\l730 11110100100011110000101110101101111111011101101001010010010101111101101011000111011110001000001000000101010010101011101111100001010111001000010010111101010000001010010110011010010111011000001100000110110000100100010001110111110010000010110110101010110110010010001110100110010111101110100010110101101010000011001000011101100101100011001010100010101110111110111000001010010111001011011010000110111010100110000101000011001100110110000001010101000011100000001100011111010000011111011000110001100011110001111110100100101001101110110011101110010111010001101011101100010001111001101111011110110101011000100110110110110010000100010000011001010100111001000101000000011010111011010011011011010111000011011001110111110110101111010110111010000; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 3": Call "load_unload" { "TDO"=\l730 XLLLHLHHLHHHLLLLHHHHLHLLLHLHLLHLLLLLLLHLLLHLLHLHHLHLHHLHHLHLHLLLLLHLLHLHLLHHHLLLHLLLLHHHLHHHHHLHHHHHHLHLHLHHLHLHLHLHLLHHLLHLHHLHLLLHLLHHHHHLLHHHHHLLHLLHHHHLHHLHHHLHLLHLHHHLHLLHLHHHHHHLHHHLHHLLLHHLLHHLLHHHHLLLHHHLLLLHHLLLHLLLLLHHLHHHHHLHLLHLLHLHLHLHLLHLLHHLHHLHHHLLLHLHHLLHHLHLLLLHLLLHLHHHLHLLHLHLLHLHLHHHHHLLHHLHHHHLLLHLLHHLHLLHHHLLHHLHLLHLLXLXHLHHHLLLLHHHHHLHHHHLHHHHHHHHHHHHLHLLHLLHLHHHHLLHLLLHLHLHHLLHHHHLHLHHHHLLHHLLHHLLHLLHHHHHHLHLHLHLHHHHLLLHHHHHHHLLHHHLLLLLHLHHHHHLLLLLHLLHHHLLHHHLLHLHLHHHLLHLHLLLHLLHHHLHHHLLLLHHLLHLLLLHLLLLHLLHLHLHLHHLLLLHHHLLLLHLLHLLLLHLHHHHHLLLHLHLHLLLLLHHLHLHHHHLLHHHLHHLLHLLHLLHLLHHLHHHHLHHHLHHHHHLLHHLHLHLHHLLLHHLHHHLHLHHHHHHHLLHLHLLLHLLHLHHLLHLLHLLHLHLLLHHHHLLHLLHHLLLHLLLLLHLLHLHLLLHLHXHXLLLLHHHHLL; "TDI"=\l730 11010001111000111101110111000100001110101010000101111100111101001100001000010110110100011000010000110110010011011111111010101100000001110001111101110001111100101001011001000101100001000100010111100010111000000000001001001001001000111011110100000100011110011011111101001001011000000111100000000101010011101100001010100001111010011101010111110010001000101000000011011011011100101110110001000010010010101011000110111011001001101001011110111100100000000100011000101010001100010110110100111000010100110111110101110110000101111101010110111000110001000101100010001101000011100100000010010101001010010111011100100010000000000110010001000010100111001110001110010000000110110010001110000011111101011001110110001101101001110110001010011000100; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 4": Call "load_unload" { "TDO"=\l730 XLHLHHHLLLLHHHLLLLHLLLHLLLHHHLHHHHLLLHLHLHLHHHHLHLLLLLHHLLLLHLHHLLHHHHLHHHHLHLLHLLHLHHHLLHHHHLHHHHLLHLLHHLHHLLHLLHLLHHLHHHLHLLHHHHLHHHLHHHLHLLLLHHHLHLLLHHHHHHHHHHHLLLLLLLHLHLHLLHHHLLHLHLLHHHHHLHHLHHHLHHHLLLLHHLHLHLHHHLHHLHHLHHLHHHLLLHLLLLHLHHHHHLHHHLLLLHHLLHLLLLLLHLHHLHHLHLLHHHHHHLLLLHHHHHHHHLHLHLHHLLLHLLHHHHLHLHLHHHHLLLLHLHHLLLHLHLHHHHHHLXLXHHLHLHLHLHHHHLLHLLLHLHLLHLHHHHHHLLLHLLHHHLHHHHLHHLHHLHLHLHLLHHHLLHLLLHLLHHLHHLLHLHHLHLLLLHLLLLHHLHHHHHHHHLHHHLLHHHLHLHLHHHLLHHHLLLLLHLLHHLHLLHHLHLLHHHLHLLHHHLHHHLLHLHHHHLLLHHLHHHHHHLHHLHLHLHHLHLHHLHLHHLLHLLLLLHHHLHHHHHLLHHHLHHLHLLHLHLHHLLHHHLHHHHLHLLLLHLLLHHLHHHLHHHHHHHHHHLLHHLHHHLHHHHLHLHHLLLHHLLLHHHLLLHHLHHHHHHHLLHLLHHLHHHLLLHHHHHLLLLLLHLHLLHHLLLHLLHHHLLHLLHLHHLLLHLHLLHXHXLHLHHLHHHL; "TDI"=\l730 01011001010001000101111011101001110100100100001001011101101001111111011000000110010100000111111001110001101101000000110000111100000110011101001101000100000011110010101000000111100100000111110010001101001101000111001100000111100100010001011011001111110111000100001110111100010100100110101011011000001111110000011101000000100100111110000001011101000100011101011001110100111110101001110111111011001111001001011110101011100111001000001011000101010000110100100000011110110011001110001010100000010010110110101111000010010101110100100011111101011100111101111101110111110110101101110101100001101101001101111101101110000011111001010000000011100011101001111100110011100110100110001110100100101100110101100010001011000010100000110110111111111; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 5": Call "load_unload" { "TDO"=\l730 XLHLLHHLHLHHHLHHHLHLLLLHLLLHLHHLLLHLHHLHHLHHHHLHHLHLLLHLLHLHHLLLLLLLHLLHHHHHHLLHHLHLHHHHHLLLLLLLHLHLLHHLLLLLHHHLLLHLHHHHHHLLLLHHLHHHHHLLLLLHHLHHHLLHLHHLLHLHHHLLLHHLHHHLLHHHHLLLHLHLLLHHHHLLLLLHHHLLHHHLLHLLHLLHHLHLHLLHHHHHHLLLLHHLHHHLHHHLHLLHLLHHLLLLLLHLLLHHHLHHHHLLLHLLLLHHHLHLHHLHHLLHLHLHLLHLLHHHHHLLLLLLHHHHHLLLHLHHHHHHLHHLHHLLLLLHHHHHHLLHLXLXLHHHHLLLHLHHHLLHLHHHHLHHLLHHHHHHLHHLLLHLLLLLLHLLHHLLLLHHLHHLHLLLLHLHLHLLLHHLLLHHLHHHHHLHLLHHHLHLHLHHHHLLHLHHLHHHHHHLLLLHLLHHLLHHLLLHHHLHLHLHHHHHHLHLLLLHLLLLLHLLLHLLLLLHLLHLHLLHLLLHLHLLHHHHLLHLLHLHHLHLHLHHLLHHLLLLHHHHHHLHHLHLLLHHHLLLHLLLLHLLHHHHLLHLLLHLLLLLHLLHLLLHHHHHLLLLLHHLHLHHHHHHHHLLLHHHLLLHLHHLLLLLHHLLHHLLLHHLLHLHHLLHHHLLLHLHHLHHLHLLHHLLHLHLLHHHLHHHLHLLHHHHLHLHLLLLHHXHXHLHHHLLLLL; "TDI"=\l730 01100101101100000010010111100101110111010000000010010000110001110000100010000100011001010000100111010111011011010111000011010000111100110010100000100000000101001101101001111101001111111010110111110010111110110010110110000101010000110010010100100011011110001010101110000000111100111101101101101010111010110010101011100111111011110111000011110111100111000101010111011010001110101001000110111111111001100111011000011101100001010011010010111100000000110010000000010100010101011001001011100111000111010000111110001010101100101100010100010111100010000100111001010011011100011010100111100000111111010101001111111111111000110110110010010111101110100010011010101101001111001101111010100001111011110011000001100010111100000010101100011101111; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 6": Call "load_unload" { "TDO"=\l730 XLLHHLHLLHLLHHHHHHLHHLHLLLLHHLHLLLHLLLHLHHHHHHHHLHHLHHHHLLHHHLLLHHHHLHHHLHHHHLHHHLLHHLHLHHHHLHHHLHLLLHLHLLLLLLHHLLHLHHLLLLLHLHHLLLLLLLHLHLLHLLLLLHHLHLLLLLHLLHHLHLLHLLLHHHHLLHLHHLLHHLLHHLLHLHLHHHLLLHLHLLLLLLHLLLHHHLLHLLHHLLHHLHLHHHHHLLLLHHHLHLHLHLLLHHHHHHHLLLLHHLLLLHLLHLLHLLHLHLHLLLHLHLLHHLHLHLHLLLHHLLLLLLHLLLLHLLLHHHLHHHHLHLHLHHHHLLHLHHHHLXLXLLHLLHHLLLHHHLLLLLLHLHLHHHHHHHHHLHHLHHHLLHLLLLLLLLLHHLLHHLLLHLLHHHHLLLHLLHHHHLHLHHLLHLHHLHLLLLHHHHHHHHLLHHLHHHHHHHHLHLHHHLHLHLHLHHHHLLHLHHLHHLLHLHHHHHLHHLLLHHLHLHHLLHLLLHHHLLHLHLHHLLLLHHHHHLLLLLLHLHLLLLLLHHHHHLHHHLHHLLHHLHHHHHHHHHLLLHHHLHLLHLLHLLLHLHLHLHLHLLHHLHLLHHLHLLLLHLLLHLHHHLHHLLHLHLHLLHLHHLLLLHHLLHLLLLHLHLHHHHLLLLHLLLLHHLLHHHHHLLHHHLHLLLLHHHHLHLHHLLLLLLLLLLLLHHHLHHXHXHHLLLLLLLH; "TDI"=\l730 10010011111001000011100101000111011001011101101010000101100001101000001110010100110011101100011110011011010111110110100100100011110100011100101111100011010010111110000111110100010101100001111101111010000001110011100011101110100001011101011101010011011011100101111111000110110111111000010010101001111011011101100110000000101011110000000010111100001111011100110000010110011110101010011100101001111011001011000110110011110000100110011011100010001101100010010001100010110110111010101110011100101111010001100111101000011010101101111010100100000100011001101010000010100110100001001100011110100110110010110100001000000001010000110101111101011111111110010011100101100000011111011111100010010011110111111110000111001001010101101011010010010; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 7": Call "load_unload" { "TDO"=\l730 XHHLHHLLLLLHHLHHHHLLLHHLHLHHHLLLHLLHHLHLLLHLLHLHLHHHHLHLLHHHHLLHLHHHHHLLLHHLHLHHLLHHLLLHLLHHHLLLLHHLLHLLHLHLLLLLHHHHLLLLLHLHHHLHLHLLHHHHLLLLLHLLLLHLHHHHHHLLLHHLLLHHLLHLHHLHHLHHLHHLHHLLHHHHLLHHHLLLHLLHHLLLHHHHLHLLHLHHHHLLLLLLLLHLLLLLHLHLLLHHLHLLLLLLLHHHLLHLLHLLLLLLHHHHLHHLHLHLHHLLLLHLLHLLLHLLHHLLHHHHHHHLHLHLLLLHHHHHHHLLLHLLLHLHHHHLHLLHLLHHLXLXHHLHHLLLHHHHHLLHHHLHHLLHLHHHHHHHLHLHHLLLHHLHLHHLLLLHLLHHLHLLHHHLLHLLHHLLLLHHHHLHHLLHHLLHLLLHHHLHHHLLHLLHHHLHHLHHHLLHHHLHLLHLLHLLHHLHHHLHLLLHLLHLHHHHLLHHLLHLHLHHHHHLHLHHLLHLHHHHLHHLLHHHLLLLHLHHLLHLLHHLHHLLLLHLLLHHHHLLLHLHHLLLHLLHLLLLLHLLLLHLHLHLHHLHHHLHHHHLLHLHLHLLHLLLLHLHLLLLLLLLLLHHLHHLLLHHLHLLHHHHHHLLLLLHLLLLLLHHHLHHLHHLLLLHLLLLLLLLHHHHLLLHHLHHLHLHLHLLHLHHHHLHHHHHHLHHHHXHXHHLHLHLHHL; "TDI"=\l730 10100001111000100000001001110001011100110101001011100110010000011001100010001101100110101101100001000101101000100000101101110100011011110010001000111010110100011000101110101111011111011111011000000011011010011010010001101100100010110110100011111011001110100100100000001110100000011110001000111100000110100010000000111000111010000111011000100110001111000001001001011111100101101101101111101000101100110111001001110101011110010000001010011011110000010011011100000011100010010001010011110000010100101111001110000000110110101001110011100110011001011010100001100111110001000011100011100110100111110000001111000100001010010010010001000010101110100111001111010110110010100010010110100100001101110001101011111010001110111010110110101001000; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 8": Call "load_unload" { "TDO"=\l730 XHLHHHHLLLLHHHLHHHHHHHLHHLLLHHHLHLLLHHLLHLHLHHLHLLLHHLLHHLHHHHHLLHHLLHHHLHHHLLHLLHHLLHLHLLHLLHHHHLHHHLHLLHLHHHLHHLHLLLHLHLLLLHLLLLLHLLLLLHLLHHHHHHHLLHLLHLHHLLHLHHLHLLHLHHHLLLLHHHHHHHLLLLHLLHLHHLHHHLLLLHLLHLHLLLHLHHLHHLLHLLHHLHHHLHLLHLLHLHHHLLLLLHLLHHLLLHLHHLHHLHHHHHHHLLLHLHHHHHHLLLLHHHLHHHLLLLHHHHHLLHLHHHLHHHHHHHLLLHHHLLLHLHHHHLLLHLLHHLHLLXLXLLHLLHHHLHHHHHLHHLLHHHHHHHLHHLHHLLHLLHLLLLLHLHHHLHLLHHLLHLLLHHLHHLLLHLHLHLLLLHHLHHHHHHLHLHHLLHLLLLHHHHHLHHLLHLLLHHHHHHLLLHHHLHHLHHLLHHHLHLLLLHLLHLLHLLHLHLHHHHLLHHLLLLLHHHLHHHHLLLHHHLLLHHLLHLHHLLLLLHHHHHHHHLLHLLHLLHLLLLHLLLLLLHHHLLHHHHLLHLHHHLLHLHHLLHHHHHLLHLLHLHLHHLHHHLHLHLLLHLHHLLLHHLLLLHLHLLHLLHHLHLHHHLHHLHLLHLHHLHHHHLLHLLLHHHLLHLHLLLLLHLHHHLLLHLLHHHHHLLLLHHHLHHHHLHHLHHXHXLLHHLHHHLL; "TDI"=\l730 01010011100011101100010001011111100110100101000001000011011101001010011100100000101001111101100001000111111001110110001000011101111010111101110010010010111111001101100010111100001111111101110101111110101110010101110101101111111000110100101100000001100001111101111111101101011000110011100011000011011001000100001011110111000011100010001011000010111110110111011110100010010001011111111111110001100001000000000110011101010110010100011111101101011010111001111110011100011011000101101100011110101010011111010001001110110111100111011000000110110011000010111011111011000010101000011000010111001110110011011111111000000110010000100111111111010010001001111000111100000101011001101011101110011001001001111111110000001001110100111011110110011; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 9": Call "load_unload" { "TDO"=\l730 XLHLHHLLLHHHLLLHLLHHHLHHHLHLLLLLLHHLLHLHHLHLHHHHHLHHHHLLHLLLHLHHLHLHHLLLHHLHHHHHLHLHHLLLLLHLLHHLLLHLLHHLLLLHHHHHHLHHHLHLLLLHHHHLLLLLLLLHLLLHLHLLLLLLHLHLLLHHLHLHLLLHHLHHLLLLLLLLLLLLHLHLHLHLLHHLHHHHLLHLHLLLHHHHLHHHLHHHHLLHLLLLLLLHHHLLHLHHLHLLHHHHHHHLLHHHHLLLLLHLLLLLLLLHLLHLHLLHHHLLHHLLLHHHLLHHHHLLHLLHHLHHHLHHHHLHLLLLHLLLHHHHLLLHHHLHHHLHLLLLLXLXHLHHHLHLLHHHHHLLLHLLHHHHHHHHHHHHLLLLLLLLLLLLHHHLLHHHHLHHHHHHHHHLLHHLLLHLHLHLLHHLHLHHHLLLLLLHLLHLHLLHLHLLLHHLLLLLLHHLLLHHHLLHLLHHHLHHHLHLLLLHHLHHHHLHHHHLHLLLHLLLLLHLLHHHHLHLHLHHHHLLHHHHLHLLLHHLLLHLLHHLHLLHLLHLLHHHHLHHLLLHHLLHHLHLHLLHHHHLHHHHHLLLLLHHLHLLHLLLLLLLLHHHHHHLLHHLHHHHLHHLLLLLLLLLHLHHLHHHLHHLLLLHHHLLLLHHHHHLHLHLLHHLLHLHLLLHLLLHHLLHHLHHLHHLLLLLLLLLHHHHHHLHHLLLHHLLHHXHXHLLLLHLLHL; "TDI"=\l730 00100011000100001011000000110010010100110001111010111001111001011011101000010011110101001100011110101101011000000010000011110100000110111000100000011010111110000000100001100111000011100101011101011000001001100110111000001000001110100101011001100011011010001110101011110000111110011011011111001101001010101011110100010101001101010100111110100001000001010011110100011101111100000000011010011001110000101000000011111010110111000001110110110010110100101010110010011010011111111001011001000100111110111111100011010010101000100111010001000110111011100010101001011001111111111011111001100111010001100001101011110111111010000011110000101100100111010001011100011010000110100101110111010111011011001110111000001111111011011011001000111001101; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 10": Call "load_unload" { "TDO"=\l730 XHLHHHLLHHHLHHHHLHLLHHHHHHLLHHLHHLHLHHLLHHHLLLLHLHLLLHHLLLLHHLHLLHLLLHLHHHHLHHLLLLHLHLHHLLHHHLLLLHLHLLHLHLLHHHHHHLHHHHLLHHLLLHHHHLLLHHLHLHLLLHLHLLHHHHHLHHLLHHLLHLLLLLHHLHHHHLHLLHHHLHHLLLHHLHHHHLHLLHHHHLLHHLLHLHLHHHHHHLHLLHLLHLLLHHLLLLHLHHHLLLHLHLHLLLLHHHHLLLLLHHLLHLLHLLLLLHHLLHLHHLHLHLHLHLLLLHLHHHLHLHLHHLLHLHLHLHHLLLHHHHLHHHHHLLLHLHHLLLHLLXLXHHLHLLHHHLHHHLLLHHLHHHHHHHHHHHHHHHHHHLLHLHHLLHHLLLHHHHLHLHHHHHHHLLLLLHLHLLHLLLHHHHHLLLHLLHLLHHLHLLHLHHLHLHLHLLHHLHHLLHLHHLLLLLLLLHHHLHLHHLLLLLLLHLLLHHHLHLHLHHLHLLHHLLLLLLLLLLHLLLLLHHLLHHLLLHLHHHLLHLLLHLLLLLLLHHHHHLLLHLLHHLLHHHHHLHLHLLLLHHHHHHLHHLHHLLHHLHLHLHHHLHHLLLHLLHHLHHLLLHLHHHLHLLLHHHLLHLHHHHLLHLHHLHLLLHLLLHLHLLLHLLHLLHHLLLHLLLHHHHHLLLLLLLHLLHLHHLLHLHLLLLHLLLLLLHLHLHXHXHLLLLLHLHH; "TDI"=\l730 11100111110100001111000111010011001001110111111010110100011111100010000111110011000010101111101011000100100001101100001110101010010010110000010000010011111000000100101110000001011010111101100000000100000100100101010000110100101001101101011001011110011000011110001111110001100110110000011011100011010101101111011010010110010010111111110010110110100100101001011100011100011011011100110010010101111110101111101001011100010011011010110010001010000000111010111000100011101001000010100110100000010011110100101000010011011110111100000001101100010101010111010111100101000101110001010011100101101000000000000111010100101011000101110010111100111001101001011010100001111110101000011010110011010011101000100111010011011010110101010101011000100; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 11": Call "load_unload" { "TDO"=\l730 XLLHHLLLLLHLHHHHLLLLHHHLLLHLHHLLHHLHHLLLHLLLLLLHLHLLHLHHHLLLLLLHHHLHHHHLLLLLHHLLHHHHLHLHLLLLLHLHLLHHHLHHLHHHHLLHLLHLLLHHHHHHLHLLHLHLLLLHLLHHHHHHHHLHHHHHLHHLHHLHLHLHLHHHHLLLHLHLLHHHHLLHHLHLLHHHLHHLHHLHLHHHLLLHHLHLLLHHLHHHHLLLLLLHLHLHHLHHHHLLLLHHHLLLLLLHHHLLHHLLHLLHHHHHLLHLLLHHHLLHLHLHLLHLLLLHLLHLHHLHLLHHLHHLHLLLLLLLLHHHLLHLHHLHLHHLLHLHLLHHLXLXLLLLHHLHLHHHHLLLHHLHHHHHHHHHHHHHLLHHLLHHLHHLHLHLLLLLLHLHLLLLLHLHHLHLLLHHHLHHLLHLLHLHLLHHLHHHLHLHHHHHHHLLLHLHLLLHHHLHHHLLLHLHHLHHHHLHLHHLHHHLLHLLHHLHLHLLLHLHLLLLHHLHLHHHLHLLLHHHLHLHHLLLHHLHLLHLHHHHHHHLLLLHLHHLHLHHLLLHLHHHLHLHLHHHLLLHLLLLHHLLHHLHLHLLHLHHLLHLLLLHLLLLHHLLLHHLLLHHLLHLHHLHLLHLHLHHHHLLLLLLHLHLHHHHLLHLHLLHHLLHLHHLLLHLHHHLHHLLLHLHHLLHLLHLHLLHHHHHHLLLHLHLHHLHHLHHLHXHXLLLHLLHHLH; "TDI"=\l730 11100100010001101011011101010001111000000100111011001010110001100111010100110010101011111001000011111110111001100011011011101101100111001001100111001110110111010011010101010110011111100110001111001100011010101100011101001010110101001100111010101110001101111101010100101011011110100010011110100111010001000101001101101011100101110101010011000110100110001010000111011101010000111000111010001111011010010110111000011110011001111010101010110011101101011001001111001110100011011110100111111010101100101010110101010100100111111000011011101110000101011101101111111011010011100000110011001011110000000101001011110110001101000011100101010101100100110110111111010101110110100100000101101011100001010110100010001100001001000001101101100101110; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 12": Call "load_unload" { "TDO"=\l730 XLLHHLHHHLHHHLLHLHLLHLLLHLHLHHHLLLLHHHHHHLHHLLLHLLHHLHLHLLHHHLLHHLLLHLHLHHLLHHLHLHLHLLLLLHHLHHHLLHLHLLHLHLLLLHHHLHLHLHLHLHLLHHLLLLLLHHLLHHHLLLLHHLLHHHLLHLHLHLLHHHLLLLHHHHLLHLHHHHLHLHHLLLLLHLLLHHHHHLLLLHHLHHLLHHHLHHLHHLLLHHLHHLLHHLLLHLLHLLLLLHLHLHLHHLHLHLLHLLLLHLHHHLHHLLLLHLHHLLLHLHHHLHHHLHLHHLLHLLHLHLLLHHLHLLLHLHLHLHHLHHLHLHLLHLHLHHLHLLLLLXLXLLLLLHLHLHHHHHLLLLLHHHHHHHHHHHHHLHHHLLLHLHHHLLLLHLLHLHHLHLLHLLLHHHHLLLLHHLLHHLLLLHLHLHLHLHLLHHLLLHLLHLHLLHHLHHLLLLHHLLLHLHHHLLHLLLLHLHLHLHHHHHLLHLLHLLLHLLHLLLLLLLHLLHLHHLLLHHHHHLLHHLLHHLHLLLLHHHHHHLHHHHLLHHHLLHLHHLHLLLLHHHHLLLLLLLLHHLLLHHLLHHLHLLHLLLHLHHLHLLLLHLLHHHLLHLHHHHLLLHHLHLHLHLHLLHHLHHLLHLLHLLLLLLHLHLHLLLHLLHLHHLHHHHHLHLLHLHLLLHHHHLHLHLLHLHHHLHHHLLHHHHLHHLHHHHHHHHXHXLHLLLLLHLH; "TDI"=\l730 01010111110011111011100101111101010101010000101010000100100000110001001011000110010000010010100000111011100010011101010000100100111100011101100010001101011100011101011011010111010110101001100000010010101100001000010010101011111100000110100101000011010001111000101010000101101100111101010010110100001000001001001101010011001111000001010011111000111011111010010100101010010100001100000111000100100001100101101000010101100000011000011111100111111011011001110011101001100111100010011110101111000100000001100001110000100100110101110111100010010000011001110101101010111001111000010011111110101001100001101001111110101011100100011011111100111001101001101000011010010011001001010001011000001101100011101001110011011110100111111001011111101; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 13": Call "load_unload" { "TDO"=\l730 XLHLHLLLLLHHLLLLLHLLLHHLHLLLLLHLHLHLHLHLHHHHLHLHLHHHHLHHLHHHHHLLHHHLHHLHLLHHHLLHHLHHHHHLHHLHLHHHHHLLLHLLLHHHLHHLLHLLHLLHLHLLLHLHLLHLHLHHLLHHHHHHLHHLHLHLLHHHHLHHHHLHLHLHLHHHHLHHLHLLHHHLLHHLHLLLLHHHHLHHHLHLLLLHLHLLLLLHLHLHLHLLLLLLHHHHHLLHLHHLHLHHHHLLHLHHHLLLLHHHLHLHLHHHHLHLLHLLHHLLLLHLHLHHLHLLHLHHHHLHHHHHLHHLHHLLHLHLHHLLHHLLLLHHHHHLHLHLHHHHLXLXHHLLHLLHHHHHHHLLHHLLHHHHHHHHHHHHHLHHHHHLLLHHHLHHLHHHHLLHHLHLLHLHHHHLHLHLLHHHHHHLLHHHHLLLLLLHHLLLLLLHLLHLLHHLLLHHLLLHLHHLLHHLLLLHHHLLLLHLLLLLHHHHLHHHLLHHLLLHLHLLHLHLHLLLHHLLLLHHHHLHHLLLLLLLHLHLHHLLHHLLLHLHHHHHHLLLLHHHLLLLLHHLLLLLHHHHHHLLLLHLHHHHLLHHLLHHHHLHHLHHLLHLHLLLLHHLLLHHLLHLHHLLHLHHHHLLHLHHLHHLLHHLHHLHLHHHLHLLHHHHHLLHLLHHHLLLHLHHLLLHHLLHLLLLHLHHHLLHLHHLLLLLLHLHHLLHHHXHXLHHHLLHLHH; "TDI"=\l730 00100100111010010100101010011100000000000001001101001000101000110110001111100010000010111110100110011111011100011010010010010101101100100001110111010101101101100000110001100110001101000100110001000111011111001001101001101010000001001011000000001010001000011010110011010100100000010100011000101000010101110111001101100111001111001000101110111100001010100000110110111100100111100110010110100111110010101100100101010010110101011100100011011101110010100100000111011000000000001000101011001110000010101000011111110100010101000100001011100010111111000011011001001101101000001100111000010111011011010101100110110110001010001101010101100110110111101000001000100111001011100000101010110001111101010100010000100010001101010101000010110100100; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 14": Call "load_unload" { "TDO"=\l730 XHLHHLHHLLLHLHHLHLHHLHLHLHHLLLHHHHHHHHHHHHHLHHLLHLHHLHHHLHLHHHLLHLLHHHLLLLLHHHLHHHHHLHLLLLLHLHHLLHHLLLLLHLLLHHHLLLLHHHLLHHLLHHHLLHLHHHLHHLLHHHLHHHLLLHLLLLLHHLHHLLHLHLHHLHHLHHLHHLLLLHLLLHLLHHHLHHLLLHLHHHLLHHLLHLHLLHLHHHHHLHHLLLLLHHHHLLHHHHLLHLHLLHHLLHLHLHHLHHHHHHLHLHHHLLHHHLHLHHHHLHLHLLLHLLLHHLLHLLHHLLLHHLLLLHHLHHHLHLHLLHLHLHHHHHHLHHLLLLHHLXLXLHLHHHHHHHHHHHLLLLHHHHHHHHHHHLLHLLLHHLHLLHLHHLLLLLHHLHLHLLHHLHHLHLHLHHLHLLHLHLHLLLHHLHHHLLHLLLHLLLHHLHLHHLHHHHHLLLHLLHHHHHHHHHHHHHHHLHHHHHHHLHLLHHLHHHHLLHLLHHLHHLLHLLHLHHHHHLLHHLLLHHHHLHLLLHLLHLLHLHHLHLHLHHHHLLHHLHLLHLHHHHLLHLHHLHHHHLLLHHLLLLHHLLHLHLHLHHHLHLHLHHHLHHHHLLHLLHLLLLHLHHHHHLHHHLHHLLLHHLHLLLHHHHHLHLHLHLLHHHLLLLLHLHLHLHHHLHHHHLHHHLHHHLLHLHLLHLLHHLLHLLHLLHHHHLHHLHXHXLHLLLLHHHL; "TDI"=\l730 10101110011101111110000100110111011111100000101111000101000111101110101001001001111010110000101001000111100101100111110001011011101100110111011100001100001011011100111001111011000111100011111010111101001100100011010011101100001011010010110111111011010111001010001101100110010100101010101001111011110000111111101101010111100110100001101001111101101100101110011111000001011101010011101101101010000010101001000111110011010010111111010010010100110000111111001011111000101110111001011011011010111000111001110001010110100000010001101010100000111110011110101001010011100001000101101010001010010001010100011111010011110010100100101001110111000010001111001010111011111100100001111000101101111010111001101111111010111111100001111111110000110; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 15": Call "load_unload" { "TDO"=\l730 XHLHLLLHHLLLHLLLLLLHHHHLHHLLHLLLHLLLLLLHHHHHLHLLLLHHHLHLHHHLLLLHLLLHLHLHHLHHLHHLLLLHLHLLHHHHLHLHHLHHHLLLLHHLHLLHHLLLHHLLLLHLLHHHLLLLHHHLLLLLHLHLLLLHLHHLLHHLHHHLLHLHLLLLLHHHLHLLLLHLLHHLHLLLLHLHHLHLHHLHLHLLHLLLLLLHLLHHLLLHLLHHHHLHLLHLHHLHLLHLLLLLLHLLHLHLLLHHLHLHHHLLHLLHHLLHHLHLHHLHLHLHLHLHHLLLLHLLLLHHHHLLLLLLLHLLHLHLHLLLLHHLLHLHHHHLLHLHLHHHLXLXHLLHHHLLHLHHHLLLLLHLHHHHHHHHHHHHLHLLLHLLHLLHLHLHHHHHLHLHLHHLHHHLLLLLHHLLHLHHLHLLLLLLHLHHLHHLHLHHLLHHHHLLLLLLHHLHLLLLLHHHLHLLLHLLHHLLHHLLHHLLLLLHLLHHLLLLHLHLHHLHLHHLLLHHHHLHHHLHLLHLHLHHHLHLHHLHHHLHLLLHHLHLLLHLLLHLLLLHHLHLHLHHHLLLLLLHHLLLHHHLHHHHHHLHLLHLLHLHHHHHHLHHHLLHLLLHHHHLHHHLLLLHHLHLHLLLHLLLLLLHHLHHHHLLLLHHHLHLLHLLLLHLHLLLHHLLHLLLLLLLHLHLLLLLLLHLHHHLLLLLHLHHLLLLHHHHHHXHXLHLLHLLHLL; "TDI"=\l730 11100001101101110001011111111011100111100000000000010010010000000011101000011001000101011110000000100111010000001100101001100111000100010110011101100010101000100111001111100110010000011110101100101011001100001011011010101001100110000011000110011110010111100001000001100011110110111010100011101100010100110101010111110001001100011000101000011100001110011100011011000000001100111110001110101011100000110001000010110000011101110111010110100010001010111000111101100100101101110000111001001101011100001111111000111010101100010000000011001011100101111100110110000010001011101001101011000101110011001101001001101000011100101110111101101011110101100110010111100010100111001001101100101010000011000001110111000011111010011111000111001101010; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 16": Call "load_unload" { "TDO"=\l730 XLLHHHHLLHLLHLLLHHHLHLLLLLLLLHLLLHHLLLLHHHHHHHHHHHHLHHLHHLHHHHHHHHLLLHLHHHHLLHHLHHHLHLHLLLLHHHHHHHLHHLLLHLHHHHHHLHHLLLLLHHLLHHLHHHHHLLLLHLHLLHHLHLHLLHHLLHHHHLHLLHLLLHHLHLHHLLHLHHHHLHLHLLHLHLHLLHHHLHLLLHHHHLHLHHHHHLHHLHLHLHHLLHHLLHHHHHLLHHHLLHHLLLLHHLHLLLLHHHHLHHHHHLLHHHLLLLHLLHLLLHLHLHHHLLLHLLHHHLHLHHLLHLHLHLHLLLLLHHHLHHLLHHHLLHHHLHLHHHLHLXLXHLHHHLLLHHHHHLLHLLHLHHHHHHHHHHHHLLLHHHLLLHLHLHLLLHHHHHLLHHHLHHHHLHLLHHHHHLLLHLLLHLLLHLHLLHLHHHLHHHLHLHLLLHHHLLLLHLLHHLHHLHLLHLLLHHHHLLLHHLHHLLHLHLLLLLLHHLLHLLHHHHHLHHHLHLLLHLHHLLHLHLLHHHLHLLLHHLLHHLLHHHHLLLLLLLHLLHLLLHHHLHHLHHHHHLLHLLHLLLLLHHLLLLLLLLLHLLHHLHHHLHHLHLHLHLLLLHLHLLHHLLHHLHLLLLHHHLHLHHLLLHHLHHLLHLLHHLHLHLHHHHHLLHHHHHLLLHLLLHHHHLLLLLHLHHLLHLHHLHHLLHLHHHHLLLLHLHXHXHHHLLHLHLL; "TDI"=\l730 10010001111001110011100000101101001101010011100010101101100110101100101111100000011010110001011001110110111010001101111011000011010101000001111000110001110001011010110111010010001000100001010010010011111100011001110111100010110011110001010111011100011110111100001100100010110011010011111110111000011110011000111001100000111100101001100100001000010110110001101011000011011110111110110001001001000000001010110001100100001100100010111000110010010010111100110000100001111100011100111011001000100101010101111000101110000011110101011101011100011010110110111100011011010000101101111111100010000110111000111011001011100101001111100101110010111010100010000110101011101001010101100011111000100100001110011010101100000011111101100001011111100; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 17": Call "load_unload" { "TDO"=\l730 XHHLHHHLLLLHHLLLHHLLLHHHHHLHLLHLHHLLHLHLHHLLLHHHLHLHLLHLLHHLLHLHLLHHLHLLLLLHHHHHHLLHLHLLHHHLHLLLHHLLHLLLHHHLHLLHLLLHLLLHLHHLHHHLHHHLHHHHLHLHHLHHLHHLLLLLLHHHLLHHLLLHLHHLLHLHLHLHLHHHLLHHLHHLLHHHHLHLHLHLHHLHLLLHLLHHLLLHLLLHHHLHLLHHLLLLHHHLHLHLLLHLLLHHHLLLLHLLLLHHHHLLHHLHHHLHLLHHLLHLHHLLLLLLLHLLLHHHHLLLLHHLLHHHLLLHHLLHHHHHLLLLHHLHLHHLLHHLHHLLLXLXLLHLHLHHHHHHHLLHLLHLHHHHHHHHHHHHLLLHLLHHHLHHLHHLHHHHHHHHLHLHLLHHHLLHHLHHHHLLHHLHHHLHLLLHHHLLHHLHHLHHLHLLLLHHLLHHHHLHHHHLLLLLHHHLLLHHLLLHLLHHLHHHLHHLLHLLHLLLLHHHLLHLLHLHHHHLHLLHLLLLLLLLHHHLHHHHLLHLLLLHHHHLLHLHLLLHHHHLHHHHHLHHLLHHLHLLLHHLHLLHHLLLLLLLLHHHLLLHLLHHLHLLLHHLHLHHLLLLLHHLHLLLHHLHLLLHLHLHHHLHHHHLLHLHLHLLLHLHHLHLHLHLLHHHLLLLLHHHLHHLHHHHLLLHHLLHLHLHLLHHHHHHLLLLLLHHHHXHXLLHLHLHHHH; "TDI"=\l730 01000001111100110110001011111010000111000110100111011010101110100111010001101101111101101010101010000010000011010111100100111110111010110011101000000101110000010100101011000010101001011000001011010110110101110111000011000000111101011010000110010111110000111100110000001010111101010001101111010110011010111001100110010111100010011110001110100101100000111111000010110111110000010010000010111110100000101101111010101100001011111011000101010100100100110110001110100100100111111100100111000001010011010011000001110101011101010101001110010010101110010000101001101000100000010100010011110010011100000000101001101110110011000100110111011100111010110100001111101111101011111101100000010001111101001010111010000000011110101000011011100011000; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 18": Call "load_unload" { "TDO"=\l730 XLHHHHHLLLLLHHLLHLLHHHLHLLLLLHLHHHHLLLHHHLLHLHHLLLHLLHLHLHLLLHLHHLLLHLHHHLLHLLHLLLLLHLLHLHLHLHLHLHHHHHLHHHHHLLHLHLHLHLLHHHHLHLHLHHLHLLHHHHHLHLLHLHLLHLLHLHLLLHLLLHHHLHHLLLLHLHLHHLLLLHLHLLLHLHLHHHHLHLHHLHHHHHLHHHHLLLLHHLLLLLHLLLHHHLLHHHHHHLLLLHHLLHHHHHHLHLHLLLLHLHLHHHLLHLLLLHLHLLHHLLHLHLLLHHLLHHLLHHLHLLLLHHHLHHLLLLHHHLLLHHHHHHLLLLHLHLLLLLHLLXLXHLHHLLLLHLHHHHLHLLHHHHHHHHHHHHHHLHLHHHHHLHLLLLLHLHHHHHLHLLHLLLLHLHLHLLHHHHLHLLLLLHLLHHHLHLHLHLHHLHHLHHLLHLLHHHLLLHLHHLHHLHHLLLLLLLLLHHHLLLHLHHLLHHHHLHHHHLHLHHLLHLHHHLHHHHHHLHLHHHLHHLLLLHHLHHLLLHHHHHHLLHLHHLLHHHLHLHLLLHHLHHLLHLHLLHLLHLLHHLHHLLHHLHHHLHHHLHLHHLLHLLLHLLHHLLHHHLHHLLHLLLHLLLHHLLLHLHLLHLHHHHLLLLLHLLLLLHLHLLLLLLHLLHHHHHHLHHHLLLLLHLHHLHLHLLLHLHHHHHHHHLLLLHLHHLLLLHXHXHLLLHHHHHL; "TDI"=\l730 11110101000111001111101011011101110110111101110001000001011011010001111100101110101010100101001101011101011100101111010011101110100000100011111010110111000110000110011100010001110101101111101010111010010110011110110001110101010111001111010110010110000111010100101000110100101101000011011010001010011001101101001110000011101001100000100000010011100111011111110111101110101100011101000100000000110100110001001011111001000000010111101100100000010011101101010111011101010000001111101000111011100100111011101100011010000110101100010000110011010101011110001000111101011110100010001111100010101011111000111011111101101001010000100100010001001011100000001011000101101111111001110111000101001000000110000011010101100111111011100000010101111; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 19": Call "load_unload" { "TDO"=\l730 XLLLHLHLHHHLLLHHLLLLLHLHLLHLLLHLLLHLLHLLLLHLLLHHHLHHHHHLHLLHLLHLHHHLLLLLHHLHLLLHLHLHLHLHHLHLHHLLHLHLLLHLHLLLHHLHLHLLLHHHLHHHLLLHLHLLHLLLLLHLHLHLLLHLHHLHLLHHLLLLHLLHLLLHLHHLLLHLHLHLLLLHHHHHLLHLLLLHLLHLHHLLLLHHLLLLLHHHHLLLHLHLHLHLLLHHLLLLHLHLLHHLHLLHHHHLLLHLHLHHLHLHHHLLHLHHLHLLHLHHHHLLHLLHLHHHLHLHHLLHHLLHLLHLHHLLLHHHHHLLLHLHHLLHHHHHLHHHHHLHLXLXHLLHLLLLLLHHHLLLLLLLHHHHHHHHHHHHLLHLHHHLHHHHHHHHLLHLHHLLHHHLHHLHLLLLLHHLHHHHHHHLHLLLLHLLHHLHHHHHHLHHLLLHLLHLHLHLLLHLLLHLHLHHHHHHLLLLLHLHHHLLLHLLLHLHLLLLHHHLHHHLLLLHLHLLLLHLHHHLHHHLLLLLHHHLHLHLHLLLLHHHHLHLLHHLLHLHHHHHLHLLLLHLHLLLLLHLHHLHHLHHHLHHHHLLLHHHLLLHLLLLLLHLLHLHHLHLHHHHLHHLHHHLHHHLHHLHLLLHHHHHHHLHLLHHHLHLLHLLLLLLLHHLLLHLLLHHHLHLHHLHHHHHHLLHHHHHLLHLHLHLLHHLLLLLLHLHHHXHXHLLLHLLLHH; "TDI"=\l730 00111110111011001101000000011110011011000011111001011111000111001100010111101011101110101000111010000001111001100000100111010101101011000111001010010000111100000011001111100100110001000111111111111000011111010111000011011101010010111010010011000001011111100100101001101100111101000101100000111011001100011000000010011110100101110111101110011101100100011100011011111101000010011110011101001001011101000010101111000011111101010100100000000101010010110000011010001111101010000111001101010100001110110000100111010001000011011111111000100111010011100100100011110001101101101000001110110010111101010010111100010101010110111000111100000110100110000011011101000000011001110101011101111000000111001010010111000010000000110111010011101011110; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 20": Call "load_unload" { "TDO"=\l730 XHLLLLLHLLLHLLHHLLHLHHHHHHHLLLLHHLLHLLHHHHLLLLLHHLHLLLLLHHHLLLHHLLHHHLHLLLLHLHLLLHLLLHLHLHHHLLLHHHHHHHHLLLLHHLLHHHHLLLLLHHLHHLLHHHLHHHLLLLLLLLLLLLHHHHLLLLLHLHLLLHHHHHHLHHLLLHLHLLHHLHHLLLHHLHLHHLHLLLLHLHHLLHLLHLLLHLLHLHHLHHLLLLHHLHHLHLLLLLHHLHHLHLHHLLHLLHHLLLLHLHHHLHLLHHHHHLLLHLLHHLLHHHLLHHHHHHHLHHLLLLHLHHLHLLLHLLLLHLLLHLLLHLHLHHLHLLLHHHLHLXLXLHHHHLLLHLHHHHLLHHHHHHHHHHHHHHHHLLLHHLLLHLHHLHHLHLLLHLHHHHLHLHLLLLHHHHLLLLLLHLHLHLHHLHHHHHHHHLHLHLHHLHLLHHHHHLLHLHHHLLLLLHLHLHHHLLLLHLLLLLLLHLLLHHLLHHLHHLHHHLLLLHHHLLHLLHLLHLHHHHHLLLHLLHHLHLLLLHLHLLLLHLLHHHHLHHHLHLHLLHLHLHLLLHHLHHLLHLLLHLLLLLHLLLLLLHLHLLLLHHHLHLHLHLHLLHLLLHHHLLLLHHHHHLLHLHHLLHHHHHLLHLLLHLHHHHHHHLLHHLLLHLHLHLLLHLLLLHHHHHHLLLHHLHLHHLHLLLHHHHLHHHHHHHLLHLLHLHXHXLHHHHLLHHL; "TDI"=\l730 10010100101100000111011010011101101000010110110010110110010101101001100100101101000000001010100010000010111111010100110010110000000100000010011000010001010011010101010001000010001011010110011110000101011110101101111111010010110101110111011100111111110001011001111101011101011011000010011101011011011101110111000101101110111011001011000011001001001011010000100101010110100101110010111011100110011001101011011010000001000100100110101001001101010111010111010001111000111110000010001101000000110011010100001010111011001101100101101100010100100101000011101000100001001110100001110011100100111111001010110011001110011010111111001110111111110110110000100110101100011101011000111001101111110011111010010011001101011001000011000110010111100; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 21": Call "load_unload" { "TDO"=\l730 XHHLHLHHLHLLHHHHHLLLHLLHLHHLLLHLLHLHHHHLHLLHLLHHLHLLHLLHHLHLHLLHLHHLLHHLHHLHLLHLHHHHHHHHLHLHLHHLLLLHHLHHHLHLHLLLLHLHHHLHHHHLHHHLHLLHLHLLHHLLLLHHHHLHLHLLLLHLHLLHLLLLLLHLLLHLLHHHHHLHLLLLHLLHLLHHHLHHHLHHLHHHLLLLHHLHLHLHHLHHHHHHLHHLLHHHHHHHLHLLHHLLLLLHLHLLLHLHLLHLLHHHHLHHLLLHLHLLHLLHLLLHLLLHLLLHHHLHLLHLLLHLLLHLLHHLHLLHHHLLHLHHLHLLHLHLLLHHLLLLLXLXHLLLLLHHHLHHHHLLHLLHHHHHHHHHHHHHLHLHLLLHLLLHHLLHHLLHHLLHLHLLHLLHLHHHHHHLHHHLHHLHHLLHLHLHHLHHLLHLHLHLLLHLHLLLHLHHHLLLLHHHLLLLLHHHHLLHHHLLHLHHHHHHLLLHHHHLLLHLHHHLHHHHLHHLLLHLHHHHLLLHHLLLHHLHHLLLLLLHHHHLLHLHLHHHHLHHLHLHHHLHLHLLLLLLHHHHHLHHHLLLLHHHLLLLLLHLHLHHLLLHHLLHLLLLLLLLLHLLHLLHHHHLHHLLHLHLLHHHLLLHLHLLHHHLLLHHLLHLLLLLLHHLLLLLHLHHLHHLLHHLLHLHLLHHLHHHLHLLHHLLHHLLLHHLLLLHLHXHXHLHLHLHHLL; "TDI"=\l730 10101000110101110000000101100111000001000011110111001110000100101100001110000001101011011000001110010010000010110000111100101010001101001010100101011010000101110001011111101100101111100110110000110100101110001000001000111010101011101101101111001010000000100101000101000010110010010001100010110110111101111011001010010100111101001001010100001111101100101001000001001111110000101011100111010100110100110100001101011001010101010000001000000011110100011011111011001001110100001100101101111010000011111111010011101011010011110001001110101001110011101100101010011011111000101011010010001110011010011100011000110000100011101011101011100111000000111010110011101000100101001110100101101111001101101111101001110101010110100010100001111101010; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 22": Call "load_unload" { "TDO"=\l730 XHLHLHHHLLHLHLLLHHHHHHHLHLLHHLLLHHHHHLHHHHLLLLHLLLHHLLLHHHHLHHLHLLHHHHLLLHHHHHHLLHLHLLHLLHHHHHLLLHHLHHLHHHHHLHLLHHLLLLLLHLLHHLHLLLLLHHLLHLLHHHHLLHLHHLHLLLHHHLHHHHHLLHHLLLHLHHHLLLLLLLHLHHHHHHHLHLHLLLLLLHLLLLHHHHLLHHLHLHHHHHLLHHHLLHLHLHHHHLHHLHLHHHLHLHHHHLHLLHHLHHLHHHLLHHHLHLLHLLHLLLLHLLLLHLLHHLHLHHLHLHHLLLLHLHHLHHLHLHHHLLLHLHLHLHLLLHLLHHLLLXLXHLLHHHLHLLHHHHLHHLHLLLLLLLHHHHHHLHLLLHHLLLHLHLHHLLHLHHLLHLHHHHLLHLHLLHHLHLHLHLHLHHHHHHLHHHHHHHLLLLHLHHHLLHLLLLLHLLHHLHHLLLHLHHHHLLHHLHLLHLLLLHLHHHLLHLLHHLHLHLHHLLHLLLLLHHHLHLHLLHLHHLHHHLLLHHLLHLHHLHHHLLHHLHHLHHLLLHHLHLHHLLHHLHHLLHHHLLLLHLHHLLLHHHHLLLHHHLLHHHLLHHHHLHHHLLLHLHLLLHLHLLLHHLLLHHHHHHLLLHLHLLHHLLLHLHHHLHHLHLHHLLLHLHHLHLLHLLLLHHLLHLLHLLLLLHLHHLLLHLHLHLHLLHLHHHHLHHXHXHHHLLHLHHH; "TDI"=\l730 11000001011001001101111010001000001110001001000010000010110000001010000011000010011011000001010101000111010111011011011100100100010010000101100101101101000110000111101001010110010001011100010101000101111011101000000110111111010001101001111100101101111011110000100100111100101001100001000110100101010001110010010010001111001101101100100110001001100110111011101011101010010011110010001110011000110110101001100101010101011000011011110111000001111010010101100000101010000101100111010011001000111110011000101101100000110101101011100110001011000001111000100101011111010110001111110100100101101101100100010111100100100010010110101100001100011101000000011001101001001011010000000010101001100011011000010111100100110000111010001010010100000; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 23": Call "load_unload" { "TDO"=\l730 XLHHHHHLHLLHHLHHLLHLLLLHLHHHLHHHHHLLLHHHLHHLHHHHLHHHHHLHLLHHHHHHLHLHHHHHLLHHHHLHHLLHLLHHHHHLHLHLHHHHHHHHLLLHLHLLHLHLHHLHLHLLHHLHHHLHLLLHHHLHLHLHHHLHLLLLHLLLHLHHHHHHHHHLHHLLLHLHLLHHLLLHLLHLHHHHHLLLHHLLHLHLLLHHHHLLHHHHLHLLLLLLHLHHHLLHLHHLLLLLHHLHLLHLLLLHLLLLHHHHLHHLHHLLLLHHLHLHHLLHHHHLHHHLLHLHHLHLHLHHHLLLHHLHHLHHLHHHLLLLHHLLHLLHLLHHLHHHHHLLLXLXLLHLHLLHHLHHHHLHLLLLHHHHHHHHHHHHLHLHHHLLLHHLLHHHLLHLLHLHLHHLLHHLHLHLHLHLHLLHHHHLLHLLLLHLLLHHHHHLLLLHLHHLHLHLLHHHHHLHLHLHHHHLHLLHHLLLHHLLHHHHLLLHHLLLLLHHHLHHLHLHLLLLLHLHLLHHHLLLLLLHLHHLHHLHLLHLLHLLHLLLHHLLHHHLHLLHLHLHHLLLLLHLLHHLLHHHHLHLHLLLHHHLHLLLLLHHHLHLLLLHHLHHLHHHLHHLHLLHLHLLHHHHLLHHHLLLHLHHHHHHHLLHHLLHLHHLHHLHLLHLHHHHHHHHLHLHLHHLLHHHLLHLLHHHHLHLLLLHHLHHLLHHHHLLLHHLLHXHXHHHHLHHHHL; "TDI"=\l730 11001010010000101101101010100000011100101101011111100101001110101001011011000011111111110011011110000010001111111111101000001101111111110110110101010011011000110000100001001011110011001111001110111000000011010000111011100111110100000000101111111111011111110101111001110101001101011000111010101111110110001100100010011110100101001111001101010000011111001100100100110000001000101001000111010010100110110111011111010110101001011010110111001101010000110010111000111001001011100000111111000110000101000111011000101011010001011111011001111100110110001111011101111110111110101000101000011000011110101101000110011100100000100100100111100110011110100010011001110110011100111100010010111101001010001110000101101100110101000010001101000110010; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 24": Call "load_unload" { "TDO"=\l730 XLHHLHLHHLHHHHLHLLHLLHLHLHLHHHHHHLLLHHLHLLHLHLLLLLLHHLHLHHLLLHLHLHHLHLLHLLHHHHLLLLLLLLLLHHLLHLLLLHHHHHLHHHLLLLLLLLHHHHLHHLHLLLLHHLLHHLLLLHHLLLHLLLHHHHHHHLLHLHHHHLLLLLLLHLHHHHHLHLLLHLHHLLHHHLLHHLLHLHLHHLLLLHHLHLLHLLLLLLHHLLLLLLHLHHHLLLLLLLLHLHLLLLHHLLLHLHLHHLLHLHLLHHHLLLHLHLHLLLLLLHLLHHHLLHHLHHHLHHLLLLHLHHLHLHHLLLLHHLLLLHHLLLLLHLHHHHHLHLLHLXLXLHHLHHLLHHHHHLLLHLHHHHHHHLHHHHHHLHHLHHHLLLHLHHLHLHHLLHLLHLLLHLLLLLHLHLLHLHLHHLHLLHLHLLHLLLHHLLHLHLHHHHLLHHLHLLLHHHLLLHHLHHLHLLLHHHHHLLLLLLHHHLLHHHHHHLLLLHLLLHLLLLLLHLLLLLHLHLHHHLHLHHHHLLHHHHLLLLHLHHLHLHHHLLLHLLLHHHLLHHHHHLLLLLLLHLLHLLLHLHHHHHHLHLLHLLHHLLHLHHHHLHHHLHHHLLHHLLLLHLHHHLHHLLHHLLLHLLHHLLLHHLLLLHHHLHHLHLLLLHLHHLHLHHHLLLHHHHLHLLHLLHHLLHLHLHHLHLHHHLLHHLLLHHLHHHHLLHXHXLLLHLHLHLH; "TDI"=\l730 01111101011000001010100101111001101111010000110001101010011011001110110001000000010110000111100010001101011101100010000101111100000001000111111101001110110100110000101110110101100001110011001010111110011000010011101000010110110001100101110000110100101000011010111011100101010010001111100100101000010010101101000011111001011100100111111000010100011010111110010110110111011001001110101101100101101000010011001100101011000110000110011011001110001000010001111101110110011001111111100110110010101111011001010111010001111010000100110100111001011110110000000101110111101100001001101000010100101110001010010100100000010011010110101010010110010001101100010010011111000010001010110010100100001010001000000001000111101011010110100110100000000; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 25": Call "load_unload" { "TDO"=\l730 XLLLLLHLHLLHHHHHLHLHLHHLHLLLLHHLLHLLLLHLHHHHLLHHHLLHLHLHHLLHLLHHLLLHLLHHHLHHHHHHHLHLLHHHHLLLLHHHLHHHLLHLHLLLHLLHHLHLLLHLLHLHLLHHHHLLLHHLLHHLHLHLLLLLHHLLHHHHLHHLLLHLHLHHHHLHLLLLHLHHLLHHHLHHHLHHLHLHLHHHHHLLLHLLLHHLLHLHHLHLLLLHHLHLLLHLHLHHHHLLHLHLLLHLLLHHLHLHLHHLHHHLLLLLHHLHHLHLHHHHLHHLHLHLLHLHHHHLLLLLHHLHLLLHHLHHLLLLLLHHHLHLLHLLHHHLLHHHHHLHLXLXHHHHLLLLHHLHHLLLLLHHHHHHHHHHHLHHLLLHLHLLHLLHHLHLLHLHHHHLHHLLHHLLHHLHLHLLHHHLLHHHHLLHHLLHLLHHLLLHHHLHHHHLHHHLLLLLHLLLHLLHHLLHHLLLLLLLLHHLLHLLHHLHLHHLLHHHHHHHLHLLLHLLLLHLLHHHHLHHLLHLHHHHLHLHHLHLLLHHHHLHLHLLHLHHHHLLHHHLLLLHLLHLLHLHHLHLLHHLHHLLLLHLLLLHLHLHHLHLHHLHHHHHHLHHLLHLHLLHLHLHLHHLHLLHHLHHHLLHLLHHHLHHLHHLLLLLHHHHLHHHLHLHLLHHLHLHHLHHHHLHLHHHLHHHHHHHHLHHHLLLLHLHLLHLHLHLHHXHXHHHHHHHHLL; "TDI"=\l730 01100100101110101001100110101111110101001101010111100100001101101010001100010001000110100011000101011000011111010001000101110011010010101111101100001100000101011100110110010101100011001011101100001111010101001110010110100011011011111111111000100100010100100000110001101111011101000111001110011001101100000111010010000101101011010111001010000110110011111011111001011000111110111100011001001101110100100100101001101010010001111010000101000100011111000001000110001101010101110011111010101111101110001010000001011100111110100100001110100011000100101110111001010011100111000100110001010110011100011010111110111100101001101010001011111011000111010001101000110100000101000010110100001101001101011101001010111110001100101111000000100101101; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 26": Call "load_unload" { "TDO"=\l730 XLLHHLHHLHLLLHLHLHHLLHHLLHLHLLLLLLHLHLHHLLHLHLHLLLLHHLHHHHLLHLLHLHLHHHLLHHHLHHHLHHHLLHLHHHLLHHHLHHLHHLLLHHLHHLLLHLLHLLHHLHLHLLHHHLLHHLHLLLHLLHHHHLLLLHLHLHLHHLLLHHLHLLLLLLHHHHLLLLLLHLLHHHHLLHLHHLLHLLLHHHHHLLLHHLHLHHLHLHLHHHLLHLLHLLLLLLLLLLLHHHLHHLHHHLHLHHLHHHHHLLHHHLLHLLLLHLLLHLHHHLLLHHLLLHHLLHHLLHLLHHHHHLLLHLHHLHHHHLHLLHLHLLHLHLLLHHLHLHLLLXLXLLLHLLLHLHHHHLLHHLLHHHHHHHHHHHHHLLHHHLLHHLHHLLHLLLHLHHLHHLHHLHLHHLLHLHLHHLHHHLLLLHLHHHHLHLHHHLHHHLLLLLHHHHHLHHHLLHHHLLHLHLHLHLLLHHLLLLLHLHLHLLLLLHHLHLLLHLLLHHLHLHHLLLHHLLLHHHLHHLLHHHLHLHLLHHLLLHHHLLLLHHHLHHLLLLLLLLHHLHHHLHHHHHHHLLLHLLHHLHLHLLHLHLHHLLLHHHLHHLLLHLLHLHLLHLLHHHLLLHLHHHLLHLHHHLLHLHHHHHLHLHHHHLHLLHLHHHHLLHLHHLLHLHLLLHLHHLHLHLLLLLHHHLLHHLHHLHLLLLLHLLLLHHLHLLLHLHXHXHLLLHLHLHH; "TDI"=\l730 00001110101011011000101011101010110000001111011001110111000010011001010001001110001100100111000101110101000101011010010000101001110001000010111010010101100111010101010100011101110111101011011110001000111011111011011011010111111100110000111011001101110000110011001001100100111010001001000011111001111101101100111110001101110111111110110010110110010110000000100111011101110100001101111000001001000011111000100111011001011110000101010010011010111000011100101111011011010010001001011110000000111111010100100111001001110010011110001111101111100100100110000100001001110101110110110110001110010111011111000010101001001101010010011101010010000111111001011101100011100011011011010001010100001000011101010001011100101111110100000101111000101; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 27": Call "load_unload" { "TDO"=\l730 XHHHLLLHLHLHLLHLLHHHLHLHLLLHLHLHLLHHHHHHLLLLHLLHHLLLHLLLHHHHLHHLLHHLHLHHHLHHLLLHHHLLHHLHHLLLHHHLHLLLHLHLHHHLHLHLLHLHLHHHLLLHLLLHLLLLHLHLLHLLLLHHHLHHHLLLHLLLLLHLLHLLHLHHLHHHHLHLHHLLHLHLLLLHLLHLHHLHHLLLLHLHHHLLHLLHHHHHLLHLHLLLLLLLHHLLHHHHLLLHLLHHLLHLLLHHHHLLHHLLHHLHHLLHHLHHLLLHLHHHLHHLHHHHLLLLLHHLLLLLHLLHLLHHLLLLLHHHLLHLLLHLLLLLLLLHLLHHLLHHLXLXLLLLLHHHLHHHHHLLLLLHHHHHHHHHHHHHHLHLLLLHHHHHLHHLHHHHLLLLLHHHLHHLLLHLLHHLHLLLLHHHHLHLHLHHLHHLLHLHLLLHHHHLLLHHLHLLLLHLLHLLHLHHLHHHLHHLHLLLLHHHHHHHLLHLHHLLHHHHLHHHHLHHLLLHLHLLLHLLHLLHLLHHHLLLHHLHLLLHLLLLLHLHLHHLHLHLHLLHHHLLHLHLHHLHHHLHHHHHLLHHHLHLHHHHLHHHHLLHHLHLLHLHHLLHHLHHHHLLLLLLHHLHLLLHLLHHHLLLHHHLLHLLHLLHLHHHLHLHLHHHHLHHHHLLLHLHLHHHLHLLLHHLHLLLLLLLLLHHHHLHLHLHHLHHHHLLLHXHXHLLLLLHLLH; "TDI"=\l730 11110011000111101001000001001011100001000111000010011001001101010111101110100010001100101110101010111100001111111011101101110111111111111000010100000111000110100001001101000110010101100000000010001110101111010110011001111100011001001011100110000100010100000010111011000001010011101101000101000011011110011101100101001000001100000010000001110010111110100101110010110111111000101110010010011111100000000100111101001011110100101010100010111111100010001010101110000010001000010111110100110010101111111001010111110111001000011110010110010001110001101110011011011010011110101010001001111100001000000001111010010010010100010000001110111111111011010011111011110011001110101001010100101001100111001101011000111100011001101110100011001010101; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 28": Call "load_unload" { "TDO"=\l730 XLLLHHLLHHHLLLLHLHHLHHHHHLHHLHLLLHHHHLHHHLLLHHHHLHHLLHHLHHLLHLHLHLLLLHLLLHLHHHLHHHLLHHLHLLLHLHLHLHLLLLHHHHLLLLLLLHHLLHLHHHLLHHLHLHLLHHHHHHHHHLHHHLLLHLHLLLLHLHLLHHLLHLLLHLLHLLLLHLHHHHHLLHLLHLLLHHLHHLLLLHLHHHHHLHLHLHHHHHHHLHHLHLHLLLHHHHLHHHHHHLHLLLHLLHHHHHLHLHHLLLHLLHLHHHLHLHHHHLLHLLLLHHLLLHLLHHLHLHHLHHHHHLLHHHHHHLHHHHHLLLLLHHHLLHHLHHLHLHHHLXLXHLLHLHHLLHHHHLLHLLHHLHHHHHHHHHHHLLLHHLHHLHHLLLLLLHHHHHHHHLHHLLLLHLHHLHLLLLHLHHLHLHLHLHHHLHLLLLLLLHHHLHHHLHLHLHLLLHHHHHLHHHLHHHHLLLLLLLHHLHHHLHLHLLLLHLLLHHLLHLLHLLHLHHLLLLHLHLHLHHHLHHLLLLLHHHHLHHHHHLLHLLHLLHHLLHHLLHHLHLHLLLLHLLLHHHHHLHLHLLLHLLLHLHHHLHHLLLLHLHHLHHLHHLHLHHHLHHHHHHLLLHLLLLLLLLLHLLHLHHLLLLLHLLLLHHLLHHLLLHLHLHHLHLHLHHLHLHHLLHHLLLHHLLHLHLLHHHLLLLHHHLLHHLLHLLHLHHXHXHLHLLLHLHL; "TDI"=\l730 10111000011000110100011001010100101111011110001100000000101010101101000000010101100011010001011000100111000101110100011100011000000111001111111011110001010110000010111011111110100010100010011111001010100100001111101110010011010011100100000101010111110101100010100110111101011011010010110000010101000111100011011111000001100111100101010010011110101001011110111101111110111000111101010100100110100001100010001000010010010100001010110010100000000111000011111000000011101001011100111111010000110111111101001001000110100100011000111010001001110111011010100010111111111010101101100000011111011111010100100001000110001101101101111101000010011110010011010000101011100010101110110000110010100000101100100110011010111010101001010101001010000; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 29": Call "load_unload" { "TDO"=\l730 XHLLLHHHHLLHHHLLHLHHHLLHHLHLHLHHLHLLLLHLLLLHHHLLHHHHHHHHLHLHLHLHLLHLHHHHHHHLHLHLLHHHLLHLHHHLHLLHHHHLHHHHLHHLLLLHLLLLHLLLLLLLHLHHHLHLHHHLHHLLLLLHHLHLHLHHLHHHHLLLLLHLLHHHLLLHHHLLHHLLLLLLLLLLHLHLLLLHHLHHLHLLLHLLLLLLLLLHLHHLHHLLHLHHLLLHHLHHHHHLHLHLHLLLLLHLHLLHHHLHLHHLLHLLLLHLHLLHLLHLHHLHLLHHHHHLHLHLHHHLLLLHHHLLHLLLLLHHHHHLLHHLLLLHHLHLHLHHLHLHLXLXLLLHHLLLLHHHHLLLLHHHHHHHHHHHHHHHLLHLHLHLHHLHHLLHLHHHHLLHHHLHHHLHHHHLHHLHHLHLHHHHLHLHLLHHLHLHHHHHHHHLLLHHHHLLLLLHHHHHHHLLLHLHHLHLLHHLLHLHLHHHHLLLHLLHLLHLHLHHHLHLLLLLLLLLHLHLHLLHLLHHHHHHLLLLLHLLLLLHLHLLLLLLLHLHHLLHHLHHHLLLHLHHLHLHLHHLLLLLHHHHLHLLLHHLLLHHLHHHHLHHHLLHHHLLHLLHLLHLLLLLHLHHHHLHHLLLLHHLHHLLHLHHHHLHLHLLLHHHLHLHLLLHLLHHHHLLHHLHLHHHHHLHLLHHLHHLLHHLLHLHLLLHLHLHLHHHLHXHXLLLLHHHHLH; "TDI"=\l730 10000010011001010011101101111000000111101110111001101100111010111111011101100110101001101000100100111111111100010001111000100111000111100111100010100101010010011000001000110011100100010110101001110011011101100011011000110010011101011100101010110101000000011001010100011010001110100011000001001110100101000010011100001110010101100000111110010100000001001111001100010100111011110110011000000101000101000011110000101100100101010100001110101010111001101010011110110111101001101001000010011111101001101100110001111110001000001011001101100110011011010101110010100011111110110001110001100111011010111110111011100100010101000101011101001000110011111111100100101110011001110011110110010000001001001111110111011011110101110110011110000010110; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 30": Call "load_unload" { "TDO"=\l730 XHHHHHLHHLLHHLHLHHLLLHLLHLLLLHHHHHHLLLLHLLLHLLLHHLLHLLHHLLLHLHLLLLLLHLLLHLLHHLLHLHLHHLLHLHHHLHHLHHLLLLLLLLLLHHHLHHHLHHHLLHHLLLHHLHHHLHLLHLHLHHLLLHHLLHLLLHLLHHHLLHLLHHLLLLHHHLHHLLHHLLHLHHLHHHHLHLLLHLHHHHHLLLLLHLLHHLLHHHLLHHLHHLLLHLHLLLHHLHLHLHLLHLHLHHHHHHHLLHHLHLHLHHHLLHLHHHLLLHLHHHLLHHHHHLHHLLLHLHHLHLHHHHLHHLLLHHHHLLLHHLHLHLLHHHHHLLLHHHLHLXLXLHHLLHLLHHHHHLLLHHLHHHHHHHHHHHHHLLLHHLLHHHHHHLHLHHHLHLHHHHLLLLHHHHLHLLHHLHHLHLHLHLHHHHLLLHLHLHLHLLLHHLLHLHLHHLLLLHLLHLLLLHLHHLLHLHHLHHHHLHHLLLLLLHLHLHLHLLLHHLHLHHHLLLLLLLHLLHHHLLLHHHLLHHLLLHLLHLHLLLHHLLHLLHHLHLLHLHHHLHHLLLHLLHLLHHLHLLHLHLHHHHLLLHHLLLHHHLLHHHLLHLHLLHHLHHHLLHHLLLLLLLLLHHLHHLHLLLHHLLHHLLLHHLLLLHLLHHLHHHHHHLHHLHHLLLLLLHLLLHLLHLLLLHLHLLLLLHLLLHLLLHHLHHHLHLHLLHXHXLHHLHLLHLL; "TDI"=\l730 10011011101101111010010110110101010011100000011101110101001110100100000100000011110000001101111001011111001001110010010110100110111010001110111010101001011111110101101011111111010101001100111110101110111000001101011011011000100010100101100001110010001010010000010001111010111011011001010000001100100101001101111101100100000001010100001101100011111000111101100111101010011101111111011100100001110001101111100001100001011000001010111010111100001010101110101000010101000110111100101100001101111110010110101010010100111111101100001111001000001011110111111101000001110010101110100010001111101000111011011001100000010001111101110010110000010101111011101010011100000100111010011000111111101000100000001110111110011010000001101111001010000; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 31": Call "load_unload" { "TDO"=\l730 XHHLLHLLLHLLHLLLLHLHHLHLLHLLHLHLHLHHLLLHHHHHHLLLHLLLHLHLHHLLLHLHHLHHHHHLHHHHHHLLLLHHHHHHLLHLLLLHHLHLLLLLHHLHHLLLHLHLHLLLLLLLLHLHLHLHHLLHHLLLLLHLHLLLHLLLHHHHHLLHLHLLLLLLLHLLHLHHHHLHLHHLLLLHLLHLLHHHHHLHHLHLLLHLHHLHHHHHLLHLLHHHLHHHLHLHHLHLLHHHHLLLHHLHHHLHLHHLHHHHHLHHHLLLLHLHLLLHLLHLLHHLHLHHHHHHLLHHLHHLHLHHLLHLLLLLHLLHHLHHHHHHHLHLHLHHHHLLLHHLLXLXHHHHHLLLLLHHHLLLLLLLHHHHHHHHHHHHLLLLHLLLHHLHHHHLLLHHHLLHLLLLLHHHHLLHHHHLHLLHHHHHLHLHLLLHLHLLLLHHHHLHLHLHLLLHLHLHHHHLHLHLHHHLLHLLLLHHLHLLHHHHLLHLLLLLLHLLLLLLLHLHHHHHLLLHHLHLHLLLHLHHHLHHHLLLLLHLHHHLLLLHLHLHLLHHLHHLHLHHHLLHLHLHLLHHHHLHHLHHHLHHHLHLLHLHLHLLHLLHHLLHHHHHHLHHHLLLLLHLLLHHLHLLHHHHHLHLHLLLLHLLLHLHLHHLLLHHHHHLHHLLLHLHHLLHHHLLLLLLLHLHHHLHHHHHHHLLLHLLLLLHHLLHLHHHHHHHHHXHXLHLHLHHHLL; "TDI"=\l730 10001100100101100100110000100001101000011001001011101010000111010101110100110000010000000010101000001101011011010000010001101100001001010111011000100110001001100011101000100010110100011000100010011010100000001111110101101101111001100110101011110101100111100010011010010011110000110000100110000110101110100011010100001110110001101000100101011000010111100000000111010011111110110000111101111001100000110011001011100111100100100110011010011010010001100100111010101100011000010001000011111001000000001011000110000111110011110010001011100100100011011010000100000110110110000100111010001100010110010110111111110001111100100110001001101101100011110000111010111000011011010011101101110110000000000011011100111001100100011111011010011010000; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 32": Call "load_unload" { "TDO"=\l730 XHHHLLHHLHHLHLLHHLHHLLHHHHLHHHHLLHLHHHHLLHHLHHLHLLLHLHLHHHHLLLHLHLHLLLHLHHLLHHHHHLHHHHHHHHLHLHLLHHHLHLLLLLLLLHLLHLHLHHHLHHHLHLLHLHHHLLHHHLHHHLHHLLHLHLHHHHHHHLLLLLLHHHHHLHHHLLHLHLHHLLLHHHLLLHHHHLHLHHLLHLHHHLHLLLHHHHLLHLLHLLHLLLLHHLLHHLLHLHLHLLLLHLHLLHHLLLLHHHLHHLLHLHHLHHLLLLHHHHLLHHHHLHHLLHHHHLLHLHLLLHLHHHLLHLHLHHHHLLLHLLHHHLLHLHHHLHHLHLLHLXLXLLHLLHHHHHHHHLLLLLLHHHHHHHHHHHHHLHHHLLLLHLLLLHHLLHHHHHLLHHLLHHLHLLLHHLLLLHHLHHLHHLLHHLLHLHHLLHLHHLHHHLLHHLHHLLLHLHLHLLHHHLLHHHHLHHHHLHLLHHLHLLHHLLLHLLHLHHHHLHHHHHLLHLLHLLHHHHLHHLLLHLHHHLLHHHLHLLHHLHHHHHHLHLLHHHLLHLHLLHLLHHLLHHHHLHHHLLLHLHHHLLLHLHLLLHHLLLLLHHLLLLHHLHHLLHLLHHHLLLLHHHHLLLHLHLLLHHHHLLHLLHLHHLLLHLLHLLLHLLHHHHHHHHHHHLLHLLLHHLLLHHLLHHLHHHLLLHLLLLLLLLHHHLLLLLLHLHXHXHHLLLHHHHL; "TDI"=\l730 00100110111011011011011111101111111111111001101010000101100110111011010110110110101101110110010010111100111111101101110111110101011010101110000110010100110000110001010101001011111101101010011111001011001000001001111100011100010001000011000110101111000010000101011010100111111101011001111000101110011000101010101100111001001110101001000010101101110100011100110110100111010101111111110100000001111000000110000010111010000010110100101000101101100000001001010111000001101111101011011110110001111001111100001000010110001001110000010001110110100100011100010101101110000011100100011001101101000010110100110111101011001000110100001111010011101011011011010100101000001101101110010001111000101100111101100011010111111011011110100000110100011; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 33": Call "load_unload" { "TDO"=\l730 XHLHHLLHLLLHLLHLLHLLHLLLLLLHLLLLLLLLLLLLLHHLLHLHLHHHHLHLLHHLLHLLLHLLHLHLLHLLHLLHLHLLHLLLHLLHHLHLLHLLLHHHLLLHHLLHHHLHLHLHHLHLLLLLLHLLHLHLHHLLLLLHHLHLLHHLHHHHHLHHLLLLHHHLHHHHLHLHLHHLLLHHHHHHHHLLLLLLLHHLLHHHLHHHHHHHLLHHLHLHLHLLLHHHHLLHHHHLHHHHLHLHLLHLHLHHLLLLLLLHLHLLHHLLLLHHHLHLLLHHLLHHHLHLHLHLHLLHHLLLHHLHHLLLHLHLHHLHHHHHHLLLHHHLHHHLHHHHLLHLLXLXLHHHHLLLHLHHHHLLLHLLHHHHHHHHHHHHLLLLLLHLHHHHHHHLLLLHHHHHHLLHHHHHLHLLLHLHHHHHLHLLHLHHLHLHHHLHLLHLLHHHHHHHLHHLHLHLLLHHHHHLLHLLLLLHHHHHHLLLHLLHHHLLHLHHLLLHHHLHLHLLHLLLHHHHHLLLHHLHHHLLHHLLHLLHLHHHHLHLLLLHLHLLLLHLLHLLHHHHLLHLHHLLHHLHLHHLLLHHLLHHLLLHHHLLLLHLLHHHLHHLLLHHHHLHHLLLHLHLLHLLHLLHLHLHHLHLHHHHHLLHLLHLLLHHLHHHLLLLHHHLHLLHHLLLLHLLHHHLLHLHLLLLLLHLLHLLHHLLHLLLLHLHLLHHLLHLHHXHXLLHHHHLLHH; "TDI"=\l730 10001100001010000000000110011010101111111001011100101101011000101110001110001000111011011110111010001111100000111011000101010010101111100110100000100110101110100111100010011111101001011101011110010010111111111110001100011011100011000000001001110101100110101001100001011100010011010101111100100101010100110011100110110111110111011111100111010010110111110100011110010000001100110001000001011010101101010101100001100101010101111011000100100101111101111100011100000010101010011001101001001000011011111100111101000011111011000100000010001001000010011001100110010001100111110011110010000000010010000010010101100010011110100000111001000110100001001010100110011101111100111101100000100000100000000110101101001000100000011110000110101110101; } Call "capture_TCK" { "_pi"=11Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "pattern 34": Call "load_unload" { "TDO"=\l730 XHHHLLHHHHLHLHHHHHHHHHHLLHHLLHLHLHLLLLLLLHHLHLLLHHLHLLHLHLLHHHLHLLLHHHLLLHHHLHHHLLLHLLHLLLLHLLLHLHHLHLLHLHLHHHHLHLHHHLHHLLLLLLHLHHLHLLLHLHLLLLHHLHHLHLLLLLLLLLLLHHHLHLLHHHLHLHLHHLLLLHHLHLLLLHLLLHLHHHLLLLHLHLLLHHLLHHHHLLLLLHHLLHLHHHHHLHLLHLHLHHLLHHHHLHLLLHHHLHHLLHLHLHLLLLLHHLHHLHLHLHLHHLLHHLLLHHLLHLLHLLLLLHLLLHLLLLLLHHHHHLLHLLLHHHLLHHHLLLLHLXLXHHLHHLHLLHHHHLLLLHLHHHHHHHHHHHHHLHHLHHHHHLHLLHLHLHLLHLHLHLHLLHHHHLLHHLHLHLHLHLLLLHLLHHHLHHLHHLHLLLLLHLLLLLHHHLLLHHHHHHLHLHLHLHHLHHLLHHHLHLHHHLHLLHHHLLHHLLHHLLHHLHHHLLHHLLLLLHHLLLLHHLHHHHHHHHLHHLHHHLHLLLLLLHHLLLHLHLHHLHHLLLLLLLHHLLHHLHHLHHHLHLLHLHLHLHHHLLLLLHLLHHHLHHHHLLHLHHHHLHHLHLHLHHLLHHLLLHLLLLLHHLLLLHLLHHHHHLHHHHHLHHHHHHHHLLHLHLLHLHHLHHHLHHHHHHLHLHHLHLHLLHHHLHHLLLHLLHXHXHHHLLLHLLL; "TDI"=\l730 10111000010110011100000011111100101100001001101010010011000001011001001111111101001111110001010101100110010100101101001101010111100101101010000101111011101101001011010110110011101000011010001001110010110001111110001000001101000110100011111100101000000011000110100000010001010001100101010000110110011000100000100101110110010110000111000111010110110111111000110100101111110000101111101101001010110011111111100100110000111001001010000111100010011001110101111011100111000100110100101110011111010001001011010100101100000001010001001111110000110000000110111010010001011111001111101100111000010011100101111111101101111001001111111111010011011110010100011010001010001101110011111011011001101110100110000011011011111110100000111110000111010; } Call "capture_TCK" { "_pi"=10Z0010Z01011Z101000100Z0000P0; "_po"=LXHTTTLTLXLLXLTHHHX; } "end 34 unload": Call "load_unload" { "TDO"=\l730 XHLLLHHHHLHLLHHLLLHHHHHHLLLLLLHHLHLLHHHHLHHLLHLHLHHLHHLLHHHHHLHLLHHLHHLLLLLLLLHLHHLLLLLLHHHLHLHLHLLHHLLHHLHLHHLHLHLHLLHLLHHLLLHLHHHHLLHLHHHLHHLLLHHLHLLHHHLLLLLLHHHLLHLHHLLHLHLLHHLLLHHLLLHHHHHLHLHLLHLHHHLLLLLHHLLLLHHHHHHHLLHLHHHLLHLHHHLLLLLLHHLHLHHHHHHHLLHHHLLHLHHHHHHLHHHLHLHHHLLHHLHLHLHHHHLLHLLHHLLHHHLHHHHHLHHLHLLLHLLHHLHLLHHHHLLLHHHLLLLHLXLXHLLHLLLHLHHHHHLLHHLLHHHHHHHHHHHHLLLLLHLLHLHHLHLHLLHHLLLLLLLLLHHLHHLLHHHHLLLHHLHHLHLHHHHLLLLHHHLHHLLHHLLLHLHLLLLHLLLHHLLLHHHLHHLLHLHLHLHLLLLHLLLHHHHHHHLLHLLLHLHHLHHHLHLLLLLHHLLLLLHLLHHLLLHHHHLHHLLLHHHLHHHHHLHLHHLLLHLHLLLLLLHLLHHLLLLHLHLHHHLLLLHHHHLHLLHLLLLLLLLHLLHLLLLHHLHHLLLLLLLLLLHLHHLLHLLLLHHLHLHHHLLHLHHHLHLHHHLLHLLLHHLLLLLHLLHLLHHLLHLLLHLHHLLHHHHHLLHLLHLLLLLLLHLHLLLLHHXHXHHLLHHLHLL; } } LHHHHLLLLHHHHHHHHHHHHHHHLLHLHLHLHHLHHLLHLHHHHLLHHHLHINTERFACES/STIL/STILVCD/exp1.vtran000064400001440000012000000046561103104161000171430ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > VCD # # Original File: "exp1.stil" # # Target File: "exp1.vcd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil ; {#### INPUT FORMAT ####} orig_file = "exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into VCD format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'VCD'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block SIMULATOR Verilog_VCD {#### OUTPUT FORMAT ####} TIMESCALE = "1ns/100ps", ; target_file = "exp1.vcd"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/STIL/EVCDSTIL/000075500001440000012000000000001103104161000153045ustar00jcosleystaff00000400000023INTERFACES/STIL/EVCDSTIL/exp2.vtran000064400001440000012000000075301103104161000172430ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > STIL # # Original File: "exp1.evcd" # # Target File: "exp2.stil " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into STIL format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'EVCD'->'STIL'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'N', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; { #### ovf timing info #### } Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format STIL {#### OUTPUT FORMAT ####} repeat_threshold = "2" time_stamps = "on" ; target_file "exp2.stil"; {#### OUTPUT VECTOR FILE ####} rename_bus_pins $bus$vec; delete_pins vddo vsso pllvdd pllvss regvdd regvss; end end INTERFACES/STIL/EVCDSTIL/exp1.vtran000064400001440000012000000100561103104161000172370ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > STIL # # Original File: "exp1.evcd" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into STIL format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'EVCD'->'STIL'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'N', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'N', 'N'->'N', 'd'->'0', 'u'->'1', '?'->'N', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'N', 'c'->'N', 'f'->'Z', 'F'->'Z'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'T', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'T', 'F'->'T'; { #### ovf timing info #### } cycle 20 align_to_cycle 20 * @ 12, mclk.O @ 18, ma[6] @ 20, ma[7] @ 20; pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format STIL {#### OUTPUT FORMAT ####} repeat_threshold = "2" time_stamps = "on" ; target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} rename_bus_pins $bus$vec; delete_pins vddo vsso pllvdd pllvss regvdd regvss; end end INTERFACES/STIL/README000064400001440000012000000166131103104161000147560ustar00jcosleystaff00000400000023STIL -------- The main directory is "STIL" and the sub-directories are -> WGLSTIL -> VCDSTIL -> EVCDSTIL -> STILVCD The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLSTIL" contains the translation of WGL file to STIL output format. Sub-directory -> "EVCDSTIL" contains the translation of EVCD file to STIL output format. Sub-directory -> "EVCDSTIL" contains the translation of STIL file to VCD output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The STIL output format is invoked in the TVF_BLOCK of the command file with the following command - optional parameters are shown in[]: TESTER_FORMAT STIL [ -QUOTE_NAMES] { quotes all signal/cell/chain names } [ -USE_SCAN_GROUPS] { creates scan pin groups for Shift } [ -NO_EMPTY_VECTORS] { forces all vectors to contain at lease some wfc assignments } [ SCANIN_DEFAULT = "state"] { any input 'X' is mapped to this } [ SCANIN_CONDITION = "state"] { scan inputs are conditioned to this } { state, default is 'Z' } [ TIME_STAMPS = "OFF" ] { disables timestamps in file } [ UNITS = "units" ] { units = ps, fs, us, .. default is ns } [ INPUT_GROUP = "pinlist"] { specify input signal groups } [ OUTPUT_GROUP = "pinlist"] { specify output signal groups } [ MAX_LINE_LENGTH = "nn"] { defines max length of line (token) } { defaults to 1024 characters } [ REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [ MAX_REPEAT_COUNT = "nn"] { specify limit to repeat count in single vector loops } ; The STIL writer creates a file which conforms to the IEEE Std 1450-1999 (STIL) standard. The optional -QUOTE_NAMES parameter tells vtran to quote all signal, cell and scan chain names in the file. When translating from WGL files, scan chains of varying length may need to be padded. The SCANIN_DEFAULT parameter provides for a way of specifying this pad character - the default is N. If the "^" character is specified, the padding uses the first non-X state in each chain. In the STIL output file, a Condition statement is used prior to Macro calls for scan operations. Scan-in pins are normally conditioned to 'Z' state, but the SCANIN_CONDITION parameter can be used to change this to another state (for example to an "N" state). In the STIL syntax, when two sequential Vectors are identical, the second vector may be comprised of simply "V { }", with no wfc assignment in the brackets. The -NO_EMPTY_VECTORS flag forces every Vector to have a wfc assignment (usually this will be the same as the previous Vector if none was necessary). Normally, for documentation purposes, a timestamp is placed in each vector as a comment. This can be disabled using the TIME_STAMPS = "OFF" parameter. UNITS provides a way to change the default time units from "ns". The INPUT_GROUP and OUTPUT_GROUP parameters provide for a way to selectively group signals for assignments in the STIL file. This can help significantly reduce the STIL file size by grouping signals which have lots of activity separately from those which have little activity. Vtran will use a default grouping, if none is specified, which uses signal direction and timing information as criteria. The MAX_REPEAT_COUNT parameter can be used to limit the repeat count allowed on single-vector repeats in the STIL output file. Repeats which exceed the limit will be broken into multiple repeats. When translating from a WGL file or another STIL file, following flags should be set: tabular_format WGL -cycle, -scan, -include_cells ; or tabular_format STIL -cycle, -scan, -include_cells ; The STIL writer uses the following Waveform characters in the file: inputs: 10ZN, outputs: HLXT The input N state is the undefined (X) state. Therefore, when translating from WGL, STIL or VCD the following state_trans are recommended: For WGL->STIL: state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; For STIL(.1)->STIL(1999): state_trans inputs 'D'->'0', 'U'->'1', '?'->'N'; state_trans outputs 'h'->'H', 'l'->'L', 'x'->'X', 't'->'T', '?'->'X'; For VCD->STIL: state_trans inputs 'x'->'N', 'X'->'N', 'z'->'Z' ; state_trans outputs '0'->'L', '1'->'H', 'Z'->'T', 'z'->'T'; In the STIL directory, the following examples can be run: vtran mscan.cmd { WGL(LogicVision)->STIL translation } vtran d2p.cmd { VCD->STIL translation } vtran lab3.cmd { WGL(TetraMAX)->STIL translation } vtran stila.cmd { STIL(.1)->STIL translation } In each case, an equivalent output STIL file will be generated. An example command file for an WGL -> STIL translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > STIL # # Original File: "exp1.wgl" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl -cycle -scan -include_cells; {#### INPUT FORMAT ####} orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'STIL'#### } state_trans inputs '-'->'Z', 'X'->'N'; state_trans outputs '-'->'X', '1'->'H', '0'->'L', 'Z'->'T'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin resolution = 0.1; { #### .1ns resolution for times #### } tester_format STIL {#### OUTPUT VECTOR FILE ####} -quote_names, { #### quote all signal/cell/chain names #### } scanin_default = "^"; { #### pad short scan chains with first non-X char #### } target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} end; end; ################################################################################ _EMPTY_VECTORS] { forces all vectors to contain at lease some wfc assignments } [ SCANIN_DEFAULT = "sINTERFACES/SWAV/000075500001440000012000000000001103104161000140745ustar00jcosleystaff00000400000023INTERFACES/SWAV/WGLSWAV/000075500001440000012000000000001103104161000152265ustar00jcosleystaff00000400000023INTERFACES/SWAV/WGLSWAV/exp3.vtran000064400001440000012000000046011103104161000171620ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > SWAV # # Original File: "exp1.wgl" # # Target File: "exp3.swav " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into SWAV format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'SWAV'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 99; target_file "exp3.swav"; {#### OUTPUT VECTOR FILE ####} tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; end end; INTERFACES/SWAV/WGLSWAV/exp1.vtran000064400001440000012000000047331103104161000171660ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > SWAV # # Original File: "exp1.wgl" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into SWAV format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'SWAV'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 99; target_file "exp1.swav"; {#### OUTPUT VECTOR FILE ####} tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; end end; INTERFACES/SWAV/WGLSWAV/exp2.vtran000064400001440000012000000045731103104161000171710ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > SWAV # # Original File: "exp1.wgl" # # Target File: "exp2.swav " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into SWAV format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'SWAV'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 99; target_file "exp2.swav"; {#### OUTPUT VECTOR FILE ####} tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; end end; t format. # #======================================================================# INTERFACES/SWAV/STILSWAV/000075500001440000012000000000001103104161000153505ustar00jcosleystaff00000400000023INTERFACES/SWAV/STILSWAV/exp1.vtran000064400001440000012000000051221103104161000173010ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > SWAV # # Original File: "exp1.stil" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into SWAV format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'SWAV'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; target_file = "exp1.swav"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/SWAV/STILSWAV/exp2.vtran000064400001440000012000000047571103104161000173170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > SWAV # # Original File: "exp1.stil" # # Target File: "exp2.swav " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into SWAV format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'SWAV'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; target_file = "exp2.swav"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/SWAV/STILSWAV/exp3.vtran000064400001440000012000000047651103104161000173170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > SWAV # # Original File: "exp1.stil" # # Target File: "exp3.swav " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into SWAV format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'SWAV'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format swav {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "LT1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", DESIGN = "testchip14" ; target_file = "exp3.swav"; {#### OUTPUT VECTOR FILE ####} end; end; ===========INTERFACES/SWAV/LSIMSWAV/000075500001440000012000000000001103104161000153415ustar00jcosleystaff00000400000023INTERFACES/SWAV/LSIMSWAV/exp1.lsim000064400001440000012000001133011103104161000171030ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.lsim" # # Original File: "exp1.lsim" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# CODEFILE UNITS nS {#### INPUT/OUTPUT PIN DESCRIPTION ####} INPUTS RES,FSC,DD,TS0,TS1,TS2,SEL24,IO1(to=40),IO2(to=40), I1,REXT,ID_H,ID_M,ID_L; OUTPUTS O1(to=max),DU(to=max),IO1(to=max),IO2(to=max); CODING(ROM) # !initialize @0 <1110000XXXXXXX >XX..; # !clockdef sysclk_DCL 488 # !subclock sysclk_DCL DCL 0.00%,l 0.00%,t 50.00%,t @488 <1010000XXXXXXX >XX..; @976 <1000000ZZXXXXX >XXLH; @1464 <1010000XXXXXXX >XH..; @1952 <1000000XXXXXXX >XL..; @2440 <1010000XXXXXXX >XH..; @2928 <1000000XXXXXXX >XL..; @3416 <0010000XXXXXXX >XX..; @3904 <0010000XXXXXXX >XX..; @4392 <0010000XXXXXXX >XX..; @4880 <0000000ZZXXXXX >XXHL; @5368 <0010000XXXXXXX >XX..; @5856 <0000000XXXXXXX >XX..; @6344 <0010000XXXXXXX >XX..; @6832 <0000000XXXXXXX >XX..; @7320 <0010000XXXXXXX >XX..; @7808 <0010000XXXXXXX >XX..; @8296 <0010000XXXXXXX >XX..; @8784 <0010000XXXXXXX >XX..; @9272 <0010000XXXXXXX >XX..; @9760 <0010000XXXXXXX >XX..; @10248 <0010000XXXXXXX >XX..; @10736 <0010000XXXXXXX >XX..; @11224 <0010000XXXXXXX >XX..; @11712 <0000000XXXXXXX >XX..; @12200 <0000000XXXXXXX >XX..; @12688 <0000000XXXXXXX >XX..; @13176 <0000000XXXXXXX >XX..; @13664 <0000000XXXXXXX >XX..; @14152 <0000000XXXXXXX >XX..; @14640 <0010000XXXXXXX >XX..; @15128 <0010000XXXXXXX >XX..; @15616 <00h0000XXXXXXX >XX..; @16104 <00h0000XXXXXXX >XX..; @16592 <00h0000XXXXXXX >XX..; @17080 <00h0000XXXXXXX >XX..; @17568 <00h0000XXXXXXX >XX..; @18056 <00h0000XXXXXXX >XX..; @18544 <00h0000XXXXXXX >XX..; @19032 <00h0000XXXXXXX >XX..; @19520 <00h0000XXXXXXX >XX..; @20008 <00h0000XXXXXXX >XX..; @20496 <00h0000XXXXXXX >XX..; @20984 <00h0000XXXXXXX >XX..; @21472 <00h0000XXXXXXX >XX..; @21960 <00h0000XXXXXXX >XX..; @22448 <00h0000XXXXXXX >XX..; @22936 <00h0000XXXXXXX >XX..; @23424 <00h0000XXXXXXX >XX..; @23912 <00h0000XXXXXXX >XX..; @24400 <00h0000XXXXXXX >XX..; @24888 <00h0000XXXXXXX >XX..; @25376 <00h0000XXXXXXX >XX..; @25864 <00h0000XXXXXXX >XX..; @26352 <00h0000XXXXXXX >XX..; @26840 <00h0000XXXXXXX >XX..; @27328 <00h0000XXXXXXX >XX..; @27816 <00h0000XXXXXXX >XX..; @28304 <00h0000XXXXXXX >XX..; @28792 <00h0000XXXXXXX >XX..; @29280 <00h0000XXXXXXX >XX..; @29768 <00h0000XXXXXXX >XX..; @30256 <00h0000XXXXXXX >XX..; @30744 <00h0000XXXXXXX >XX..; @31232 <00h0000XXXXXXX >XX..; @31720 <00h0000XXXXXXX >XX..; @32208 <00h0000XXXXXXX >XX..; @32696 <00h0000XXXXXXX >XX..; @33184 <00h0000XXXXXXX >XX..; @33672 <00h0000XXXXXXX >XX..; @34160 <00h0000XXXXXXX >XX..; @34648 <00h0000XXXXXXX >XX..; @35136 <00h0000XXXXXXX >XX..; @35624 <00h0000XXXXXXX >XX..; @36112 <00h0000XXXXXXX >XX..; @36600 <00h0000XXXXXXX >XX..; @37088 <00h0000XXXXXXX >XX..; @37576 <00h0000XXXXXXX >XX..; @38064 <00h0000XXXXXXX >XX..; @38552 <00h0000XXXXXXX >XX..; @39040 <00h0000XXXXXXX >XX..; @39528 <00h0000XXXXXXX >XX..; @40016 <00h0000XXXXXXX >XX..; @40504 <00h0000XXXXXXX >XX..; @40992 <00h0000XXXXXXX >XX..; @41480 <00h0000XXXXXXX >XX..; @41968 <00h0000XXXXXXX >XX..; @42456 <00h0000XXXXXXX >XX..; @42944 <00h0000XXXXXXX >XX..; @43432 <00h0000XXXXXXX >XX..; @43920 <00h0000XXXXXXX >XX..; @44408 <00h0000XXXXXXX >XX..; @44896 <00h0000XXXXXXX >XX..; @45384 <00h0000XXXXXXX >XX..; @45872 <00h0000XXXXXXX >XX..; @46360 <00h0000XXXXXXX >XX..; @46848 <00h0000XXXXXXX >XX..; @47336 <00h0000XXXXXXX >XX..; @47824 <00h0000XXXXXXX >XX..; @48312 <00h0000XXXXXXX >XX..; @48800 <00h0000XXXXXXX >XX..; @49288 <00h0000XXXXXXX >XX..; @49776 <00h0000XXXXXXX >XX..; @50264 <00h0000XXXXXXX >XX..; @50752 <00h0000XXXXXXX >XX..; @51240 <00h0000XXXXXXX >XX..; @51728 <00h0000XXXXXXX >XX..; @52216 <00h0000XXXXXXX >XX..; @52704 <00h0000XXXXXXX >XX..; @53192 <00h0000XXXXXXX >XX..; @53680 <00h0000XXXXXXX >XX..; @54168 <00h0000XXXXXXX >XX..; @54656 <00h0000XXXXXXX >XX..; @55144 <00h0000XXXXXXX >XX..; @55632 <00h0000XXXXXXX >XX..; @56120 <00h0000XXXXXXX >XX..; @56608 <00h0000XXXXXXX >XX..; @57096 <00h0000XXXXXXX >XX..; @57584 <00h0000XXXXXXX >XX..; @58072 <00h0000XXXXXXX >XX..; @58560 <00h0000XXXXXXX >XX..; @59048 <00h0000XXXXXXX >XX..; @59536 <00h0000XXXXXXX >XX..; @60024 <00h0000XXXXXXX >XX..; @60512 <00h0000XXXXXXX >XX..; @61000 <00h0000XXXXXXX >XX..; @61488 <00h0000XXXXXXX >XX..; @61976 <00h0000XXXXXXX >XX..; @62464 <00h0000XXXXXXX >XX..; @62952 <00h0000XXXXXXX >XX..; @63440 <00h0000XXXXXXX >XX..; @63928 <00h0000XXXXXXX >XX..; @64416 <00h0000XXXXXXX >XX..; @64904 <00h0000XXXXXXX >XX..; @65392 <00h0000XXXXXXX >XX..; @65880 <00h0000XXXXXXX >XX..; @66368 <00h0000XXXXXXX >XX..; @66856 <00h0000XXXXXXX >XX..; @67344 <00h0000XXXXXXX >XX..; @67832 <00h0000XXXXXXX >XX..; @68320 <00h0000XXXXXXX >XX..; @68808 <00h0000XXXXXXX >XX..; @69296 <00h0000XXXXXXX >XX..; @69784 <00h0000XXXXXXX >XX..; @70272 <00h0000XXXXXXX >XX..; @70760 <00h0000XXXXXXX >XX..; @71248 <00h0000XXXXXXX >XX..; @71736 <00h0000XXXXXXX >XX..; @72224 <00h0000XXXXXXX >XX..; @72712 <00h0000XXXXXXX >XX..; @73200 <00h0000XXXXXXX >XX..; @73688 <00h0000XXXXXXX >XX..; @74176 <00h0000XXXXXXX >XX..; @74664 <00h0000XXXXXXX >XX..; @75152 <00h0000XXXXXXX >XX..; @75640 <00h0000XXXXXXX >XX..; @76128 <00h0000XXXXXXX >XX..; @76616 <00h0000XXXXXXX >XX..; @77104 <00h0000XXXXXXX >XX..; @77592 <00h0000XXXXXXX >XX..; @78080 <00h0000XXXXXXX >XX..; @78568 <00h0000XXXXXXX >XX..; @79056 <00h0000XXXXXXX >XX..; @79544 <00h0000XXXXXXX >XX..; @80032 <00h0000XXXXXXX >XX..; @80520 <00h0000XXXXXXX >XX..; @81008 <00h0000XXXXXXX >XX..; @81496 <00h0000XXXXXXX >XX..; @81984 <00h0000XXXXXXX >XX..; @82472 <00h0000XXXXXXX >XX..; @82960 <00h0000XXXXXXX >XX..; @83448 <00h0000XXXXXXX >XX..; @83936 <00h0000XXXXXXX >XX..; @84424 <00h0000XXXXXXX >XX..; @84912 <00h0000XXXXXXX >XX..; @85400 <00h0000XXXXXXX >XX..; @85888 <00h0000XXXXXXX >XX..; @86376 <00h0000XXXXXXX >XX..; @86864 <00h0000XXXXXXX >XX..; @87352 <00h0000XXXXXXX >XX..; @87840 <00h0000XXXXXXX >XX..; @88328 <00h0000XXXXXXX >XX..; @88816 <00h0000XXXXXXX >XX..; @89304 <00h0000XXXXXXX >XX..; @89792 <00h0000XXXXXXX >XX..; @90280 <00h0000XXXXXXX >XX..; @90768 <00h0000XXXXXXX >XX..; @91256 <00h0000XXXXXXX >XX..; @91744 <00h0000XXXXXXX >XX..; @92232 <00h0000XXXXXXX >XX..; @92720 <00h0000XXXXXXX >XX..; @93208 <00h0000XXXXXXX >XX..; @93696 <00h0000XXXXXXX >XX..; @94184 <00h0000XXXXXXX >XX..; @94672 <00h0000XXXXXXX >XX..; @95160 <00h0000XXXXXXX >XX..; @95648 <00h0000XXXXXXX >XX..; @96136 <00h0000XXXXXXX >XX..; @96624 <00h0000XXXXXXX >XX..; @97112 <00h0000XXXXXXX >XX..; @97600 <00h0000XXXXXXX >XX..; @98088 <00h0000XXXXXXX >XX..; @98576 <00h0000XXXXXXX >XX..; @99064 <00h0000XXXXXXX >XX..; @99552 <00h0000XXXXXXX >XX..; @100040 <00h0000XXXXXXX >XX..; @100528 <00h0000XXXXXXX >XX..; @101016 <00h0000XXXXXXX >XX..; @101504 <00h0000XXXXXXX >XX..; @101992 <00h0000XXXXXXX >XX..; @102480 <00h0000XXXXXXX >XX..; @102968 <00h0000XXXXXXX >XX..; @103456 <00h0000XXXXXXX >XX..; @103944 <00h0000XXXXXXX >XX..; @104432 <00h0000XXXXXXX >XX..; @104920 <00h0000XXXXXXX >XX..; @105408 <00h0000XXXXXXX >XX..; @105896 <00h0000XXXXXXX >XX..; @106384 <00h0000XXXXXXX >XX..; @106872 <00h0000XXXXXXX >XX..; @107360 <00h0000XXXXXXX >XX..; @107848 <00h0000XXXXXXX >XX..; @108336 <00h0000XXXXXXX >XX..; @108824 <00h0000XXXXXXX >XX..; @109312 <00h0000XXXXXXX >XX..; @109800 <00h0000XXXXXXX >XX..; @110288 <00h0000XXXXXXX >XX..; @110776 <00h0000XXXXXXX >XX..; @111264 <00h0000XXXXXXX >XX..; @111752 <00h0000XXXXXXX >XX..; @112240 <00h0000XXXXXXX >XX..; @112728 <00h0000XXXXXXX >XX..; @113216 <00h0000XXXXXXX >XX..; @113704 <00h0000XXXXXXX >XX..; @114192 <00h0000XXXXXXX >XX..; @114680 <00h0000XXXXXXX >XX..; @115168 <00h0000XXXXXXX >XX..; @115656 <00h0000XXXXXXX >XX..; @116144 <00h0000XXXXXXX >XX..; @116632 <00h0000XXXXXXX >XX..; @117120 <00h0000XXXXXXX >XX..; @117608 <00h0000XXXXXXX >XX..; @118096 <00h0000XXXXXXX >XX..; @118584 <00h0000XXXXXXX >XX..; @119072 <00h0000XXXXXXX >XX..; @119560 <00h0000XXXXXXX >XX..; @120048 <00h0000XXXXXXX >XX..; @120536 <00h0000XXXXXXX >XX..; @121024 <00h0000XXXXXXX >XX..; @121512 <00h0000XXXXXXX >XX..; @122000 <00h0000XXXXXXX >XX..; @122488 <00h0000XXXXXXX >XX..; @122976 <00h0000XXXXXXX >XX..; @123464 <00h0000XXXXXXX >XX..; @123952 <00h0000XXXXXXX >XX..; @124440 <00h0000XXXXXXX >XX..; @124928 <0110000XXXXXXX >XX..; @125416 <0000000XXXXXXX >XX..; @125904 <0010000XXXXXXX >XX..; @126392 <0000000XXXXXXX >XX..; @126880 <0000000XXXXXXX >XX..; @127368 <0010000XXXXXXX >XX..; @127856 <0010000XXXXXXX >XX..; @128344 <0010000XXXXXXX >XX..; @128832 <0010000XXXXXXX >XX..; @129320 <0010000XXXXXXX >XX..; @129808 <0000000XXXXXXX >XX..; @130296 <0010000XXXXXXX >XX..; @130784 <0000000XXXXXXX >XX..; @131272 <0010000XXXXXXX >XX..; @131760 <0000000XXXXXXX >XX..; @132248 <0010000XXXXXXX >XX..; @132736 <0010000XXXXXXX >XX..; @133224 <0010000XXXXXXX >XX..; @133712 <0010000XXXXXXX >XX..; @134200 <0010000XXXXXXX >XX..; @134688 <0010000XXXXXXX >XX..; @135176 <0010000XXXXXXX >XX..; @135664 <0010000XXXXXXX >XX..; @136152 <0010000XXXXXXX >XX..; @136640 <0000000XXXXXXX >XX..; @137128 <0000000XXXXXXX >XX..; @137616 <0000000XXXXXXX >XX..; @138104 <0000000XXXXXXX >XX..; @138592 <0000000XXXXXXX >XX..; @139080 <0000000XXXXXXX >XX..; @139568 <0010000XXXXXXX >XX..; @140056 <0010000XXXXXXX >XX..; @140544 <00h0000XXXXXXX >XX..; @141032 <00h0000XXXXXXX >XX..; @141520 <00h0000XXXXXXX >XX..; @142008 <00h0000XXXXXXX >XX..; @142496 <00h0000XXXXXXX >XX..; @142984 <00h0000XXXXXXX >XX..; @143472 <00h0000XXXXXXX >XX..; @143960 <00h0000XXXXXXX >XX..; @144448 <00h0000XXXXXXX >XX..; @144936 <00h0000XXXXXXX >XX..; @145424 <00h0000XXXXXXX >XX..; @145912 <00h0000XXXXXXX >XX..; @146400 <00h0000XXXXXXX >XX..; @146888 <00h0000XXXXXXX >XX..; @147376 <00h0000XXXXXXX >XX..; @147864 <00h0000XXXXXXX >XX..; @148352 <00h0000XXXXXXX >XX..; @148840 <00h0000XXXXXXX >XX..; @149328 <00h0000XXXXXXX >XX..; @149816 <00h0000XXXXXXX >XX..; @150304 <00h0000XXXXXXX >XX..; @150792 <00h0000XXXXXXX >XX..; @151280 <00h0000XXXXXXX >XX..; @151768 <00h0000XXXXXXX >XX..; @152256 <00h0000XXXXXXX >XX..; @152744 <00h0000XXXXXXX >XX..; @153232 <00h0000XXXXXXX >XX..; @153720 <00h0000XXXXXXX >XX..; @154208 <00h0000XXXXXXX >XX..; @154696 <00h0000XXXXXXX >XX..; @155184 <00h0000XXXXXXX >XX..; @155672 <00h0000XXXXXXX >XX..; @156160 <00h0000XXXXXXX >XX..; @156648 <00h0000XXXXXXX >XX..; @157136 <00h0000XXXXXXX >XX..; @157624 <00h0000XXXXXXX >XX..; @158112 <00h0000XXXXXXX >XX..; @158600 <00h0000XXXXXXX >XX..; @159088 <00h0000XXXXXXX >XX..; @159576 <00h0000XXXXXXX >XX..; @160064 <00h0000XXXXXXX >XX..; @160552 <00h0000XXXXXXX >XX..; @161040 <00h0000XXXXXXX >XX..; @161528 <00h0000XXXXXXX >XX..; @162016 <00h0000XXXXXXX >XX..; @162504 <00h0000XXXXXXX >XX..; @162992 <00h0000XXXXXXX >XX..; @163480 <00h0000XXXXXXX >XX..; @163968 <00h0000XXXXXXX >XX..; @164456 <00h0000XXXXXXX >XX..; @164944 <00h0000XXXXXXX >XX..; @165432 <00h0000XXXXXXX >XX..; @165920 <00h0000XXXXXXX >XX..; @166408 <00h0000XXXXXXX >XX..; @166896 <00h0000XXXXXXX >XX..; @167384 <00h0000XXXXXXX >XX..; @167872 <00h0000XXXXXXX >XX..; @168360 <00h0000XXXXXXX >XX..; @168848 <00h0000XXXXXXX >XX..; @169336 <00h0000XXXXXXX >XX..; @169824 <00h0000XXXXXXX >XX..; @170312 <00h0000XXXXXXX >XX..; @170800 <00h0000XXXXXXX >XX..; @171288 <00h0000XXXXXXX >XX..; @171776 <00h0000XXXXXXX >XX..; @172264 <00h0000XXXXXXX >XX..; @172752 <00h0000XXXXXXX >XX..; @173240 <00h0000XXXXXXX >XX..; @173728 <00h0000XXXXXXX >XX..; @174216 <00h0000XXXXXXX >XX..; @174704 <00h0000XXXXXXX >XX..; @175192 <00h0000XXXXXXX >XX..; @175680 <00h0000XXXXXXX >XX..; @176168 <00h0000XXXXXXX >XX..; @176656 <00h0000XXXXXXX >XX..; @177144 <00h0000XXXXXXX >XX..; @177632 <00h0000XXXXXXX >XX..; @178120 <00h0000XXXXXXX >XX..; @178608 <00h0000XXXXXXX >XX..; @179096 <00h0000XXXXXXX >XX..; @179584 <00h0000XXXXXXX >XX..; @180072 <00h0000XXXXXXX >XX..; @180560 <00h0000XXXXXXX >XX..; @181048 <00h0000XXXXXXX >XX..; @181536 <00h0000XXXXXXX >XX..; @182024 <00h0000XXXXXXX >XX..; @182512 <00h0000XXXXXXX >XX..; @183000 <00h0000XXXXXXX >XX..; @183488 <00h0000XXXXXXX >XX..; @183976 <00h0000XXXXXXX >XX..; @184464 <00h0000XXXXXXX >XX..; @184952 <00h0000XXXXXXX >XX..; @185440 <00h0000XXXXXXX >XX..; @185928 <00h0000XXXXXXX >XX..; @186416 <00h0000XXXXXXX >XX..; @186904 <00h0000XXXXXXX >XX..; @187392 <00h0000XXXXXXX >XX..; @187880 <00h0000XXXXXXX >XX..; @188368 <00h0000XXXXXXX >XX..; @188856 <00h0000XXXXXXX >XX..; @189344 <00h0000XXXXXXX >XX..; @189832 <00h0000XXXXXXX >XX..; @190320 <00h0000XXXXXXX >XX..; @190808 <00h0000XXXXXXX >XX..; @191296 <00h0000XXXXXXX >XX..; @191784 <00h0000XXXXXXX >XX..; @192272 <00h0000XXXXXXX >XX..; @192760 <00h0000XXXXXXX >XX..; @193248 <00h0000XXXXXXX >XX..; @193736 <00h0000XXXXXXX >XX..; @194224 <00h0000XXXXXXX >XX..; @194712 <00h0000XXXXXXX >XX..; @195200 <00h0000XXXXXXX >XX..; @195688 <00h0000XXXXXXX >XX..; @196176 <00h0000XXXXXXX >XX..; @196664 <00h0000XXXXXXX >XX..; @197152 <00h0000XXXXXXX >XX..; @197640 <00h0000XXXXXXX >XX..; @198128 <00h0000XXXXXXX >XX..; @198616 <00h0000XXXXXXX >XX..; @199104 <00h0000XXXXXXX >XX..; @199592 <00h0000XXXXXXX >XX..; @200080 <00h0000XXXXXXX >XX..; @200568 <00h0000XXXXXXX >XX..; @201056 <00h0000XXXXXXX >XX..; @201544 <00h0000XXXXXXX >XX..; @202032 <00h0000XXXXXXX >XX..; @202520 <00h0000XXXXXXX >XX..; @203008 <00h0000XXXXXXX >XX..; @203496 <00h0000XXXXXXX >XX..; @203984 <00h0000XXXXXXX >XX..; @204472 <00h0000XXXXXXX >XX..; @204960 <00h0000XXXXXXX >XX..; @205448 <00h0000XXXXXXX >XX..; @205936 <00h0000XXXXXXX >XX..; @206424 <00h0000XXXXXXX >XX..; @206912 <00h0000XXXXXXX >XX..; @207400 <00h0000XXXXXXX >XX..; @207888 <00h0000XXXXXXX >XX..; @208376 <00h0000XXXXXXX >XX..; @208864 <00h0000XXXXXXX >XX..; @209352 <00h0000XXXXXXX >XX..; @209840 <00h0000XXXXXXX >XX..; @210328 <00h0000XXXXXXX >XX..; @210816 <00h0000XXXXXXX >XX..; @211304 <00h0000XXXXXXX >XX..; @211792 <00h0000XXXXXXX >XX..; @212280 <00h0000XXXXXXX >XX..; @212768 <00h0000XXXXXXX >XX..; @213256 <00h0000XXXXXXX >XX..; @213744 <00h0000XXXXXXX >XX..; @214232 <00h0000XXXXXXX >XX..; @214720 <00h0000XXXXXXX >XX..; @215208 <00h0000XXXXXXX >XX..; @215696 <00h0000XXXXXXX >XX..; @216184 <00h0000XXXXXXX >XX..; @216672 <00h0000XXXXXXX >XX..; @217160 <00h0000XXXXXXX >XX..; @217648 <00h0000XXXXXXX >XX..; @218136 <00h0000XXXXXXX >XX..; @218624 <00h0000XXXXXXX >XX..; @219112 <00h0000XXXXXXX >XX..; @219600 <00h0000XXXXXXX >XX..; @220088 <00h0000XXXXXXX >XX..; @220576 <00h0000XXXXXXX >XX..; @221064 <00h0000XXXXXXX >XX..; @221552 <00h0000XXXXXXX >XX..; @222040 <00h0000XXXXXXX >XX..; @222528 <00h0000XXXXXXX >XX..; @223016 <00h0000XXXXXXX >XX..; @223504 <00h0000XXXXXXX >XX..; @223992 <00h0000XXXXXXX >XX..; @224480 <00h0000XXXXXXX >XX..; @224968 <00h0000XXXXXXX >XX..; @225456 <00h0000XXXXXXX >XX..; @225944 <00h0000XXXXXXX >XX..; @226432 <00h0000XXXXXXX >XX..; @226920 <00h0000XXXXXXX >XX..; @227408 <00h0000XXXXXXX >XX..; @227896 <00h0000XXXXXXX >XX..; @228384 <00h0000XXXXXXX >XX..; @228872 <00h0000XXXXXXX >XX..; @229360 <00h0000XXXXXXX >XX..; @229848 <00h0000XXXXXXX >XX..; @230336 <00h0000XXXXXXX >XX..; @230824 <00h0000XXXXXXX >XX..; @231312 <00h0000XXXXXXX >XX..; @231800 <00h0000XXXXXXX >XX..; @232288 <00h0000XXXXXXX >XX..; @232776 <00h0000XXXXXXX >XX..; @233264 <00h0000XXXXXXX >XX..; @233752 <00h0000XXXXXXX >XX..; @234240 <00h0000XXXXXXX >XX..; @234728 <00h0000XXXXXXX >XX..; @235216 <00h0000XXXXXXX >XX..; @235704 <00h0000XXXXXXX >XX..; @236192 <00h0000XXXXXXX >XX..; @236680 <00h0000XXXXXXX >XX..; @237168 <00h0000XXXXXXX >XX..; @237656 <00h0000XXXXXXX >XX..; @238144 <00h0000XXXXXXX >XX..; @238632 <00h0000XXXXXXX >XX..; @239120 <00h0000XXXXXXX >XX..; @239608 <00h0000XXXXXXX >XX..; @240096 <00h0000XXXXXXX >XX..; @240584 <00h0000XXXXXXX >XX..; @241072 <00h0000XXXXXXX >XX..; @241560 <00h0000XXXXXXX >XX..; @242048 <00h0000XXXXXXX >XX..; @242536 <00h0000XXXXXXX >XX..; @243024 <00h0000XXXXXXX >XX..; @243512 <00h0000XXXXXXX >XX..; @244000 <00h0000XXXXXXX >XX..; @244488 <00h0000XXXXXXX >XX..; @244976 <00h0000XXXXXXX >XX..; @245464 <00h0000XXXXXXX >XX..; @245952 <00h0000XXXXXXX >XX..; @246440 <00h0000XXXXXXX >XX..; @246928 <00h0000XXXXXXX >XX..; @247416 <00h0000XXXXXXX >XX..; @247904 <00h0000XXXXXXX >XX..; @248392 <00h0000XXXXXXX >XX..; @248880 <00h0000XXXXXXX >XX..; @249368 <00h0000XXXXXXX >XX..; @249856 <01100000000000 >XX..; @250344 <00000000001000 >XX..; @250832 <00100000001000 >XX..; @251320 <00000000001000 >XX..; @251808 <00000000001000 >XX..; @252296 <00000000001000 >XX..; @252784 <00000000000000 >XX..; @253272 <00100000000000 >XX..; @253760 <00100000000000 >XX..; @254248 <00100000000000 >XX..; @254736 <00000000000000 >XX..; @255224 <00100000000000 >XX..; @255712 <00000000000000 >XX..; @256200 <00100000000000 >XX..; @256688 <00000000000000 >XX..; @257176 <00100000000000 >XX..; @257664 <00100000000000 >XH..; @258152 <00000000000000 >XH..; @258640 <00000000000000 >XH..; @259128 <00000000000000 >XH..; @259616 <00000000000000 >XH..; @260104 <00000000000000 >XH..; @260592 <00000000000000 >XH..; @261080 <00100000000000 >XH..; @261568 <00000000000000 >XX..; @262056 <00000000000000 >XX..; @262544 <00000000000000 >XX..; @263032 <00000000000000 >XX..; @263520 <00000000000000 >XX..; @264008 <00000000000000 >XX..; @264496 <00100000000000 >XH..; @264984 <00000000000000 >XH..; @265472 <00l00000000000 >XH..; @265960 <00l00000000000 >XH..; @266448 <00l00000000000 >XH..; @266936 <00l00000000000 >XH..; @267424 <00l00000000000 >XH..; @267912 <00l00000000000 >XH..; @268400 <00l00000000000 >XH..; @268888 <00l00000000000 >XH..; @269376 <00l00000000000 >XH..; @269864 <00l00000000000 >XH..; @270352 <00l00000000000 >XH..; @270840 <00l00000000000 >XH..; @271328 <00l00000000000 >XH..; @271816 <00l00000000000 >XH..; @272304 <00l00000000000 >XH..; @272792 <00l00000000000 >XH..; @273280 <00l00000000000 >XH..; @273768 <00l00000000000 >XH..; @274256 <00l00000000000 >XH..; @274744 <00l00000000000 >XH..; @275232 <00l00000000000 >XH..; @275720 <00l00000000000 >XH..; @276208 <00l00000000000 >XH..; @276696 <00l00000000000 >XH..; @277184 <00l00000000000 >XH..; @277672 <00l00000000000 >XH..; @278160 <00l00000000000 >XH..; @278648 <00l00000000000 >XH..; @279136 <00l00000000000 >XH..; @279624 <00l00000000000 >XH..; @280112 <00l00000000000 >XH..; @280600 <00l00000000000 >XH..; @281088 <00l00000000000 >XH..; @281576 <00l00000000000 >XH..; @282064 <00l00000000000 >XH..; @282552 <00l00000000000 >XH..; @283040 <00l00000000000 >XH..; @283528 <00l00000000000 >XH..; @284016 <00l00000000000 >XH..; @284504 <00l00000000000 >XH..; @284992 <00l00000000000 >XH..; @285480 <00l00000000000 >XH..; @285968 <00l00000000000 >XH..; @286456 <00l00000000000 >XH..; @286944 <00l00000000000 >XH..; @287432 <00l00000000000 >XH..; @287920 <00l00000000000 >XH..; @288408 <00l00000000000 >XH..; @288896 <00l00000000000 >XH..; @289384 <00l00000000000 >XH..; @289872 <00l00000000000 >XH..; @290360 <00l00000000000 >XH..; @290848 <00l00000000000 >XH..; @291336 <00l00000000000 >XH..; @291824 <00l00000000000 >XH..; @292312 <00l00000000000 >XH..; @292800 <00l00000000000 >XH..; @293288 <00l00000000000 >XH..; @293776 <00l00000000000 >XH..; @294264 <00l00000000000 >XH..; @294752 <00l00000000000 >XH..; @295240 <00l00000000000 >XH..; @295728 <00l00000000000 >XH..; @296216 <00l00000000000 >XH..; @296704 <00l00000000000 >XH..; @297192 <00l00000000000 >XH..; @297680 <00l00000000000 >XH..; @298168 <00l00000000000 >XH..; @298656 <00l00000000000 >XH..; @299144 <00l00000000000 >XH..; @299632 <00l00000000000 >XH..; @300120 <00l00000000000 >XH..; @300608 <00l00000000000 >XH..; @301096 <00l00000000000 >XH..; @301584 <00l00000000000 >XH..; @302072 <00l00000000000 >XH..; @302560 <00l00000000000 >XH..; @303048 <00l00000000000 >XH..; @303536 <00l00000000000 >XH..; @304024 <00l00000000000 >XH..; @304512 <00l00000000000 >XH..; @305000 <00l00000000000 >XH..; @305488 <00l00000000000 >XH..; @305976 <00l00000000000 >XH..; @306464 <00l00000000000 >XH..; @306952 <00l00000000000 >XH..; @307440 <00l00000000000 >XH..; @307928 <00l00000000000 >XH..; @308416 <00l00000000000 >XH..; @308904 <00l00000000000 >XH..; @309392 <00l00000000000 >XH..; @309880 <00l00000000000 >XH..; @310368 <00l00000000000 >XH..; @310856 <00l00000000000 >XH..; @311344 <00l00000000000 >XH..; @311832 <00l00000000000 >XH..; @312320 <00l00000000000 >XH..; @312808 <00l00000000000 >XH..; @313296 <00l00000000000 >XH..; @313784 <00l00000000000 >XH..; @314272 <00l00000000000 >XH..; @314760 <00l00000000000 >XH..; @315248 <00l00000000000 >XH..; @315736 <00l00000000000 >XH..; @316224 <00l00000000000 >XH..; @316712 <00l00000000000 >XH..; @317200 <00l00000000000 >XH..; @317688 <00l00000000000 >XH..; @318176 <00l00000000000 >XH..; @318664 <00l00000000000 >XH..; @319152 <00l00000000000 >XH..; @319640 <00l00000000000 >XH..; @320128 <00l00000000000 >XH..; @320616 <00l00000000000 >XH..; @321104 <00l00000000000 >XH..; @321592 <00l00000000000 >XH..; @322080 <00l00000000000 >XH..; @322568 <00l00000000000 >XH..; @323056 <00l00000000000 >XH..; @323544 <00l00000000000 >XH..; @324032 <00l00000000000 >XH..; @324520 <00l00000000000 >XH..; @325008 <00l00000000000 >XH..; @325496 <00l00000000000 >XH..; @325984 <00l00000000000 >XH..; @326472 <00l00000000000 >XH..; @326960 <00l00000000000 >XH..; @327448 <00l00000000000 >XH..; @327936 <00l00000000000 >XH..; @328424 <00l00000000000 >XH..; @328912 <00l00000000000 >XH..; @329400 <00l00000000000 >XH..; @329888 <00l00000000000 >XH..; @330376 <00l00000000000 >XH..; @330864 <00l00000000000 >XH..; @331352 <00l00000000000 >XH..; @331840 <00l00000000000 >XH..; @332328 <00l00000000000 >XH..; @332816 <00l00000000000 >XH..; @333304 <00l00000000000 >XH..; @333792 <00l00000000000 >XH..; @334280 <00l00000000000 >XH..; @334768 <00l00000000000 >XH..; @335256 <00l00000000000 >XH..; @335744 <00l00000000000 >XH..; @336232 <00l00000000000 >XH..; @336720 <00l00000000000 >XH..; @337208 <00l00000000000 >XH..; @337696 <00l00000000000 >XH..; @338184 <00l00000000000 >XH..; @338672 <00l00000000000 >XH..; @339160 <00l00000000000 >XH..; @339648 <00l00000000000 >XH..; @340136 <00l00000000000 >XH..; @340624 <00l00000000000 >XH..; @341112 <00l00000000000 >XH..; @341600 <00l00000000000 >XH..; @342088 <00l00000000000 >XH..; @342576 <00l00000000000 >XH..; @343064 <00l00000000000 >XH..; @343552 <00l00000000000 >XH..; @344040 <00l00000000000 >XH..; @344528 <00l00000000000 >XH..; @345016 <00l00000000000 >XH..; @345504 <00l00000000000 >XH..; @345992 <00l00000000000 >XH..; @346480 <00l00000000000 >XH..; @346968 <00l00000000000 >XH..; @347456 <00l00000000000 >XH..; @347944 <00l00000000000 >XH..; @348432 <00l00000000000 >XH..; @348920 <00l00000000000 >XH..; @349408 <00l00000000000 >XH..; @349896 <00l00000000000 >XH..; @350384 <00l00000000000 >XH..; @350872 <00l00000000000 >XH..; @351360 <00l00000000000 >XH..; @351848 <00l00000000000 >XH..; @352336 <00l00000000000 >XH..; @352824 <00l00000000000 >XH..; @353312 <00l00000000000 >XH..; @353800 <00l00000000000 >XH..; @354288 <00l00000000000 >XH..; @354776 <00l00000000000 >XH..; @355264 <00l00000000000 >XH..; @355752 <00l00000000000 >XH..; @356240 <00l00000000000 >XH..; @356728 <00l00000000000 >XH..; @357216 <00l00000000000 >XH..; @357704 <00l00000000000 >XH..; @358192 <00l00000000000 >XH..; @358680 <00l00000000000 >XH..; @359168 <00l00000000000 >XH..; @359656 <00l00000000000 >XH..; @360144 <00l00000000000 >XH..; @360632 <00l00000000000 >XH..; @361120 <00l00000000000 >XH..; @361608 <00l00000000000 >XH..; @362096 <00l00000000000 >XH..; @362584 <00l00000000000 >XH..; @363072 <00l00000000000 >XH..; @363560 <00l00000000000 >XH..; @364048 <00l00000000000 >XH..; @364536 <00l00000000000 >XH..; @365024 <00l00000000000 >XH..; @365512 <00l00000000000 >XH..; @366000 <00l00000000000 >XH..; @366488 <00l00000000000 >XH..; @366976 <00l00000000000 >XH..; @367464 <00l00000000000 >XH..; @367952 <00l00000000000 >XH..; @368440 <00l00000000000 >XH..; @368928 <00l00000000000 >XH..; @369416 <00l00000000000 >XH..; @369904 <00l00000000000 >XH..; @370392 <00l00000000000 >XH..; @370880 <00l00000000000 >XH..; @371368 <00l00000000000 >XH..; @371856 <00l00000000000 >XH..; @372344 <00l00000000000 >XH..; @372832 <00l00000000000 >XH..; @373320 <00l00000000000 >XH..; @373808 <00l00000000000 >XH..; @374296 <00l00000000000 >XH..; @374784 <01100000000000 >XX..; @375272 <00000000000000 >XX..; @375760 <00000000000000 >XX..; @376248 <00000000000000 >XX..; @376736 <00000000000000 >XX..; @377224 <00000000000000 >XX..; @377712 <00000000000000 >XX..; @378200 <00100000000000 >XX..; @378688 <00100000000000 >XX..; @379176 <00100000000000 >XX..; @379664 <00000000000000 >XX..; @380152 <00100000000000 >XX..; @380640 <00000000000000 >XX..; @381128 <00100000000000 >XX..; @381616 <00000000000000 >XX..; @382104 <00100000000000 >XX..; @382592 <00100000000000 >XH..; @383080 <00000000000000 >XH..; @383568 <00000000000000 >XH..; @384056 <00000000000000 >XH..; @384544 <00000000000000 >XH..; @385032 <00000000000000 >XH..; @385520 <00000000000000 >XH..; @386008 <00100000000000 >XH..; @386496 <00000000000000 >XX..; @386984 <00000000000000 >XX..; @387472 <00000000000000 >XX..; @387960 <00000000000000 >XX..; @388448 <00000000000000 >XX..; @388936 <00000000000000 >XX..; @389424 <00100000000000 >XL..; @389912 <00000000000000 >XH..; @390400 <00l00000000000 >XH..; @390888 <00l00000000000 >XH..; @391376 <00l00000000000 >XH..; @391864 <00l00000000000 >XH..; @392352 <00l00000000000 >XH..; @392840 <00l00000000000 >XH..; @393328 <00l00000000000 >XH..; @393816 <00l00000000000 >XH..; @394304 <00l00000000000 >XH..; @394792 <00l00000000000 >XH..; @395280 <00l00000000000 >XH..; @395768 <00l00000000000 >XH..; @396256 <00l00000000000 >XH..; @396744 <00l00000000000 >XH..; @397232 <00l00000000000 >XH..; @397720 <00l00000000000 >XH..; @398208 <00l00000000000 >XH..; @398696 <00l00000000000 >XH..; @399184 <00l00000000000 >XH..; @399672 <00l00000000000 >XH..; @400160 <00l00000000000 >XH..; @400648 <00l00000000000 >XH..; @401136 <00l00000000000 >XH..; @401624 <00l00000000000 >XH..; @402112 <00l00000000000 >XH..; @402600 <00l00000000000 >XH..; @403088 <00l00000000000 >XH..; @403576 <00l00000000000 >XH..; @404064 <00l00000000000 >XH..; @404552 <00l00000000000 >XH..; @405040 <00l00000000000 >XH..; @405528 <00l00000000000 >XH..; @406016 <00l00000000000 >XH..; @406504 <00l00000000000 >XH..; @406992 <00l00000000000 >XH..; @407480 <00l00000000000 >XH..; @407968 <00l00000000000 >XH..; @408456 <00l00000000000 >XH..; @408944 <00l00000000000 >XH..; @409432 <00l00000000000 >XH..; @409920 <00l00000000000 >XH..; @410408 <00l00000000000 >XH..; @410896 <00l00000000000 >XH..; @411384 <00l00000000000 >XH..; @411872 <00l00000000000 >XH..; @412360 <00l00000000000 >XH..; @412848 <00l00000000000 >XH..; @413336 <00l00000000000 >XH..; @413824 <00l00000000000 >XH..; @414312 <00l00000000000 >XH..; @414800 <00l00000000000 >XH..; @415288 <00l00000000000 >XH..; @415776 <00l00000000000 >XH..; @416264 <00l00000000000 >XH..; @416752 <00l00000000000 >XH..; @417240 <00l00000000000 >XH..; @417728 <00l00000000000 >XH..; @418216 <00l00000000000 >XH..; @418704 <00l00000000000 >XH..; @419192 <00l00000000000 >XH..; @419680 <00l00000000000 >XH..; @420168 <00l00000000000 >XH..; @420656 <00l00000000000 >XH..; @421144 <00l00000000000 >XH..; @421632 <00l00000000000 >XH..; @422120 <00l00000000000 >XH..; @422608 <00l00000000000 >XH..; @423096 <00l00000000000 >XH..; @423584 <00l00000000000 >XH..; @424072 <00l00000000000 >XH..; @424560 <00l00000000000 >XH..; @425048 <00l00000000000 >XH..; @425536 <00l00000000000 >XH..; @426024 <00l00000000000 >XH..; @426512 <00l00000000000 >XH..; @427000 <00l00000000000 >XH..; @427488 <00l00000000000 >XH..; @427976 <00l00000000000 >XH..; @428464 <00l00000000000 >XH..; @428952 <00l00000000000 >XH..; @429440 <00l00000000000 >XH..; @429928 <00l00000000000 >XH..; @430416 <00l00000000000 >XH..; @430904 <00l00000000000 >XH..; @431392 <00l00000000000 >XH..; @431880 <00l00000000000 >XH..; @432368 <00l00000000000 >XH..; @432856 <00l00000000000 >XH..; @433344 <00l00000000000 >XH..; @433832 <00l00000000000 >XH..; @434320 <00l00000000000 >XH..; @434808 <00l00000000000 >XH..; @435296 <00l00000000000 >XH..; @435784 <00l00000000000 >XH..; @436272 <00l00000000000 >XH..; @436760 <00l00000000000 >XH..; @437248 <00l00000000000 >XH..; @437736 <00l00000000000 >XH..; @438224 <00l00000000000 >XH..; @438712 <00l00000000000 >XH..; @439200 <00l00000000000 >XH..; @439688 <00l00000000000 >XH..; @440176 <00l00000000000 >XH..; @440664 <00l00000000000 >XH..; @441152 <00l00000000000 >XH..; @441640 <00l00000000000 >XH..; @442128 <00l00000000000 >XH..; @442616 <00l00000000000 >XH..; @443104 <00l00000000000 >XH..; @443592 <00l00000000000 >XH..; @444080 <00l00000000000 >XH..; @444568 <00l00000000000 >XH..; @445056 <00l00000000000 >XH..; @445544 <00l00000000000 >XH..; @446032 <00l00000000000 >XH..; @446520 <00l00000000000 >XH..; @447008 <00l00000000000 >XH..; @447496 <00l00000000000 >XH..; @447984 <00l00000000000 >XH..; @448472 <00l00000000000 >XH..; @448960 <00l00000000000 >XH..; @449448 <00l00000000000 >XH..; @449936 <00l00000000000 >XH..; @450424 <00l00000000000 >XH..; @450912 <00l00000000000 >XH..; @451400 <00l00000000000 >XH..; @451888 <00l00000000000 >XH..; @452376 <00l00000000000 >XH..; @452864 <00l00000000000 >XH..; @453352 <00l00000000000 >XH..; @453840 <00l00000000000 >XH..; @454328 <00l00000000000 >XH..; @454816 <00l00000000000 >XH..; @455304 <00l00000000000 >XH..; @455792 <00l00000000000 >XH..; @456280 <00l00000000000 >XH..; @456768 <00l00000000000 >XH..; @457256 <00l00000000000 >XH..; @457744 <00l00000000000 >XH..; @458232 <00l00000000000 >XH..; @458720 <00l00000000000 >XH..; @459208 <00l00000000000 >XH..; @459696 <00l00000000000 >XH..; @460184 <00l00000000000 >XH..; @460672 <00l00000000000 >XH..; @461160 <00l00000000000 >XH..; @461648 <00l00000000000 >XH..; @462136 <00l00000000000 >XH..; @462624 <00l00000000000 >XH..; @463112 <00l00000000000 >XH..; @463600 <00l00000000000 >XH..; @464088 <00l00000000000 >XH..; @464576 <00l00000000000 >XH..; @465064 <00l00000000000 >XH..; @465552 <00l00000000000 >XH..; @466040 <00l00000000000 >XH..; @466528 <00l00000000000 >XH..; @467016 <00l00000000000 >XH..; @467504 <00l00000000000 >XH..; @467992 <00l00000000000 >XH..; @468480 <00l00000000000 >XH..; @468968 <00l00000000000 >XH..; @469456 <00l00000000000 >XH..; @469944 <00l00000000000 >XH..; @470432 <00l00000000000 >XH..; @470920 <00l00000000000 >XH..; @471408 <00l00000000000 >XH..; @471896 <00l00000000000 >XH..; @472384 <00l00000000000 >XH..; @472872 <00l00000000000 >XH..; @473360 <00l00000000000 >XH..; @473848 <00l00000000000 >XH..; @474336 <00l00000000000 >XH..; @474824 <00l00000000000 >XH..; @475312 <00l00000000000 >XH..; @475800 <00l00000000000 >XH..; @476288 <00l00000000000 >XH..; @476776 <00l00000000000 >XH..; @477264 <00l00000000000 >XH..; @477752 <00l00000000000 >XH..; @478240 <00l00000000000 >XH..; @478728 <00l00000000000 >XH..; @479216 <00l00000000000 >XH..; @479704 <00l00000000000 >XH..; @480192 <00l00000000000 >XH..; @480680 <00l00000000000 >XH..; @481168 <00l00000000000 >XH..; @481656 <00l00000000000 >XH..; @482144 <00l00000000000 >XH..; @482632 <00l00000000000 >XH..; @483120 <00l00000000000 >XH..; @483608 <00l00000000000 >XH..; @484096 <00l00000000000 >XH..; @484584 <00l00000000000 >XH..; @485072 <00l00000000000 >XH..; @485560 <00l00000000000 >XH..; @486048 <00l00000000000 >XH..; @486536 <00l00000000000 >XH..; @487024 <00l00000000000 >XH..; @487512 <00l00000000000 >XH..; @488000 <00l00000000000 >XH..; @488488 <00l00000000000 >XH..; @488976 <00l00000000000 >XH..; @489464 <00l00000000000 >XH..; @489952 <00l00000000000 >XH..; @490440 <00l00000000000 >XH..; @490928 <00l00000000000 >XH..; @491416 <00l00000000000 >XH..; @491904 <00l00000000000 >XH..; @492392 <00l00000000000 >XH..; @492880 <00l00000000000 >XH..; @493368 <00l00000000000 >XH..; @493856 <00l00000000000 >XH..; @494344 <00l00000000000 >XH..; @494832 <00l00000000000 >XH..; @495320 <00l00000000000 >XH..; @495808 <00l00000000000 >XH..; @496296 <00l00000000000 >XH..; @496784 <00l00000000000 >XH..; @497272 <00l00000000000 >XH..; @497760 <00l00000000000 >XH..; @498248 <00l00000000000 >XH..; @498736 <00l00000000000 >XH..; @499224 <00l00000000000 >XH..; @499712 <01000000000000 >XX..; @500200 <00000000000000 >XX..; @500688 <00100000000000 >XX..; @501176 <00100000000000 >XX..; @501664 <00100000000000 >XX..; @502152 <00000000000000 >XX..; @502640 <00000000000000 >XX..; @503128 <00000000000000 >XX..; @503616 <00100000000000 >XX..; @504104 <00100000000000 >XX..; @504592 <00000000000000 >XX..; @505080 <00100000000000 >XX..; @505568 <00000000000000 >XX..; @506056 <00100000000000 >XX..; @506544 <00000000000000 >XX..; @507032 <00100000000000 >XX..; @507520 <00000000000000 >XH..; @508008 <00000000000000 >XH..; @508496 <00000000000000 >XH..; @508984 <00000000000000 >XH..; @509472 <00000000000000 >XH..; @509960 <00100000000000 >XH..; @510448 <00000000000000 >XH..; @510936 <00100000000000 >XH..; @511424 <00000000000000 >XX..; @511912 <00000000000000 >XX..; @512400 <00000000000000 >XX..; @512888 <00000000000000 >XX..; @513376 <00000000000000 >XX..; @513864 <00000000000000 >XX..; @514352 <00100000000000 >XL..; @514840 <00100000000000 >XH..; @515328 <00h00000000000 >XH..; @515816 <00h00000000000 >XH..; @516304 <00h00000000000 >XH..; @516792 <00h00000000000 >XH..; @517280 <00h00000000000 >XH..; @517768 <00h00000000000 >XH..; @518256 <00h00000000000 >XH..; @518744 <00h00000000000 >XH..; @519232 <00h00000000000 >XH..; @519720 <00h00000000000 >XH..; @520208 <00h00000000000 >XH..; @520696 <00h00000000000 >XH..; @521184 <00h00000000000 >XH..; @521672 <00h00000000000 >XH..; @522160 <00h00000000000 >XH..; @522648 <00h00000000000 >XH..; @523136 <00h00000000000 >XH..; @523624 <00h00000000000 >XH..; @524112 <00h00000000000 >XH..; @524600 <00h00000000000 >XH..; @525088 <00h00000000000 >XH..; @525576 <00h00000000000 >XH..; @526064 <00h00000000000 >XH..; @526552 <00h00000000000 >XH..; @527040 <00h00000000000 >XH..; @527528 <00h00000000000 >XH..; @528016 <00h00000000000 >XH..; @528504 <00h00000000000 >XH..; @528992 <00h00000000000 >XH..; @529480 <00h00000000000 >XH..; @529968 <00h00000000000 >XH..; @530456 <00h00000000000 >XH..; @530944 <00h00000000000 >XH..; @531432 <00h00000000000 >XH..; @531920 <00h00000000000 >XH..; @532408 <00h00000000000 >XH..; @532896 <00h00000000000 >XH..; @533384 <00h00000000000 >XH..; @533872 <00h00000000000 >XH..; @534360 <00h00000000000 >XH..; @534848 <00h00000000000 >XH..; @535336 <00h00000000000 >XH..; @535824 <00h00000000000 >XH..; @536312 <00h00000000000 >XH..; @536800 <00h00000000000 >XH..; @537288 <00h00000000000 >XH..; @537776 <00h00000000000 >XH..; @538264 <00h00000000000 >XH..; @538752 <00h00000000000 >XH..; @539240 <00h00000000000 >XH..; @539728 <00h00000000000 >XH..; @540216 <00h00000000000 >XH..; @540704 <00h00000000000 >XH..; @541192 <00h00000000000 >XH..; @541680 <00h00000000000 >XH..; @542168 <00h00000000000 >XH..; @542656 <00h00000000000 >XH..; @543144 <00h00000000000 >XH..; @543632 <00h00000000000 >XH..; @544120 <00h00000000000 >XH..; @544608 <00h00000000000 >XH..; @545096 <00h00000000000 >XH..; @545584 <00h00000000000 >XH..; @546072 <00h00000000000 >XH..; @546560 <00h00000000000 >XH..; @547048 <00h00000000000 >XH..; @547536 <00h00000000000 >XH..; @548024 <00h00000000000 >XH..; @548512 <00h00000000000 >XH..; @549000 <00h00000000000 >XH..; @549488 <00h00000000000 >XH..; @549976 <00h00000000000 >XH..; @550464 <00h00000000000 >XH..; @550952 <00h00000000000 >XH..; @551440 <00h00000000000 >XH..; @551928 <00h00000000000 >XH..; @552416 <00h00000000000 >XH..; @552904 <00h00000000000 >XH..; @553392 <00h00000000000 >XH..; @553880 <00h00000000000 >XH..; @554368 <00h00000000000 >XH..; @554856 <00h00000000000 >XH..; @555344 <00h00000000000 >XH..; @555832 <00h00000000000 >XH..; @556320 <00h00000000000 >XH..; @556808 <00h00000000000 >XH..; @557296 <00h00000000000 >XH..; @557784 <00h00000000000 >XH..; @558272 <00h00000000000 >XH..; @558760 <00h00000000000 >XH..; @559248 <00h00000000000 >XH..; @559736 <00h00000000000 >XH..; @560224 <00h00000000000 >XH..; @560712 <00h00000000000 >XH..; @561200 <00h00000000000 >XH..; @561688 <00h00000000000 >XH..; @562176 <00h00000000000 >XH..; @562664 <00h00000000000 >XH..; @563152 <00h00000000000 >XH..; @563640 <00h00000000000 >XH..; @564128 <00h00000000000 >XH..; @564616 <00h00000000000 >XH..; @565104 <00h00000000000 >XH..; @565592 <00h00000000000 >XH..; @566080 <00h00000000000 >XH..; @566568 <00h00000000000 >XH..; @567056 <00h00000000000 >XH..; @567544 <00h00000000000 >XH..; @568032 <00h00000000000 >XH..; @568520 <00h00000000000 >XH..; @569008 <00h00000000000 >XH..; @569496 <00h00000000000 >XH..; @569984 <00h00000000000 >XH..; @570472 <00h00000000000 >XH..; @570960 <00h00000000000 >XH..; @571448 <00h00000000000 >XH..; @571936 <00h00000000000 >XH..; @572424 <00h00000000000 >XH..; @572912 <00h00000000000 >XH..; @573400 <00h00000000000 >XH..; @573888 <00h00000000000 >XH..; @574376 <00h00000000000 >XH..; @574864 <00h00000000000 >XH..; @575352 <00h00000000000 >XH..; @575840 <00h00000000000 >XH..; @576328 <00h00000000000 >XH..; @576816 <00h00000000000 >XH..; @577304 <00h00000000000 >XH..; @577792 <00h00000000000 >XH..; @578280 <00h00000000000 >XH..; @578768 <00h00000000000 >XH..; @579256 <00h00000000000 >XH..; @579744 <00h00000000000 >XH..; @580232 <00h00000000000 >XH..; @580720 <00h00000000000 >XH..; @581208 <00h00000000000 >XH..; @581696 <00h00000000000 >XH..; @582184 <00h00000000000 >XH..; @582672 <00h00000000000 >XH..; @583160 <00h00000000000 >XH..; @583648 <00h00000000000 >XH..; @584136 <00h00000000000 >XH..; @584624 <00h00000000000 >XH..; @585112 <00h00000000000 >XH..; @585600 <00h00000000000 >XH..; @586088 <00h00000000000 >XH..; @586576 <00h00000000000 >XH..; @587064 <00h00000000000 >XH..; @587552 <00h00000000000 >XH..; @588040 <00h00000000000 >XH..; @588528 <00h00000000000 >XH..; @589016 <00h00000000000 >XH..; @589504 <00h00000000000 >XH..; @589992 <00h00000000000 >XH..; @590480 <00h00000000000 >XH..; @590968 <00h00000000000 >XH..; @591456 <00h00000000000 >XH..; @591944 <00h00000000000 >XH..; @592432 <00h00000000000 >XH..; @592920 <00h00000000000 >XH..; @593408 <00h00000000000 >XH..; @593896 <00h00000000000 >XH..; @594384 <00h00000000000 >XH..; @594872 <00h00000000000 >XH..; @595360 <00h00000000000 >XH..; END H..; @434808 <00l00000000000 >XH..; @435296 <00l00000000000 >XH..; @435784 <00l00000000000 >XH..; @436272 <00l00000000000 >XH..; @436760 <00l00000000000 >XH..; @437248 <00l00000000000 >XH..; @437736 <00l00000000000 >XH..; @438224 <00l00000000000 >XH..; @438712 <00l00000000000 >XH..; @439200 <00l00000000000 >XH..; @439INTERFACES/SWAV/LSIMSWAV/exp1.vtran000064400001440000012000000052431103104161000172760ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: LSIM < to > SWAV # # Original File: "exp1.lsim" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp1.lsim"; {#### INPUT VECTOR FILE ####} tabular_format lsim ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the LSIM # # vector data to translate into SWAV format # #======================================================================# } proc_block begin; { #### state character translations for 'LSIM'->'SWAV'#### } state_trans 'x'->'X', '?'->'X', 'z'->'Z', '.'->'X', 'H'->'1', 'L'->'0'; cycle = 488; align_to_step 488 487; {#### collapse to cycle data ####} disable_vector_filter; {#### Timing Info for SWAV file #### } pintype stb * @ 486, 488; { #### all outputs ####} pintype nrz * @ 0; pintype nrz RES FSC DD TS0 @ 40; separate_timing; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } {#### this puts the vertical pin names in as comments####} rename_bus_pins $bus_$vec; {#### flatten busses ####} tester_format swav ; {#### OUTPUT FORMAT ####} target_file "exp1.swav"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/SWAV/EVCDSWAV/000075500001440000012000000000001103104161000153165ustar00jcosleystaff00000400000023INTERFACES/SWAV/EVCDSWAV/exp2.vtran000064400001440000012000000076061103104161000172610ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > SWAV # # Original File: "exp1.evcd" # # Target File: "exp2.swav " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} { bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into SWAV format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'SWAV'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; {#### timing info ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; TESTER_FORMAT SWAV {#### OUTPUT FORMAT ####} -auto_group, VERSION = "state 0 3 0", DESTINATION = "MEGA1001", BIDIRECTS = "bidir1", REPEAT_THRESHOLD = "5", DESIGN = "testchip6" ; target_file "exp2.swav"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/SWAV/EVCDSWAV/exp1.vtran000064400001440000012000000101321103104161000172440ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > SWAV # # Original File: "exp1.evcd" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} { bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into SWAV format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'SWAV'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; {#### timing info ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; TESTER_FORMAT SWAV {#### OUTPUT FORMAT ####} -auto_group, VERSION = "state 0 3 0", DESTINATION = "MEGA1001", BIDIRECTS = "bidir1", REPEAT_THRESHOLD = "5", DESIGN = "testchip6" ; target_file "exp1.swav"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/SWAV/README000064400001440000012000000256631103104161000147700ustar00jcosleystaff00000400000023SWAV: -------- The main directory is "SWAV" and the sub-directories are -> WGLSWAV -> VCDSWAV -> STILSWAV -> EVCDSWAV -> LSIMSWAV ->SWAVSTIL/ ->SWAVVERILOG/ The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLSWAV" contains the translation of WGL file to SWAV output format. Sub-directory -> "EVCDSWAV" contains the translation of EVCD file to SWAV output format. Sub-directory -> "SWAVSTIL" contains the translation of SWAV file to STIL output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... This directory presents several examples of WGL and STIL to SWAV (Credence) format. There are also examples of LSIM and Verilog VCD to SWAV translation. The SWAV output format is invoked in the TVF_BLOCK with the following command - optional parameters are shown in []: TESTER_FORMAT SWAV [, -ALLOW_WINDOW_COMPARE] { enables output window strobing } [, VERSION = "version string"] [, DESTINATION = "tester"] { the tester name } [, SCANIN_DEFAULT = "state"] { any input 'X' is mapped to this } [, BIDIRECTS = "bidir1"] { specifies single column bidirs } [, DESIGN = "name"] { used in header } [, DATE = "date"] { specifies date of file creation } [, SOURCE = "name"] { name of source } [, DESIGNER = "name"] { name of designer } [, TIMESCALE = "ns"] { timescale - defaults to ps } [, SIGNAL_FILE = "filename"] { replace signal section with file } { contents } [, PATTERN_NAME = "name"] { name of pattern } [, CONTROL = "string"] { control string after pattern name } [, TIMESET_FILE = "filename"] { replace timing section with file } { contents } [, MAX_LINE_LENGTH = "nn"] { defines max length of line in tvf } { defaults to 80 characters } [, REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [, TIME_STAMPS = "ON" | "OFF"] { enables/disables timestamps in file } { default is ON } ; The -ALLOW_WINDOW_COMPARE flag directs the output formatter to support window compares. Without this flag, the timing generated in SWAV files for output pins only will accommodate edge compares. Adding this flag to the parameter list for SWAV out will cause the outputs to be window strobed when this is specified in the input file or in a pintype stb statement (by specifying both t1 and t2) in the PROC_BLOCK. The quoted parameter value strings may contain spaces. When using the WGL or STIL reader it should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -cycle flag prevents the WGL/STIL reader from flattening-out timing when the file is being read. The -scan flag tells the reader to maintain the scan data separately, i.e. do not flatten it out. Since the SWAV format supports a scan data structure, we do not want the WGL/STIL reader to flatten it out. Note that for STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is to be scan data translated. The LSIM and Verilog VCD translation examples are basically reading print-on- change files, collapsing them to cycle data, and specifying pin timing for the SWAV file. For the VCD file, the pin directions must also be specified along with logic to separate input from output data on bidirects. This directory presents several examples of translations to SWAV format. The SWAV output format is invoked in the TVF_BLOCK of the command file with the following command : begin target_file "exp3.swav"; {#### OUTPUT VECTOR FILE ####} tester_format swav ; {#### OUTPUT FORMAT ####} end; The vectors and timing information are both contained in the "exp3.swav". An example command file for an WGL -> SWAV translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > SWAV # # Original File: "exp3.wgl" # # Target File: "exp3.swav " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp3.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into SWAV format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'SWAV'#### } state_trans '-'->'X'; state_trans 'P'->'^'; state_trans outputs '0'->'L', '1'->'H'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp3.swav"; {#### OUTPUT VECTOR FILE ####} tester_format swav ; {#### OUTPUT FORMAT ####} end; end; ################################################################################ Beginning with vtran release 7.0, a number of the tester output interface options include a canned reader which is specifically designed to read the vtran-generated tester files and translate these directly to a Verilog or VHDL testbench (or actually any flat format). These canned readers are "Read-Back" modules which provide a direct way to verify the tester files, thru testbench re-simulation, prior to trying them on the tester. Note that these Read-Back modules support only the subset of the tester syntax used by vtran when generating the test programs and only support a flat translation, thus they are not intended for use as a general-purpose translation tool for the tester languages. The SWAV tester canned reader optionally will generate cyclized output formats. This reader still supports only the subset of tester syntax used by vtran when generating the test programs. This tester canned reader has several options that allow the user to control whether scan vectors, single-vector repeats, and loops are retained or flattened in the output format, when cycle-based output is selected. The vtran command files for using the canned reader module to create cycle-based output formats are typically quite simple, as illustrated below. The vtran command files for using the Read-Back module to create a verification testbench are typically quite simple, as illustrated below. An example command file for an SWAV -> VERILOG TEST BENCH translation would look like: ovf_block begin; orig_file "exp1.swav"; {#### INPUT VECTOR FILE ####} tabular_format SWAV ; {#### INPUT FORMAT ####} end; proc_block begin; { #### state character translations for 'SWAV'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; tvf_block begin; { rename_bus_pins $bus_$vec; } simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; The timing, vectors, and Scan data are in the "exp1.swav" file, a vtran-generated file required by the reader. The SWAV Reader optionally will generate cycle-based timing and vectors. To select this feature, include the flag "-cycle" with the tabular_format command in the OVF_BLOCK of the Vtran command file. The Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that cycle-based output must be selected to enable the Scan option. The Reader, by default, will not flatten loops and repeated vectors if cycle-based output is selected. To disable this feature, include the flag "-expand_loops" and/or "-expand_reps" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that if cycle-based output is not selected, loops and repeated vectors will be flattened. Example 1: ovf_block begin; orig_file "exp1.swav"; tabular_format swav -cycle; end; In this case, Vtran will read the SWAV source file and create cycle-based data for the Target files. Loops and repeated vectors will be available for inclusion in the Target files. Example 2: ovf_block begin; orig_file "exp1.swav"; tabular_format swav -cycle -scan -expand_loops; end; In this case, Vtran will read the SWAV source file and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files, as will repeated vectors. Loops will be flattened. Example 3: ovf_block begin; orig_file "exp1.swav"; tabular_format swav -cycle -scan -expand_loops -expand_reps; end; In this case, Vtran will read the SWAV source file and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files. Loops and repeated vectors will be flattened. An example command file for a SWAV->STIL translation might look like: ovf_block begin; orig_file "exp1.tp"; tabular_format SWAV -cycle -scan; end; proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; tvf_block begin; resolution = 0.1; { rename_bus_pins $bus_$vec; } simulator stil scanin_condition = "0"; target_file "exp1.stil"; end; { #======================================================================# INTERFACES/SWAV/SWAVSTIL/000075500001440000012000000000001103104161000153505ustar00jcosleystaff00000400000023INTERFACES/SWAV/SWAVSTIL/cyc2.vtran000064400001440000012000000045661103104161000172770ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Credence SWAV # # translating to STIL. # # Translation: SWAV < to > STIL # # Original File: "cyc1.swav" # # Target File: "cyc2.stil " # # Command File: "cyc2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.swav"; {#### INPUT VECTOR FILE ####} tabular_format swav -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the SWAV # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'SWAV'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/SWAV/SWAVSTIL/scan1.tp000064400001440000012000000121361103104161000167250ustar00jcosleystaff00000400000023timescale ns; signal "clk" input { testchannel = "1"; pin = "1"; } signal "pllclk_ext" input { testchannel = "2"; pin = "2"; } signal "pllclk_tm" input { testchannel = "3"; pin = "3"; } signal "reset" input { testchannel = "4"; pin = "4"; } signal "address_i[5]" input { testchannel = "5"; pin = "5"; } signal "address_i[4]" input { testchannel = "6"; pin = "6"; } signal "address_i[3]" input { testchannel = "7"; pin = "7"; } signal "address_i[2]" input { testchannel = "8"; pin = "8"; } signal "address_i[1]" input { testchannel = "9"; pin = "9"; } signal "address_i[0]" input, scan_input { testchannel = "10"; pin = "10"; } signal "cmd_i[2]" input { testchannel = "11"; pin = "11"; } signal "cmd_i[1]" input { testchannel = "12"; pin = "12"; } signal "cmd_i[0]" input { testchannel = "13"; pin = "13"; } signal "tm_i" input { testchannel = "14"; pin = "14"; } signal "tsi2" input, scan_input { testchannel = "15"; pin = "15"; } signal "tms" input { testchannel = "16"; pin = "16"; } signal "tck" input { testchannel = "17"; pin = "17"; } signal "tdi" input { testchannel = "18"; pin = "18"; } signal "trst" input { testchannel = "19"; pin = "19"; } signal "test_se" input { testchannel = "20"; pin = "20"; } signal "tdo" output { testchannel = "21"; pin = "21"; } signal "carry_o" output { testchannel = "22"; pin = "22"; } signal "error_o" output, scan_output { testchannel = "23"; pin = "23"; } signal "error_pll" output { testchannel = "24"; pin = "24"; } signal "mux_o" output { testchannel = "25"; pin = "25"; } signal "tso2" output, scan_output { testchannel = "26"; pin = "26"; } signal "data[7]" bidir1 { testchannel = "27"; pin = "27"; } signal "data[6]" bidir1 { testchannel = "28"; pin = "28"; } signal "data[5]" bidir1 { testchannel = "29"; pin = "29"; } signal "data[4]" bidir1 { testchannel = "30"; pin = "30"; } signal "data[3]" bidir1 { testchannel = "31"; pin = "31"; } signal "data[2]" bidir1 { testchannel = "32"; pin = "32"; } signal "data[1]" bidir1 { testchannel = "33"; pin = "33"; } signal "data[0]" bidir1 { testchannel = "34"; pin = "34"; } set ts0 { period 30 ; apply "clk" { force { format RZ; start 10; stop 20; } } apply "pllclk_ext" { force { format RZ; start 14; stop 16; } } apply "pllclk_tm" { force { format NRZ; start 0; } } apply "reset" { force { format NRZ; start 0; } } apply "address_i[5]" { force { format NRZ; start 0; } } apply "address_i[4]" { force { format NRZ; start 0; } } apply "address_i[3]" { force { format NRZ; start 0; } } apply "address_i[2]" { force { format NRZ; start 0; } } apply "address_i[1]" { force { format NRZ; start 0; } } apply "address_i[0]" { force { format NRZ; start 0; } } apply "cmd_i[2]" { force { format NRZ; start 0; } } apply "cmd_i[1]" { force { format NRZ; start 0; } } apply "cmd_i[0]" { force { format NRZ; start 0; } } apply "tm_i" { force { format NRZ; start 0; } } apply "tsi2" { force { format NRZ; start 0; } } apply "tms" { force { format NRZ; start 0; } } apply "tck" { force { format RZ; start 14; stop 16; } } apply "tdi" { force { format NRZ; start 0; } } apply "trst" { force { format NRZ; start 0; } } apply "test_se" { force { format NRZ; start 0; } } apply "tdo" { sense { start 29; } } apply "carry_o" { sense { start 29; } } apply "error_o" { sense { start 29; } } apply "error_pll" { sense { start 29; } } apply "mux_o" { sense { start 29; } } apply "tso2" { sense { start 29; } } apply "data[7]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[6]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[5]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[4]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[3]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[2]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[1]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[0]" { force { format NRZ; start 0; } sense { start 29; } } } pattern: 00XXXXXXXXXXXXXX0XXXXXXXXXZZZZZZZZ > ts0 ; /* 0 */ 0010XXXXXX1001X10X0XXXXXXXZZZZZZZZ ; /* 30 */ scan_start: 1110XXXXX01001010X11XXXXXXZZZZZZZZ ; /* 60 */ scan_data "address_i[0]"; 11001100110011001100110011001100110011001100110011001100110011001100110011001100 1100110011001100110011001; scan_data "tsi2"; XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXX1001100110011001; scan_end; 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3210 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3240 */ 0010XXXXXX1001X10X11XXLXXHZZZZZZZZ ; /* 3270 */ scan_start: 1110XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3300 */ scan_data "error_o"; LHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHL LHHLLHHLLHHLLHHLLHHLLHHLX; scan_data "tso2"; LLHHLLHHLLHHLLHXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXX; scan_end; 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6450 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6480 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6510 */ pattern_end; INTERFACES/SWAV/SWAVSTIL/scan1.vtran000064400001440000012000000046121103104161000174340ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back SWAV translating to # # STIL. # # Translation: SWAV < to > STIL # # Original File: "scan1.tp" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "scan1.tp"; {#### INPUT VECTOR FILE ####} tabular_format SWAV -cycle -scan; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the SWAV # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; resolution = 0.1; { #### .1ns resolution for times #### } { rename_bus_pins $bus_$vec; } simulator stil {#### OUTPUT FORMAT ####} scanin_condition = "0"; target_file "scan1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/SWAV/SWAVSTIL/cyc1.vtran000064400001440000012000000047271103104161000172750ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Credence SWAV # # translating to STIL. # # Translation: SWAV < to > STIL # # Original File: "cyc1.swav" # # Target File: "cyc1.stil " # # Command File: "cyc1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.swav"; {#### INPUT VECTOR FILE ####} tabular_format swav -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the SWAV # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'SWAV'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc1.stil"; {#### OUTPUT VECTOR FILE ####} end; #INTERFACES/SWAV/SWAVSTIL/cyc1.swav000064400001440000012000000104521103104161000171130ustar00jcosleystaff00000400000023timescale ns; signal "out0" output { testchannel = "1"; pin = "1"; } signal "out1" output { testchannel = "2"; pin = "2"; } signal "out2" output { testchannel = "3"; pin = "3"; } signal "in0" input { testchannel = "4"; pin = "4"; } signal "in1" input { testchannel = "5"; pin = "5"; } signal "in2" input { testchannel = "6"; pin = "6"; } signal "clk1" input { testchannel = "7"; pin = "7"; } signal "clk2" input { testchannel = "8"; pin = "8"; } signal "SDI0" input, scan_input { testchannel = "9"; pin = "9"; } signal "SDI1" input, scan_input { testchannel = "10"; pin = "10"; } signal "SDO0" output, scan_output { testchannel = "11"; pin = "11"; } signal "SDO1" output, scan_output { testchannel = "12"; pin = "12"; } signal "ACK0" input { testchannel = "13"; pin = "13"; } signal "BCK0" input { testchannel = "14"; pin = "14"; } set ts0 { period 90 ; apply "out0" { sense { start 10; } } apply "out1" { sense { start 10; } } apply "out2" { sense { start 10; } } apply "in0" { force { format NRZ; start 0; } } apply "in1" { force { format NRZ; start 0; } } apply "in2" { force { format NRZ; start 0; } } apply "clk1" { force { format RZ; start 70; stop 80; } } apply "clk2" { force { format RZ; start 70; stop 80; } } apply "SDI0" { force { format NRZ; start 0; } } apply "SDI1" { force { format NRZ; start 0; } } apply "SDO0" { sense { start 10; } } apply "SDO1" { sense { start 10; } } apply "ACK0" { force { format RZ; start 20; stop 30; } } apply "BCK0" { force { format RZ; start 60; stop 70; } } } set ts1 { period 90 ; apply "out0" { sense { start 10; } } apply "out1" { sense { start 10; } } apply "out2" { sense { start 10; } } apply "in0" { force { format NRZ; start 0; } } apply "in1" { force { format NRZ; start 0; } } apply "in2" { force { format NRZ; start 0; } } apply "clk1" { force { format RZ; start 70; stop 80; } } apply "clk2" { force { format RZ; start 70; stop 80; } } apply "SDI0" { force { format NRZ; start 0; } } apply "SDI1" { force { format NRZ; start 0; } } apply "SDO0" { sense { start 10; } } apply "SDO1" { sense { start 10; } } apply "ACK0" { force { format RZ; start 20; stop 30; } } apply "BCK0" { force { format RZ; start 60; stop 70; } } } set ts2 { period 110 ; apply "out0" { sense { start 10; } } apply "out1" { sense { start 10; } } apply "out2" { sense { start 10; } } apply "in0" { force { format NRZ; start 0; } } apply "in1" { force { format NRZ; start 0; } } apply "in2" { force { format NRZ; start 0; } } apply "clk1" { force { format RZ; start 20; stop 30; } } apply "clk2" { force { format RZ; start 20; stop 30; } } apply "SDI0" { force { format NRZ; start 0; } } apply "SDI1" { force { format NRZ; start 0; } } apply "SDO0" { sense { start 10; } } apply "SDO1" { sense { start 10; } } apply "ACK0" { force { format RZ; start 20; stop 30; } } apply "BCK0" { force { format RZ; start 60; stop 70; } } } set ts3 { period 100 ; apply "out0" { sense { start 10; } } apply "out1" { sense { start 10; } } apply "out2" { sense { start 10; } } apply "in0" { force { format NRZ; start 0; } } apply "in1" { force { format NRZ; start 0; } } apply "in2" { force { format NRZ; start 0; } } apply "clk1" { force { format RZ; start 50; stop 80; } } apply "clk2" { force { format RZ; start 50; stop 80; } } apply "SDI0" { force { format NRZ; start 0; } } apply "SDI1" { force { format NRZ; start 0; } } apply "SDO0" { sense { start 10; } } apply "SDO1" { sense { start 10; } } apply "ACK0" { force { format RZ; start 20; stop 30; } } apply "BCK0" { force { format RZ; start 60; stop 70; } } } pattern: XXXXXX00XXXX00 > ts3 cy3 ; /* 0 */ scan_start: XXXXXX0000XX11 ; /* 100 */ scan_data "SDI0"; 0010; scan_data "SDO0"; XXXX; scan_data "SDI1"; 0001; scan_data "SDO1"; XXXX; scan_end; XXX0100011XX00 ; /* 500 */ XXX1000010XX00 > ts0 cy0 ; /* 600 */ loop 12; XXXXXX00XXXX01 > ts3 cy3 ; /* 690 */ endloop; XXXXXX11XXXX00 ; /* 1890 */ loop 5; XXXXXX01XXXX01 ; /* 1990 */ XXXXXX10XXXX01 ; /* 2090 */ endloop; XXXXXX01XXXX01 ; /* 2990 */ scan_start: XXX1000000XX11 ; /* 3090 */ scan_data "SDI0"; 0000; scan_data "SDO0"; XXHL; scan_data "SDI1"; 0000; scan_data "SDO1"; XXXX; scan_end; XXXXXX01XXXX11 ; /* 3490 */ XXXXXX01XXXX00 ; /* 3590 */ pattern_end; INTERFACES/SWAV/SWAVVERILOG/000075500001440000012000000000001103104161000157045ustar00jcosleystaff00000400000023INTERFACES/SWAV/SWAVVERILOG/exp1.vtran000064400001440000012000000051151103104161000176370ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back SWAV translating to # # verilog testbench. # # Translation: SWAV < to > VERILOG TEST BENCH # # Original File: "exp1.tp" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} tabular_format SWAV ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the SWAV # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'SWAV'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/SWAV/SWAVVERILOG/exp1.tp000064400001440000012000000121361103104161000171310ustar00jcosleystaff00000400000023timescale ns; signal "clk" input { testchannel = "1"; pin = "1"; } signal "pllclk_ext" input { testchannel = "2"; pin = "2"; } signal "pllclk_tm" input { testchannel = "3"; pin = "3"; } signal "reset" input { testchannel = "4"; pin = "4"; } signal "address_i[5]" input { testchannel = "5"; pin = "5"; } signal "address_i[4]" input { testchannel = "6"; pin = "6"; } signal "address_i[3]" input { testchannel = "7"; pin = "7"; } signal "address_i[2]" input { testchannel = "8"; pin = "8"; } signal "address_i[1]" input { testchannel = "9"; pin = "9"; } signal "address_i[0]" input, scan_input { testchannel = "10"; pin = "10"; } signal "cmd_i[2]" input { testchannel = "11"; pin = "11"; } signal "cmd_i[1]" input { testchannel = "12"; pin = "12"; } signal "cmd_i[0]" input { testchannel = "13"; pin = "13"; } signal "tm_i" input { testchannel = "14"; pin = "14"; } signal "tsi2" input, scan_input { testchannel = "15"; pin = "15"; } signal "tms" input { testchannel = "16"; pin = "16"; } signal "tck" input { testchannel = "17"; pin = "17"; } signal "tdi" input { testchannel = "18"; pin = "18"; } signal "trst" input { testchannel = "19"; pin = "19"; } signal "test_se" input { testchannel = "20"; pin = "20"; } signal "tdo" output { testchannel = "21"; pin = "21"; } signal "carry_o" output { testchannel = "22"; pin = "22"; } signal "error_o" output, scan_output { testchannel = "23"; pin = "23"; } signal "error_pll" output { testchannel = "24"; pin = "24"; } signal "mux_o" output { testchannel = "25"; pin = "25"; } signal "tso2" output, scan_output { testchannel = "26"; pin = "26"; } signal "data[7]" bidir1 { testchannel = "27"; pin = "27"; } signal "data[6]" bidir1 { testchannel = "28"; pin = "28"; } signal "data[5]" bidir1 { testchannel = "29"; pin = "29"; } signal "data[4]" bidir1 { testchannel = "30"; pin = "30"; } signal "data[3]" bidir1 { testchannel = "31"; pin = "31"; } signal "data[2]" bidir1 { testchannel = "32"; pin = "32"; } signal "data[1]" bidir1 { testchannel = "33"; pin = "33"; } signal "data[0]" bidir1 { testchannel = "34"; pin = "34"; } set ts0 { period 30 ; apply "clk" { force { format RZ; start 10; stop 20; } } apply "pllclk_ext" { force { format RZ; start 14; stop 16; } } apply "pllclk_tm" { force { format NRZ; start 0; } } apply "reset" { force { format NRZ; start 0; } } apply "address_i[5]" { force { format NRZ; start 0; } } apply "address_i[4]" { force { format NRZ; start 0; } } apply "address_i[3]" { force { format NRZ; start 0; } } apply "address_i[2]" { force { format NRZ; start 0; } } apply "address_i[1]" { force { format NRZ; start 0; } } apply "address_i[0]" { force { format NRZ; start 0; } } apply "cmd_i[2]" { force { format NRZ; start 0; } } apply "cmd_i[1]" { force { format NRZ; start 0; } } apply "cmd_i[0]" { force { format NRZ; start 0; } } apply "tm_i" { force { format NRZ; start 0; } } apply "tsi2" { force { format NRZ; start 0; } } apply "tms" { force { format NRZ; start 0; } } apply "tck" { force { format RZ; start 14; stop 16; } } apply "tdi" { force { format NRZ; start 0; } } apply "trst" { force { format NRZ; start 0; } } apply "test_se" { force { format NRZ; start 0; } } apply "tdo" { sense { start 29; } } apply "carry_o" { sense { start 29; } } apply "error_o" { sense { start 29; } } apply "error_pll" { sense { start 29; } } apply "mux_o" { sense { start 29; } } apply "tso2" { sense { start 29; } } apply "data[7]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[6]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[5]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[4]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[3]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[2]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[1]" { force { format NRZ; start 0; } sense { start 29; } } apply "data[0]" { force { format NRZ; start 0; } sense { start 29; } } } pattern: 00XXXXXXXXXXXXXX0XXXXXXXXXZZZZZZZZ > ts0 ; /* 0 */ 0010XXXXXX1001X10X0XXXXXXXZZZZZZZZ ; /* 30 */ scan_start: 1110XXXXX01001010X11XXXXXXZZZZZZZZ ; /* 60 */ scan_data "address_i[0]"; 11001100110011001100110011001100110011001100110011001100110011001100110011001100 1100110011001100110011001; scan_data "tsi2"; XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXX1001100110011001; scan_end; 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3210 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3240 */ 0010XXXXXX1001X10X11XXLXXHZZZZZZZZ ; /* 3270 */ scan_start: 1110XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 3300 */ scan_data "error_o"; LHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHL LHHLLHHLLHHLLHHLLHHLLHHLX; scan_data "tso2"; LLHHLLHHLLHHLLHXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXX; scan_end; 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6450 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6480 */ 0010XXXXXX1001X10X11XXXXXXZZZZZZZZ ; /* 6510 */ pattern_end; INTERFACES/SWAV/VCDSWAV/000075500001440000012000000000001103104161000152115ustar00jcosleystaff00000400000023INTERFACES/SWAV/VCDSWAV/exp1.vtran000064400001440000012000000177611103104161000171560ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD(Print-on-change) < to > SWAV # # Original File: "exp1A.vcd" # # Target File: "exp1.swav " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ################################################################### The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. #####################################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,,S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS ,,S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,,L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,,T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,,S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; INPUTS ,,SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,,S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into SWAV format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'SWAV'#### } STATE_TRANS inputs 'x'->'X', 'z'->'X' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'Z', 'z'->'Z' ; { ##################################################################### In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. ####################################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { ########################################################################## The vector data in the VCD file is in a print-on-change format. The vector data for the SWAV file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, strobing all pure input signals and all output signals at 49 nS into the 50 nS cycle, but strobing bidirectional inputs at 10 nS into the cycle ###########################################################################} CYCLE = 50; ALIGN_TO_CYCLE 50 PURE_INPUTS @ 49, BIDIR_INPUTS @ 10, ALL_OUTPUTS @ 49 ; { ####################################################################### Now we can define some timing for the Credence file since the VCD file does not contain this info separately and we just removed all cycle timing with the ALIGN_TO_CYCLE process above ######################################################################## } ADD_PIN HECS_CLK = 1; { add clock pin - not necessary if already in data } PINTYPE NRZ * @ 5; { drive all inputs at 5 } PINTYPE STB * @ 45; { strobe all outputs at 45 } PINTYPE RZ HECS_CLK @ 20, 30; { clock pin behavior } SEPARATE_TIMING; { necessary for cycle-based formats } DISABLE_VECTOR_FILTER; { necessary for cycle-based formats } END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN TESTER_FORMAT SWAV {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "MEGA1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", REPEAT_THRESHOLD = "5", DESIGN = "testchip14" ; TARGET_FILE "exp1.swav"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/SWAV/VCDSWAV/exp2.vtran000064400001440000012000000160441103104161000171500ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD(Print-on-change) < to > SWAV # # Original File: "exp1A.vcd" # # Target File: "exp2.swav " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ################################################################### The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. #####################################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,,S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS ,,S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,,L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,,T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,,S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; INPUTS ,,SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,,S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into SWAV format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'SWAV'#### } STATE_TRANS inputs 'x'->'X', 'z'->'X' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'Z', 'z'->'Z' ; { ##################################################################### In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. ####################################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { ####################################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the SWAV file needs to be in cycle-based format. Now we can define some timing for the Credence file since the VCD file does not contain this info separately. ######################################################################## } Include "../../DATA/exp1A.tcyc" SEPARATE_TIMING; { necessary for cycle-based formats } DISABLE_VECTOR_FILTER; { necessary for cycle-based formats } END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN TESTER_FORMAT SWAV {#### OUTPUT FORMAT ####} VERSION = "state 0 3 0", DESTINATION = "MEGA1001", SCANIN_DEFAULT = "0", BIDIRECTS = "bidir1", REPEAT_THRESHOLD = "5", DESIGN = "testchip14" ; TARGET_FILE "exp2.swav"; {#### OUTPUT VECTOR FILE ####} END; _CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,,L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2INTERFACES/TDL91/000075500001440000012000000000001103104161000141115ustar00jcosleystaff00000400000023INTERFACES/TDL91/WGLTDL91/000075500001440000012000000000001103104161000152605ustar00jcosleystaff00000400000023INTERFACES/TDL91/WGLTDL91/exp2.vtran000064400001440000012000000050311103104161000172110ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDL91 # # Original File: "exp1.wgl" # # Target File: "exp2.tdl" # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TDL91'#### } state_trans 'P'->'.'; state_trans inputs '0'->'L', '1'->'H', 'X'->'Y' '-'->'Y'; state_trans outputs 'N'->'M', 'x'->'M', 'X'->'M', '-'->'M'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin merge_bidirects 10HLZXMY; target_file "exp2.tdl"; {#### OUTPUT VECTOR FILE ####} simulator tdl_91 -AUTO_GROUP, {#### OUTPUT FORMAT ####} LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; end; end; INTERFACES/TDL91/WGLTDL91/exp1.vtran000064400001440000012000000051751103104161000172210ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDL91 # # Original File: "exp1.wgl" # # Target File: "exp1.tdl" # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TDL91'#### } state_trans 'P'->'.'; state_trans inputs '0'->'L', '1'->'H', 'X'->'Y' '-'->'Y'; state_trans outputs 'N'->'M', 'x'->'M', 'X'->'M', '-'->'M'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin merge_bidirects 10HLZXMY; target_file "exp1.tdl"; {#### OUTPUT VECTOR FILE ####} simulator tdl_91 -AUTO_GROUP, {#### OUTPUT FORMAT ####} LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; end; end; # # Translation: WGL < to > TDL91 # # Original File: "exp1.wgl" # # Target File: "exp1.tdl" # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" #INTERFACES/TDL91/WGLTDL91/exp3.vtran000064400001440000012000000050371103104161000172200ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDL91 # # Original File: "exp1.wgl" # # Target File: "exp3.tdl" # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TDL91'#### } state_trans 'P'->'.'; state_trans inputs '0'->'L', '1'->'H', 'X'->'Y' '-'->'Y'; state_trans outputs 'N'->'M', 'x'->'M', 'X'->'M', '-'->'M'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin merge_bidirects 10HLZXMY; target_file "exp3.tdl"; {#### OUTPUT VECTOR FILE ####} simulator tdl_91 -AUTO_GROUP, {#### OUTPUT FORMAT ####} LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; end; end; INTERFACES/TDL91/VCDTDL91/000075500001440000012000000000001103104161000152435ustar00jcosleystaff00000400000023INTERFACES/TDL91/VCDTDL91/exp2.vtran000064400001440000012000000150541103104161000172020ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > TDL91 # # Original File: "exp1A.vcd" # # Target File: "exp2.tdl91 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} {############################################################## The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. #################################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,, S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,, L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,, T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,, S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS ,, SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,, S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into TDL91 format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'TDL91'#### } STATE_TRANS inputs 'x'->'Y', 'z'->'Y', '1'->'H', '0'->'L' ; STATE_TRANS outputs 'x'->'M', 'z'->'Z' ; { ################################################################ In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. #################################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { ####################################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the TDL_91 file needs to be in cycle-based format. Now we can define some timing for the TDL_91 file since the VCD file does not contain this info separately. ########################################################################} Include "../../DATA/exp1A.tcyc" SEPARATE_TIMING; END; TVF_BLOCK BEGIN SIMULATOR TDL_91 REPEAT_THRESHOLD = "5", LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; TARGET_FILE "exp2.tdl"; END; #######} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,, S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDIINTERFACES/TDL91/VCDTDL91/exp1.vtran000064400001440000012000000170361103104161000172030ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > TDL91 # # Original File: "exp1A.vcd" # # Target File: "exp1.tdl91 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} {############################################################## The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. #################################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,, S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,, L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,, T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,, S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS ,, SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,, S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into TDL91 format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'TDL91'#### } STATE_TRANS inputs 'x'->'Y', 'z'->'Y', '1'->'H', '0'->'L' ; STATE_TRANS outputs 'x'->'M', 'z'->'Z' ; { ################################################################ In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. #################################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { #################################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the TDL_91 file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, strobing all pure input signals and all output signals at 49 nS into the 50 nS cycle, but strobing bidirectional inputs at 10 nS into the cycle #######################################################################} CYCLE = 50; ALIGN_TO_CYCLE 50 PURE_INPUTS @ 49, BIDIR_INPUTS @ 10, ALL_OUTPUTS @ 49 ; { ####################################################################### Now we can define some timing for the TDL_91 file since the VCD file does not contain this info separately and we just removed all cycle timing with the ALIGN_TO_CYCLE process above ########################################################################} ADD_PIN HECS_CLK = 1; { #### add clock pin - not necessary if already in data #### } PINTYPE NRZ * @ 5; { #### drive all inputs at 5 #### } PINTYPE STB * @ 45; { #### strobe all outputs at 45 #### } PINTYPE RZ HECS_CLK @ 20, 30; { #### clock pin behavior #### } SEPARATE_TIMING; END; TVF_BLOCK BEGIN SIMULATOR TDL_91 REPEAT_THRESHOLD = "5", LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; TARGET_FILE "exp1.tdl"; END; ===========================================# # This is vtran command file. # # Translation: VCD < to > TDL91 # # Original File: "exp1A.vcd" # # Target File: "exp1.tdl91 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" #INTERFACES/TDL91/STILTDL91/000075500001440000012000000000001103104161000154025ustar00jcosleystaff00000400000023INTERFACES/TDL91/STILTDL91/exp2.vtran000064400001440000012000000047661103104161000173510ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TDL91 # # Original File: "exp1.stil" # # Target File: "exp2.tdl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil {#### INPUT FORMAT ####} -CYCLE -INCLUDE_CELLS ; orig_file = "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'TDL91'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'L', 'U'->'H', '?'->'Y', 'Z'->'Y'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'M', 'x'->'M', 'X'->'M', 'l'->'0', 'h'->'1', 't'->'M', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'Y'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block header 9999; comments on; merge_bidirects 10HLMZXY; simulator tdl_91; {#### OUTPUT FORMAT ####} target_file = "exp2.tdl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TDL91/STILTDL91/exp1.vtran000064400001440000012000000051411103104161000173340ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TDL91 # # Original File: "exp1.stil" # # Target File: "exp1.tdl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil {#### INPUT FORMAT ####} -CYCLE -EXPAND_LOOPS -EXPAND_REPS -INCLUDE_CELLS ; orig_file = "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'TDL91'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'L', 'U'->'H', '?'->'Y', 'Z'->'Y'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'M', 'x'->'M', 'X'->'M', 'l'->'0', 'h'->'1', 't'->'M', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'Y'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block header 9999; comments on; merge_bidirects 10HLMZXY; simulator tdl_91; {#### OUTPUT FORMAT ####} target_file = "exp1.tdl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TDL91/STILTDL91/exp3.vtran000064400001440000012000000050061103104161000173360ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TDL91 # # Original File: "exp1.stil" # # Target File: "exp3.tdl " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil {#### INPUT FORMAT ####} -CYCLE -SCAN -INCLUDE_CELLS ; orig_file = "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'TDL91'#### } state_trans 'P'->'^'; state_trans inputs 'D'->'L', 'U'->'H', '?'->'Y', 'Z'->'Y'; state_trans outputs 'L'->'0', 'H'->'1', 'T'->'M', 'x'->'M', 'X'->'M', 'l'->'0', 'h'->'1', 't'->'M', 'R'->'0', 'G'->'1', 'Q'->'Z', '?'->'Y'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block header 9999; comments on; merge_bidirects 10HLMZXY; simulator tdl_91; {#### OUTPUT FORMAT ####} target_file = "exp3.tdl"; {#### OUTPUT VECTOR FILE ####} end; end; thor: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================#INTERFACES/TDL91/EVCDTDL91/000075500001440000012000000000001103104161000153505ustar00jcosleystaff00000400000023INTERFACES/TDL91/EVCDTDL91/exp1.vtran000064400001440000012000000100451103104161000173010ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > TDL91 # # Original File: "exp1.evcd" # # Target File: "exp1.tdl91 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'TDL91' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR TDL_91 REPEAT_THRESHOLD = "5", LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; TARGET_FILE "exp1.tdl"; END; INTERFACES/TDL91/EVCDTDL91/exp2.vtran000064400001440000012000000074521103104161000173120ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > TDL91 # # Original File: "exp1.evcd" # # Target File: "exp2.tdl91 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'TDL91' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR TDL_91 REPEAT_THRESHOLD = "5", LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; TARGET_FILE "exp2.tdl"; END; # # This block provides information about the input file and # # input format. # #======================================================================#INTERFACES/TDL91/README000064400001440000012000000135261103104161000150000ustar00jcosleystaff00000400000023TDL91 -------- The main directory is "TDL91" and the sub-directories are -> WGLTDL91 -> VCDTDL91 -> STILTDL91 -> EVCDTDL91 The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLTDL91" contains the translation of WGL file to TDL91 output format. Sub-directory -> "EVCDTDL91" contains the translation of EVCD file to TDL91 output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The TDL_91 output format is invokde in the TVF_BLOCK with the following command - optional parameters are shown in []: TESTER_FORMAT TDL_91 [, -AUTO_GROUP] { causes pin grouping by algorithm } [, -IDDQ] { looks for TMAX {measureIDDQ} } [, LIBRARY_TYPE = "string"] [, CUSTOMER = "name"] [, TI_PART_NUMBER = "partno"] [, PATTERN_SET_NAME = "name"] [, PATTERN_SET_TYPE = "type"] [, PATTERN_SET_DESCRIPTION = "description"] [, REVISION = "revision"] [, SCANIN_DEFAULT="X"] { sets scan-in padding state } [, DATE = "date"] { "'date" gives today's date } [, SD_PORT = "portname"] [, UNITS = "NS"] { defaults to NS } [, MAX_LINE_LENGTH = "nn"] { defines max length of line in tvf } { defaults to 80 characters } [, REPEAT_THRESHOLD = "nn"] { sets # of identical vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [, TIME_STAMPS = "ON" | "OFF"] { enables/disables timestamps in file } { default is ON } ; The -IDDQ flag should be used with a -KEEP_ANNOTATIONS flag in the TABULAR_FORMAT command (only with WGL). This is designed to detect {measureIDDQ} annotations from TetraMAX and mapping it to ASIC_TEST statements in the TDL_91 file. The quoted parameter value strings may contain spaces. The SD_PORT parameter provides a way to add the scan cell scan-in port name (hierarchically) to the scan cell name. An example would be: SD_PORT = ".SD", With this parameter, all scan cell names would have a ".SD" port name suffix appended for the TDL_91 format. Vtran will also map all '/' characters in hierarchical cell names to '.' . When using the WGL or STIL reader it should be invoked in the OVF_BLOCK with ([] means optional): tabular_format WGL -cycle, -scan -include_cells [-keep_annotations] [TDL91_INFO] ; or tabular_format STIL -cycle, -scan -include_cells [-TDL91_INFO]; The -cycle flag prevents the readers from flattening-out timing when the file is being read. The -scan flag tells the reader to maintain the scan data separately, i.e. do not flatten it out. Since the TDL_91 format supports a scan data structure, we do not want these readers to flatten it out. The -include_cells should be used if you want the TDL_91 format to include the cells (VAR) and polarity (CONFIG) information in the PATH block for parallel scan loading. For WGL or STIL files generated by recent versions of TetraMAX (Synopsys), the -TDL91_INFO flag can be specified which tells vtran to look for header information at the beginning of the file and pass it thru to the TDL_91 output file. An example command file for a WGL -> TDL91 translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDL91 # # Original File: "exp1.wgl" # # Target File: "exp1.tdl" # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan -include_cells; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDL91 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TDL91'#### } state_trans 'P'->'.'; state_trans inputs '0'->'L', '1'->'H', 'X'->'Y' '-'->'Y'; state_trans outputs 'N'->'M', 'x'->'M', 'X'->'M', '-'->'M'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin merge_bidirects 10HLZXMY; target_file "exp1.tdl"; {#### OUTPUT VECTOR FILE ####} simulator tdl_91, {#### OUTPUT FORMAT ####} LIBRARY_TYPE = "TGC100", CUSTOMER = "Seagate", TI_PART_NUMBER = "HC1005", PATTERN_SET_NAME = "TC_SYN_1", PATTERN_SET_TYPE = "SCANCHK", REVISION = "1.10", DATE = "2/15/99" ; end; end; ################################################################################ INTERFACES/TDX/000075500001440000012000000000001103104161000137535ustar00jcosleystaff00000400000023INTERFACES/TDX/WGLTDX/000075500001440000012000000000001103104161000147645ustar00jcosleystaff00000400000023INTERFACES/TDX/WGLTDX/exp5.wgl000064400001440000012000000006461103104161000163660ustar00jcosleystaff00000400000023waveform xxx signal data[7 .. 0] : input radix binary; end pattern memCheck (data) diagonal_fill(0); diagonal_fill(1); diagonal_fill(z); diagonal_fill(x); end macro diagonal_fill (s) vector(+) : [0000000@s]; vector(+) : [000000@s0]; vector(+) : [00000@s00]; vector(+) : [0000@s000]; vector(+) : [000@s0000]; vector(+) : [00@s00000]; vector(+) : [0@s000000]; vector(+) : [@s0000000]; endmacro end INTERFACES/TDX/WGLTDX/exp4c.wgl000064400001440000012000000020571103104161000165260ustar00jcosleystaff00000400000023#___________________________________________________________________________ # file: exp4c.wgl #___________________________________________________________________________ # # Here are macros defining read and write cycles in terms of only the data # that changes, in the order that you might want to fill them out. macro readcycle(instr, addr, data16_32, fc0_2, size) vector(+, read) := [- - @addr - - - - - - - - - - @instr ---- @data16_32 ---- - @fc0_2 - - - --- - - - - - @size ]; endmacro macro writecycle(instr, addr, data16_32, fc0_2, size) vector(+, write) := [- - @addr - - - - - - - - - - ---- @instr ---- @data16_32 - @fc0_2 - - - --- - - - - - @size ]; endmacro macro idlecycle vector(+, idle) := [- - -------- - - - - - - - - - - ---- ---- ---- ---- - --- - - - --- - - - - - -- ]; endmacro macro resetcycle vector(+, reset) := [- - -------- - - - - - - - - - - ---- ---- ---- ---- - --- - - - --- - - - - - -- ]; endmacro INTERFACES/TDX/WGLTDX/exp3.vtran000064400001440000012000000042131103104161000167170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDX # # Original File: "exp1.wgl" # # Target File: "exp3.tdx " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDX format # #======================================================================# } proc_block disable_vector_filter; { #### state character translations for 'WGL'->'TDX" #### } state_trans '-'->'X'; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block target_file "exp3.tdx"; {#### OUTPUT VECTOR FILE ####} header 55; simulator tdx; {#### OUTPUT FORMAT ####} end; INTERFACES/TDX/WGLTDX/exp1.vtran000064400001440000012000000043131103104161000167160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDX # # Original File: "exp1.wgl" # # Target File: "exp1.tdx " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDX format # #======================================================================# } proc_block disable_vector_filter; { #### state character translations for 'WGL'->'TDX" #### } state_trans '-'->'X'; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block target_file "exp1.tdx"; {#### OUTPUT VECTOR FILE ####} header 55; simulator tdx; {#### OUTPUT FORMAT ####} end; INTERFACES/TDX/WGLTDX/exp4a.wgl000064400001440000012000000014241103104161000165210ustar00jcosleystaff00000400000023#___________________________________________________________________________ # file: exp4a.wgl #___________________________________________________________________________ signal AS : output; AVEC : input; A[0..31] : output radix hexadecimal; BERR : input; BG : output; BGACK : input; BR : input; CDIS : input; CLK : input; DBEN : output; DS : output; DSACK0 : input; DSACK1 : input; D[0..31] : bidir radix hexadecimal; ECS : output; FC[0..2] : input; HALT : bidir; IPEND : output; IPL[0..2]: input; OCS : output; RESET : bidir; RMC : output; "R/W" : output; SIZ[0..1]: output; # # We divide the data bus up into the instruction and data groups # Inst [D[0..15]] : radix hexadecimal; Data [D[16..31]] : radix hexadecimal; end INTERFACES/TDX/WGLTDX/exp4b.wgl000064400001440000012000000047171103104161000165320ustar00jcosleystaff00000400000023#___________________________________________________________________________ # file: exp4b.wgl #___________________________________________________________________________ timeplate read period 120nS CLK := input[60nS:D, 80nS:U, 20nS:D]; CLK := input[0pS:U, 100nS:D, 40nS:U]; A[0..31] := output[0ps:X, 20nS:Q, 115nS:X]; FC[0..2] := input[0pS:P, 20nS:S]; SIZ[0..1] :=output[0pS:X, 20nS:Q, 115nS:x]; ECS, OCS := output[0pS:X, 8nS:L, 25nS:x]; AS := output[0pS:X, 40nS:L, 100nS:X]; DS := output[0pS:X, 40nS:L, 100nS:X]; "R/W" := output[0pS:X, 10nS:H, 115ns:X]; DSACK0, DSACK1 := input[0pS:U, 70nS:D, 110nS:U]; Inst,Data := bidir[0pS:X, 80nS:S, 130nS:X]; DBEN :=output[0pS:X, 50NS:L, 115nS:X]; BERR, HALT, RESET := input[0pS:U, 80nS:D]; # asynch inputs AVEC, BGACK, BR, CDIS, IPL[0..2] := input[0pS:N, 45nS:D, 75nS:N]; # asynch outputs BG, IPEND, RMC := output[0pS:X]; end timeplate write period 120nS CLK := input[0pS:U, 20nS:D, 40nS:U, 60nS:D, 80nS:U, 100nS:D]; A[0..31] := output[0pS:X, 20nS:Q, 115nS:X]; FC[0..2] := input[0pS:P, 20nS:S]; SIZ[0..1] := output[0pS:X, 20nS:Q, 115nS:X]; ECS, OCS := output[0pS:X, 8nS:L, 25nS:X]; AS := output[0pS:X, 40nS:L, 100nS:X]; DS := output[0pS:X, 60nS:L, 100nS:X]; "R/W" := output[0pS:X, 10nS:L, 115ns:X]; DSACK0, DSACK1 := input[0pS:U, 65nS:D, 110nS:U]; Inst,Data := output[0pS:X, 40ns:Q, 130nS:X]; DBEN := output[0pS:X, 25nS:L, 115nS:X]; BERR, HALT, RESET := input[0pS:U, 80nS:D]; # asynch inputs AVEC, BGACK, BR, CDIS, IPL[0..2] := input[0pS:N, 45nS:D 75nS:N]; # asynch outputs BG, IPEND, RMC := output[0pS:X]; end timeplate idle period 40nS CLK := input[0pS:U, 20nS:D]; A[0..31] := output[0pS:X]; FC[0..2] := input[0pS:P]; SIZ[0..1], ECS, OCS, AS, DS, "R/W" := output[0pS:X]; DSACK0, DSACK1 := input[0pS:U]; Inst,Data := output[0pS:X]; DBEN := output[0pS:X]; BERR, HALT, RESET := input[0pS:U]; # asynch inputs AVEC, BGACK, BR, CDIS, IPL[0..2] := input[0pS:N]; #asynch outputs BG, IPEND, RMC := output[0pS:X]; end timeplate reset period 40nS CLK := input[0pS:U, 20nS:D]; A[0..31] := output[0pS:X]; FC[0..2] := input[0pS:N]; SIZ[0..1], ECS, OCS, AS, DS, "R/W" := output[0pS:X]; DSACK0, DSACK1 := input[0pS:N]; Inst,Data := output[0pS:X]; DBEN := output[0pS:X]; BERR, HALT := input[0pS:N]; RESET := input[0pS:D]; # asynch inputs AVEC, BGACK, BR, CDIS, IPL[0..2] := input[0pS:N]; # asynch outputs BG, IPEND, RMC := output[0pS:X]; end INTERFACES/TDX/WGLTDX/exp4.wgl000064400001440000012000000006231103104161000163600ustar00jcosleystaff00000400000023#___________________________________________________________________________ # file:exp4.wgl #--------------------------------------------------------------------------- # An example showing the use of macros and include files, used to generate # a test for a Test_Chip microprocessor # waveform Test_Chip_test1 include "exp4a.wgl" include "exp4b.wgl" include "exp4c.wgl" include "exp4d.wgl" end INTERFACES/TDX/WGLTDX/exp4d.wgl000064400001440000012000000017061103104161000165270ustar00jcosleystaff00000400000023#--------------------------------------------------------------------------- # file: exp4d.wgl #--------------------------------------------------------------------------- # # here are the patterns for test1 pattern group_ALL (AS,AVEC,A,BERR,BG,BGACK,BR,CDIS,CLK,DBEN,DS,DSACK0, DSACK1,Inst:I,Inst:O,Data:I,Data:O,ECS,FC,HALT:I,HALT:O, IPEND,IPL,OCS,RESET:I,RESET:O,RMC,"R/W",SIZ) repeat 12 resetcycle readcycle(B61B, B6EE13D6, FCA3, 100, 00) writecycle(9691, F0201827, A308, 111, 10) idlecycle readcycle(4281,F0201827,4314,111,10) writecycle(30C2,E4394013,4460,011,11) readcycle(EB3C,86F78F4C,F616,100,11) writecycle(EE53,9C32C7BA,E9EC,101,00) readcycle(BF16,D44C5EB1,DF57,000,11) writecycle(8D54,E7AB41EC,2927,100,00) readcycle(7ABC,8316DF68,0744,001,10) writecycle(69D0,AE31A3A2,0DF0,001,01) idlecycle readcycle(7A64,D3B28D8E,A4D6,011,11) writecycle(4F7E,CFFE12F7,4850,011,11) readcycle(9A5F,225D2C89,F66B,010,11) writecycle(619D,7721483A,4862,000,10) end INTERFACES/TDX/WGLTDX/exp5.vtran000064400001440000012000000044271103104161000167300ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDX # # Original File: "exp5.wgl" # # Target File: "exp5.tdx " # # Command File: "exp5.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp5.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl_cycle; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDX format # #======================================================================# } proc_block begin separate_timing; { #### state character translations for 'WGL'->'TDX" #### } state_trans 'x'->'X', 'z'->'Z', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 55; target_file "exp5.tdx"; {#### OUTPUT VECTOR FILE ####} simulator tdx; {#### OUTPUT FORMAT ####} end; end; INTERFACES/TDX/WGLTDX/exp4.vtran000064400001440000012000000043161103104161000167240ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDX # # Original File: "exp4.wgl" # # Target File: "exp4.tdx " # # Command File: "exp4.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp4.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl_cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDX format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TDX" #### } state_trans '-'->'X'; separate_timing; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp4.tdx"; {#### OUTPUT VECTOR FILE ####} header 60; simulator tdx; {#### OUTPUT FORMAT ####} end; end; # # Original File: "exp4.wgl" # # Target File: "exp4.tdx " # # Command File: "exp4.vtran" # # Reference File:"Readme.txt" #INTERFACES/TDX/VCDTDX/000075500001440000012000000000001103104161000147475ustar00jcosleystaff00000400000023INTERFACES/TDX/VCDTDX/exp1.vtran000064400001440000012000000141171103104161000167040ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > TDX # # Original File: "exp1A.vcd" # # Target File: "exp1.tdx " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into TDX format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'TDX'#### } STATE_TRANS inputs 'x'->'0', 'z'->'Z', 'X'->'0' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'X', 'z'->'Z' ; { #### Separate bidir in from out data using control pins #### } BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { #### collapse to cycle-based data, strobe all pins at 49 in cycle #### } CYCLE = 50; ALIGN_TO_STEP 50 49; { #### since VCD file does not contain this info separately #### } ADD_PIN HECS_CLK = 1; { #### add clock pin - not necessary if already in data #### } PINTYPE NRZ * @ 5; { #### drive all inputs at 5 #### } PINTYPE STB * @ 45; { #### strobe all outputs at 45 #### } PINTYPE RZ HECS_CLK @ 20, 30; { #### clock pin behavior #### } SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block target_file "exp1.tdx"; {#### OUTPUT VECTOR FILE ####} header 55; simulator tdx; {#### OUTPUT FORMAT ####} end; INTERFACES/TDX/EVCDTDX/000075500001440000012000000000001103104161000150545ustar00jcosleystaff00000400000023INTERFACES/TDX/EVCDTDX/exp1.vtran000064400001440000012000000075711103104161000170170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > TDX # # Original File: "exp1.evcd" # # Target File: "exp1.tdx " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into TDX format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'TDX' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block delete_pins vddo vsso pllvdd pllvss regvdd regvss; target_file "exp1.tdx"; {#### OUTPUT VECTOR FILE ####} simulator tdx; {#### OUTPUT FORMAT ####} end; end; INTERFACES/TDX/README000064400001440000012000000127121103104161000146360ustar00jcosleystaff00000400000023TDX -------- The main directory is "TDX" and the sub-directories are -> WGLTDX -> VCDTDX -> EVCDTDX -> STILTDX The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLTDX" contains the translation of WGL file to TDX output format. Sub-directory -> "EVCDTDX" contains the translation of EVCD file to TDX output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The TDX output format is invokde in the TVF_BLOCK with the following command - optional parameters are shown in []: simulator TDX [, TIMEPLATE_FILE = "filename"] [, TIMEPLATE = "timeplate_name"] [, MINIMIZE = "TRUE"] { default FALSE } ; When using the WGL or STIL reader it should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -scan flag is only necessary if the WGL or STIL file contains scan data. The TDX format creates up to three files: The vector file (.vec) The scan cells file (.scn) - only if scan if used in WGL file The initialization file (.ini) VTRAN produces a TDX vector file whose name is defined with the TARGET_FILE command in the VTRAN TVF_BLOCK. This file is bacically just a tabular file. This file can be reduced in size by specifying the parameter: SIMULATOR TDX, MINIMIZE = "TRUE"; Using this truncates each vector line after the last pin colunm whose state changed from the last vector. The timeplate file used by TDX can be handled in one of two ways. First of all, the following optional parameters can be used: SIMULATOR TDX, TIMEPLATE_FILE = "design.tpl", TIMEPLATE = "TPL1"; Here, the user is telling VTRAN that he has already created the timing file needed by TDX and VTRAN should specify this one in the initialization file. The format of the timing information in the timing file is identical to the timeplate blocks in the WGL file format. Thus, the user may wish to specify these himself. Since this TIMEPLATE_FILE can contain several actual timeplates, the TIMEPLATE parameter specifys which one to use initially. If the TIMEPLATE_FILE parameter is not used, then VTRAN will create a timing file itself. The information for this file can come from one of several places. If the Original Vector File is a WGL file (and the WGL_CYCLE canned reader is used), then VTRAN will pull the timing information directly from the timeplates in the WGL file. Otherwise, VTRAN will use timing information that has come from the Original Vector File itself (when using some of the other canned readers such as TDL_91 or TSTL2), or from PINTYPE statements specified by the user in the PROC_BLOCK of the VTRAN command file. It is important to remember that the TDX file format uses cycle-based data and hence the translation process must either maintain cycle-based data from the Original Vector File (if it was cycle-based to begin with), or collapse event-driven (print-on-change) data in the Original Vector File to cycle- based data. In either case, the SEPARATE_TIMING command should be used. An example command file for an WGL -> TDX translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > TDX # # Original File: "exp1.wgl" # # Target File: "exp1.tdx " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TDX format # #======================================================================# } proc_block disable_vector_filter; { #### state character translations for 'WGL'->'TDX" #### } state_trans '-'->'X'; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block target_file "exp1.tdx"; {#### OUTPUT VECTOR FILE ####} header 55; simulator tdx; {#### OUTPUT FORMAT ####} end; ################################################################################ INTERFACES/TDX/STILTDX/000075500001440000012000000000001103104161000151065ustar00jcosleystaff00000400000023INTERFACES/TDX/STILTDX/exp1.vtran000064400001440000012000000043701103104161000170430ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TDX # # Original File: "exp1.stil" # # Target File: "exp1.tdx " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle ; {#### INPUT FORMAT ####} { #### loops/repeats always flattened; expand flags not required #### } { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TDX format # #======================================================================# } proc_block disable_vector_filter; { #### state character translations for 'STIL'->'TDX" #### } state_trans '-'->'X'; state_trans outputs 'L'->'0', 'H'->'1'; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block target_file "exp1.tdx"; {#### OUTPUT VECTOR FILE ####} header 55; simulator tdx; {#### OUTPUT FORMAT ####} end; INTERFACES/FSDB/000075500001440000012000000000001103104161000140325ustar00jcosleystaff00000400000023INTERFACES/FSDB/FSDBVERILOG/000075500001440000012000000000001103104161000156005ustar00jcosleystaff00000400000023INTERFACES/FSDB/FSDBVERILOG/exp1.vcd000064400001440000012000000376321103104161000171660ustar00jcosleystaff00000400000023$date Sep 20, 2000 16:57:02 $end $version ncsim: v2.2.(s3) $end $timescale 10 ps $end $scope module membistv_chip $end $scope module chip $end $var wire 1 ! hclkin $end $var wire 1 " harb $end $var wire 1 # hcs_n $end $var wire 1 $ hhold $end $var wire 1 % hholda $end $var wire 1 & hblast $end $var wire 1 ' has_n $end $var wire 1 ( hwr $end $var wire 1 ) hbe_n [3] $end $var wire 1 * hbe_n [2] $end $var wire 1 + hbe_n [1] $end $var wire 1 , hbe_n [0] $end $var wire 1 - hwait_n $end $var wire 1 . hboff $end $var wire 1 / hrdy_n $end $var wire 1 0 hd [31] $end $var wire 1 1 hd [30] $end $var wire 1 2 hd [29] $end $var wire 1 3 hd [28] $end $var wire 1 4 hd [27] $end $var wire 1 5 hd [26] $end $var wire 1 6 hd [25] $end $var wire 1 7 hd [24] $end $var wire 1 8 hd [23] $end $var wire 1 9 hd [22] $end $var wire 1 : hd [21] $end $var wire 1 ; hd [20] $end $var wire 1 < hd [19] $end $var wire 1 = hd [18] $end $var wire 1 > hd [17] $end $var wire 1 ? hd [16] $end $var wire 1 @ hd [15] $end $var wire 1 A hd [14] $end $var wire 1 B hd [13] $end $var wire 1 C hd [12] $end $var wire 1 D hd [11] $end $var wire 1 E hd [10] $end $var wire 1 F hd [9] $end $var wire 1 G hd [8] $end $var wire 1 H hd [7] $end $var wire 1 I hd [6] $end $var wire 1 J hd [5] $end $var wire 1 K hd [4] $end $var wire 1 L hd [3] $end $var wire 1 M hd [2] $end $var wire 1 N hd [1] $end $var wire 1 O hd [0] $end $var wire 1 P srck0 $end $var wire 1 Q srd0 $end $var wire 1 R srfs0 $end $var wire 1 S stck0 $end $var wire 1 T std0 $end $var wire 1 U stfs0 $end $var wire 1 V srck1 $end $var wire 1 W srd1 $end $var wire 1 X srfs1 $end $var wire 1 Y stck1 $end $var wire 1 Z std1 $end $var wire 1 [ stfs1 $end $var wire 1 \ srck2 $end $var wire 1 ] srd2 $end $var wire 1 ^ srfs2 $end $var wire 1 _ stck2 $end $var wire 1 ` std2 $end $var wire 1 a stfs2 $end $var wire 1 b srck3 $end $var wire 1 c srd3 $end $var wire 1 d srfs3 $end $var wire 1 e stck3 $end $var wire 1 f std3 $end $var wire 1 g stfs3 $end $var wire 1 h gpio [15] $end $var wire 1 i gpio [14] $end $var wire 1 j gpio [13] $end $var wire 1 k gpio [12] $end $var wire 1 l gpio [11] $end $var wire 1 m gpio [10] $end $var wire 1 n gpio [9] $end $var wire 1 o gpio [8] $end $var wire 1 p gpio [7] $end $var wire 1 q gpio [6] $end $var wire 1 r gpio [5] $end $var wire 1 s gpio [4] $end $var wire 1 t gpio [3] $end $var wire 1 u gpio [2] $end $var wire 1 v gpio [1] $end $var wire 1 w gpio [0] $end $var wire 1 x pjclk $end $var wire 1 y pjdo $end $var wire 1 z pjrstb $end $var wire 1 { pjms $end $var wire 1 | pjdi $end $var wire 1 } ljclk $end $var wire 1 ~ ljdo $end $var wire 1 !! ljrstb $end $var wire 1 "! ljms $end $var wire 1 #! ljdi $end $var wire 1 $! ej_rst_n $end $var wire 1 %! ej_dclk $end $var wire 1 &! ejtag [2] $end $var wire 1 '! ejtag [1] $end $var wire 1 (! ejtag [0] $end $var wire 1 )! scan_en_n $end $var wire 1 *! test_en_n $end $var wire 1 +! jtsel $end $var wire 1 ,! lx_bisten $end $var wire 1 -! tm_dsp $end $var wire 1 .! tm_hi $end $var wire 1 /! tm_sb $end $var wire 1 0! rstn $end $var wire 1 1! dm_sel [5] $end $var wire 1 2! dm_sel [4] $end $var wire 1 3! dm_sel [3] $end $var wire 1 4! dm_sel [2] $end $var wire 1 5! dm_sel [1] $end $var wire 1 6! dm_sel [0] $end $var wire 1 7! pll_rstn $end $var wire 1 8! pll_oe $end $var wire 1 9! pll_bp $end $var wire 1 :! pll_pd $end $var wire 1 ;! pll_clkout $end $var wire 1 ! pll_sel [1] $end $var wire 1 ?! pll_sel [0] $end $var wire 1 )! clk_ratio $end $var wire 1 @! pad_hhold_outen $end $var wire 1 A! pad_hholda_outen $end $var wire 1 B! pad_hblast_outen $end $var wire 1 C! pad_has_n_outen $end $var wire 1 D! pad_hwr_outen $end $var wire 1 E! pad_hbe_n_outen $end $var wire 1 F! pad_hwait_n_outen $end $var wire 1 G! pad_hrdy_n_outen $end $var wire 1 H! pad_hd_outen_d $end $var wire 1 I! pad_hd_outen_z $end $var wire 1 J! pad_sck_outen [0] $end $var wire 1 K! pad_sfs_outen [0] $end $var wire 1 L! pad_sck_outen [4] $end $var wire 1 M! pad_sxd_outen [0] $end $var wire 1 N! pad_sfs_outen [4] $end $var wire 1 O! pad_sck_outen [1] $end $var wire 1 P! pad_sfs_outen [1] $end $var wire 1 Q! pad_sck_outen [5] $end $var wire 1 R! pad_sxd_outen [1] $end $var wire 1 S! pad_sfs_outen [5] $end $var wire 1 T! pad_sck_outen [2] $end $var wire 1 U! pad_sfs_outen [2] $end $var wire 1 V! pad_sck_outen [6] $end $var wire 1 W! pad_sxd_outen [2] $end $var wire 1 X! pad_sfs_outen [6] $end $var wire 1 Y! pad_sck_outen [3] $end $var wire 1 Z! pad_sfs_outen [3] $end $var wire 1 [! pad_sck_outen [7] $end $var wire 1 \! pad_sxd_outen [3] $end $var wire 1 ]! pad_sfs_outen [7] $end $var wire 1 ^! pad_gpio_outen [15] $end $var wire 1 _! pad_gpio_outen [14] $end $var wire 1 `! pad_gpio_outen [13] $end $var wire 1 a! pad_gpio_outen [12] $end $var wire 1 b! pad_gpio_outen [11] $end $var wire 1 c! pad_gpio_outen [10] $end $var wire 1 d! pad_gpio_outen [9] $end $var wire 1 e! pad_gpio_outen [8] $end $var wire 1 f! pad_gpio_outen [7] $end $var wire 1 g! pad_gpio_outen [6] $end $var wire 1 h! pad_gpio_outen [5] $end $var wire 1 i! pad_gpio_outen [4] $end $var wire 1 j! pad_gpio_outen [3] $end $var wire 1 k! pad_gpio_outen [2] $end $var wire 1 l! pad_gpio_outen [1] $end $var wire 1 m! pad_gpio_outen [0] $end $scope module pad_top $end $var wire 1 n! pad_ej_outen $end $upscope $end $scope module pad_right $end $var wire 1 o! pad_pjdo_outen $end $var wire 1 p! pad_ljdo_outen $end $var wire 1 p! pad_pll_clkout_outen $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars z! z" z# x$ x% z& z' z( z) z* z+ z, z- z. z/ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z: z; z< z= z> z? z@ zA zB zC zD zE zF zG zH zI zJ zK zL zM zN zO xP zQ xR xS xT xU xV zW xX xY xZ x[ x\ z] x^ x_ x` xa xb zc xd xe xf xg xh xi xj xk xl xm xn xo xp xq xr xs xt xu xv xw 0x xy 0z 0{ 0| z} x~ z!! z"! z#! z$! x%! x&! x'! x(! 1)! 1*! 0+! z,! z-! z.! 0/! 00! z1! z2! z3! z4! z5! z6! z7! 08! 09! 0:! x;! 0! 1?! x@! xA! 1B! 1C! 1D! 1E! 1F! 1G! 1H! 1I! xJ! xK! xL! xM! xN! xO! xP! xQ! xR! xS! xT! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! 0n! 0o! 0p! $end #600 19! 1+! #640 0;! #750 1 em1_mdc $end $var port 1 ? em1_mdio $end $var port [15:0] @ md $end $var port [12:0] A ma $end $var port [1:0] B mb $end $var port [1:0] C mm $end $var port 1 D mras_ $end $var port 1 E mcas_ $end $var port 1 F mwe_ $end $var port [1:0] G mcs_ $end $var port 1 H mcke $end $var port 1 I mclk $end $var port [42:40] J gpio42_40 $end $var port 1 K gpio38 $end $var port 1 L gpio33 $end $var port 1 M gpio26 $end $var port 1 N gpio25 $end $var port [22:13] O gpio22_13 $end $var port [8:5] P gpio8_5 $end $var port 1 Q gpio3 $end $var port 1 R gpio2 $end $var port 1 S gpio1 $end $var port 1 T trst_ $end $var port 1 U tck $end $var port 1 V tms $end $var port 1 W tdi $end $var port 1 X tdo $end $var port 1 Y afetx0 $end $var port 1 Z aferx0 $end $var port 1 [ aferx1 $end $var port 1 \ fafe_sclk $end $var port 1 ] fafe_stb $end $var port 1 ^ fafe_ctrlin $end $var port 1 _ fafe_ctrlout $end $var port 1 ` mon_done $end $var port 1 a mon_clk $end $var port 1 b mon_out $end $var port 1 c vregenn $end $var port 1 d vddo $end $var port 1 e vsso $end $var port 1 f pllvdd $end $var port 1 g pllvss $end $var port 1 h regvdd $end $var port 1 i regvss $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpports pa 6 6 ! pX 6 6 " pX 6 6 # pX 6 6 $ pa 6 6 % pb 6 6 & pXXXX 6666 6666 ' pa 6 6 ( pa 6 6 ) pXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 66666666666666666666666666666666 66666666666666666666666666666666 * pX 6 6 + pX 6 6 , pXXXXXXXXXX 6666666666 6666666666 - pX 6 6 . pX 6 6 / pX 6 6 0 pX 6 6 1 pX 6 6 2 pX 6 6 3 pa 6 6 4 pXXXX 6666 6666 5 pX 6 6 6 pX 6 6 7 pa 6 6 8 pa 6 6 9 pa 6 6 : pXaaa 6666 6666 ; pa 6 6 < pa 6 6 = pX 6 6 > pX 6 6 ? p???????????????? 6666666666666666 6666666666666666 @ pXXXXXbb?????? 6666666666666 6666666666666 A pXX 66 66 B pXX 66 66 C pX 6 6 D pX 6 6 E pX 6 6 F pXX 66 66 G pX 6 6 H pX 6 6 I pXXX 666 666 J p? 6 6 K p? 6 6 L p? 6 6 M pX 6 6 N pX??X?X??XX 6666666666 6666666666 O p?XX? 6666 6666 P pX 6 6 Q pX 6 6 R p? 6 6 S pa 6 6 T pa 6 6 U pb 6 6 V pa 6 6 W pX 6 6 X pX 6 6 Y pX 6 6 Z pX 6 6 [ pa 6 6 \ pX 6 6 ] pX 6 6 ^ pa 6 6 _ pX 6 6 ` pX 6 6 a pX 6 6 b pU 0 6 c ph 0 6 d pl 6 0 e pF 0 0 f pF 0 0 g pF 0 0 h pF 0 0 i $end #1 pT 0 0 " pD 6 0 ) #1 pD 6 0 % pU 0 6 & pDDDD 5555 0000 ' pD 6 0 ( pT 0 0 0 pD 6 0 4 pD 6 0 8 pD 6 0 9 pD 6 0 : pTDDD 0666 0000 ; pD 6 0 < pD 6 0 = pD 6 0 T pd 6 0 U pU 0 6 V pD 6 0 W pT 0 0 Z pT 0 0 [ pD 6 0 \ pD 6 0 _ #9 pT 0 0 ^ #9 pT 0 0 Y #9 pXXXXXbU?????? 6666660666666 6666666666666 A #9 pT 0 0 ] #10 pU 6 6 ! #10 pXXXXXUU?????? 6666600666666 6666666666666 A #11 pT 0 0 X #13 pL 6 0 I #13 pXXXXLUU?????? 6666600666666 6666066666666 A #13 pLXXXLUU?????? 6666600666666 0666066666666 A #13 pXH 60 66 C #13 pLXXLLUU?????? 6666600666666 0660066666666 A #13 pLLXLLUU?????? 6666600666666 0060066666666 A #13 pHX 06 66 G #13 pHH 00 66 C #14 pHH 00 66 G #14 pLLLLLUU?????? 6666600666666 0000066666666 A #14 pL 6 0 H #14 pXL 66 60 B #14 pLL 66 00 B #15 pH 0 6 D #15 pXXT 660 660 J #15 pH 0 6 E #15 pH 0 6 F #15 pT 0 0 R #15 pX??X?X??TX 6666666606 6666666606 O #15 pT??X?X??TX 0666666606 0666666606 O #15 pXXXXXXXXXXXXXXXXXXXXXXfXXXXXXXXX 66666666666666666666660666666666 66666666666666666666660666666666 * #15 pXXXXXXXXXXXXXXXXXXXXXXffXXXXXXXX 66666666666666666666660066666666 66666666666666666666660066666666 * #15 pN 6 6 M #15 pTXT 060 060 J #15 p?XT? 6606 6606 P #16 pTN?X?X??TX 0666666606 0666666606 O #16 pXXXXXXXXXXXXXXXXXXXXXXffXXXXXfXX 66666666666666666666660066666066 66666666666666666666660066666066 * #16 pXXXXXXXXXXXXXXXXXXXXXXffXXXXXffX 66666666666666666666660066666006 66666666666666666666660066666006 * #16 pXXXXXXXXXXXXXXXXXXXXXXffXXXXXfff 66666666666666666666660066666000 66666666666666666666660066666000 * #16 pXXXXXXXXXXXXXXXXXXXXXXffXXXXffff 66666666666666666666660066660000 66666666666666666666660066660000 * #16 pTTT 000 000 J #16 pT 0 0 N #16 pXXXXXXXXXXXXXXXXXXXXXXffXXXfffff 66666666666666666666660066600000 66666666666666666666660066600000 * #16 pXXXXXXXXXXXXXXXXXXXXXXffXXffffff 66666666666666666666660066000000 66666666666666666666660066000000 * #16 pXXXXXXXXXXXXXXXXXXXXXXffXfffffff 66666666666666666666660060000000 66666666666666666666660060000000 * #16 pXXXXXXXXXXXXXXXXXXXXXXffffffffff 66666666666666666666660000000000 66666666666666666666660000000000 * #16 pXXXXXXXXXXXXXXXXXXXXXfffffffffff 66666666666666666666600000000000 66666666666666666666600000000000 * #16 pT 0 0 Q #16 pTN?X?X?NTX 0666666606 0666666606 O #16 pTN?X?X?NTT 0666666600 0666666600 O #16 pXXXXXXXXXXXXXXXXXXXXffffffffffff 66666666666666666666000000000000 66666666666666666666000000000000 * #16 pXXXXXXXXXXXXXXXXXXXfffffffffffff 66666666666666666660000000000000 66666666666666666660000000000000 * #16 pNXT? 6606 6606 P #16 p??N????????????? 6666666666666666 6666666666666666 @ #16 pXXXXXXXXXXXXXXXXXXffffffffffffff 66666666666666666600000000000000 66666666666666666600000000000000 * #16 p??NN???????????? 6666666666666666 6666666666666666 @ #16 p??NNN??????????? 6666666666666666 6666666666666666 @ #16 pXXXXXXXXXXXXXXXXXfffffffffffffff 66666666666666666000000000000000 66666666666666666000000000000000 * #16 pXXXXXXXXXXXXXXXXffffffffffffffff 66666666666666660000000000000000 66666666666666660000000000000000 * #16 pL 6 0 # #16 pT 0 0 ? #16 p??NNN?????N????? 6666666666666666 6666666666666666 @ #16 p??NNN???N?N????? 6666666666666666 6666666666666666 @ #17 pTN?XNX?NTT 0666666600 0666666600 O #17 pTN?XNXNNTT 0666666600 0666666600 O #17 p??NNNN??N?N????? 6666666666666666 6666666666666666 @ #17 pD 5 0 3 #17 pU 0 5 2 #17 pLLLLLUUN????? 6666600666666 0000066666666 A #17 pTNNXNXNNTT 0666666600 0666666600 O #17 p??NNNNN?N?N????? 6666666666666666 6666666666666666 @ #17 p??NNNNNNN?N????? 6666666666666666 6666666666666666 @ #17 p??NNNNNNN?N??N?? 6666666666666666 6666666666666666 @ #17 p??NNNNNNN?N?NN?? 6666666666666666 6666666666666666 @ #17 p??NNNNNNN?NNNN?? 6666666666666666 6666666666666666 @ #17 p??NNNNNNNNNNNN?? 6666666666666666 6666666666666666 @ #17 pN 6 6 L #17 pL 6 0 ` #17 pXLXX 6666 6066 5 #17 pL 6 0 a #18 p??NNNNNNNNNNNN?N 6666666666666666 6666666666666666 @ #18 p??NNNNNNNNNNNNNN 6666666666666666 6666666666666666 @ #18 p?NNNNNNNNNNNNNNN 6666666666666666 6666666666666666 @ #18 pNNNNNNNNNNNNNNNN 6666666666666666 6666666666666666 @ #18 pLLLLLUUN???N? 6666600666666 0000066666666 A #18 pNXTN 6606 6606 P #18 pLLLLLUUN???NN 6666600666666 0000066666666 A #18 pLLLLLUUNN??NN 6666600666666 0000066666666 A #18 pXLXL 6666 6060 5 #18 pLLLLLUUNN?NNN 6666600666666 0000066666666 A #18 pXLLL 6666 6000 5 #18 pLLLL 6666 0000 5 #18 pLLLLLUUNNNNNN 6666600666666 0000066666666 A #19 pD 5 0 , #19 pL 6 0 7 #19 pL 6 0 6 #19 pTNNHNXNNTT 0660666600 0666666600 O #19 pDXXXXXXXXX 5666666666 0666666666 - #20 pL 6 0 . #20 pL 6 0 $ #20 pNHTN 6006 6606 P #20 pDXXDXXXXXX 5665666666 0660666666 - #20 pDXXDDXXXXX 5665566666 0660066666 - #20 pD 5 0 + #20 pDXXDDDXXXX 5665556666 0660006666 - #20 pD 6 0 ! #20 pDXXDDDDXXX 5665555666 0660000666 - #20 pXXXXXXXXXXLXXXXXffffffffffffffff 66666666666666660000000000000000 66666666660666660000000000000000 * #20 pL 6 0 1 #20 pL 6 0 / #20 pDXXDDDDXLX 5665555666 0660000606 - #20 pDXXDDDDXLD 5665555665 0660000600 - #20 pDXXDDDDDLD 5665555565 0660000000 - #20 pDXDDDDDDLD 5655555565 0600000000 - #20 pDDDDDDDDLD 5555555565 0000000000 - #21 pXXXXXXXXXXLXLXXXffffffffffffffff 66666666666666660000000000000000 66666666660606660000000000000000 * #21 pU 0 6 M #21 pC 6 6 S #21 pL 6 0 > #21 pXXHXXXXXXXLXLXXXffffffffffffffff 66066666666666660000000000000000 66666666660606660000000000000000 * #21 pTNNHNLNNTT 0660666600 0666606600 O #21 pHXHXXXXXXXLXLXXXffffffffffffffff 06066666666666660000000000000000 66666666660606660000000000000000 * #21 pHHHXXXXXXXLXLXXXffffffffffffffff 00066666666666660000000000000000 66666666660606660000000000000000 * #22 pHHHXXXXXXLLXLXXXffffffffffffffff 00066666666666660000000000000000 66666666600606660000000000000000 * #22 pHHHXXXXXXLLXLXXLffffffffffffffff 00066666666666660000000000000000 66666666600606600000000000000000 * #22 pHHHXXXXXLLLXLXXLffffffffffffffff 00066666666666660000000000000000 66666666000606600000000000000000 * #22 pC 6 6 K #22 pHHHXXXLXLLLXLXXLffffffffffffffff 00066666666666660000000000000000 66666606000606600000000000000000 * #22 pHHHXXXLXLLLXLLXLffffffffffffffff 00066666666666660000000000000000 66666606000600600000000000000000 * #22 pHHHXXXLLLLLXLLXLffffffffffffffff 00066666666666660000000000000000 66666600000600600000000000000000 * #22 pHHHXXXLLLLLLLLXLffffffffffffffff 00066666666666660000000000000000 66666600000000600000000000000000 * #23 pHHHXLXLLLLLLLLXLffffffffffffffff 00066666666666660000000000000000 66660600000000600000000000000000 * #23 pHHHXLLLLLLLLLLXLffffffffffffffff 00066666666666660000000000000000 66660000000000600000000000000000 * #23 pHHHLLLLLLLLLLLXLffffffffffffffff 00066666666666660000000000000000 66600000000000600000000000000000 * #23 pHHHLLLLLLLLLLLLLffffffffffffffff 00066666666666660000000000000000 66600000000000000000000000000000 * #23 pL 6 0 b #30 pU 6 6 ! #40 pD 6 0 ! #50 pU 6 6 ! #60 pD 6 0 ! #70 pU 6 6 ! #80 pD 6 0 ! #90 pU 6 6 ! #100 pD 6 0 ! #110 pU 6 6 ! #120 pD 6 0 ! #130 pU 6 6 ! #140 pD 6 0 ! #150 pU 6 6 ! #160 pD 6 0 ! #170 pU 6 1 ! #180 pD 6 0 ! #190 pU 6 6 ! #200 pD 6 0 ! #210 pU 6 6 ! #220 pD 6 0 ! #230 pU 6 6 ! #240 pD 6 0 ! #250 pU 6 6 ! #260 pD 6 0 ! #270 pU 6 6 ! #280 pD 6 0 ! #290 pU 6 6 ! #300 pD 6 0 ! #310 pU 6 6 ! #320 pD 6 0 ! #330 pU 6 6 ! #340 pD 6 0 ! #350 pU 6 6 ! #360 pD 6 0 ! #370 pU 6 6 ! #380 pD 6 0 ! #390 pU 6 6 ! #400 pD 6 0 ! #410 pU 6 6 ! #420 pD 6 0 ! #430 pU 6 6 ! #440 pD 6 0 ! #450 pU 6 6 ! #460 pD 6 0 ! #470 pU 6 6 ! #480 pD 6 0 ! #490 pU 6 6 ! #500 pD 6 0 ! #510 pU 6 6 ! #520 pD 6 0 ! #530 pU 6 6 ! #540 pD 6 0 ! #550 pU 6 6 ! #560 pD 6 0 ! #570 pU 6 6 ! #580 pD 6 0 ! #590 pU 6 6 ! #600 pD 6 0 ! #610 pU 6 6 ! #620 pD 6 0 ! #630 pU 6 6 ! #640 pD 6 0 ! #640 pU 0 6 ) #650 pU 6 6 ! #660 pD 6 0 ! #670 pU 6 6 ! #680 pD 6 0 ! #690 pU 6 6 ! #700 pD 6 0 ! #705 pHHHLLLLLLLLLLLLLUUUUUUUUUUUUUUUU 00066666666666660000000000000000 66600000000000006666666666666666 * #710 pU 6 6 ! #720 pD 6 0 ! #730 pU 6 6 ! #735 pH 0 6 I #739 pH 0 6 $ #740 pD 6 0 ! #750 pU 6 6 ! #755 pL 6 0 I #760 pD 6 0 ! #761 pL 6 0 $ #770 pU 6 6 ! #775 pH 0 6 I #779 pH 0 6 $ #780 pD 6 0 ! #790 pU 6 6 ! #795 pL 6 0 I #800 pD 6 0 ! #801 pL 6 0 $ #810 pU 6 6 ! #815 pH 0 6 I #819 pH 0 6 $ #820 pD 6 0 ! #830 pU 6 6 ! #835 pL 6 0 I #840 pD 6 0 ! #841 pL 6 0 $ #850 pU 6 6 ! #855 pH 0 6 I #859 pH 0 6 $ #860 pD 6 0 ! #870 pU 6 6 ! #875 pL 6 0 I #880 pD 6 0 ! #881 pL 6 0 $ #890 pU 6 6 ! #895 pH 0 6 I #899 pH 0 6 $ #900 pD 6 0 ! #910 pU 6 6 ! #915 pL 6 0 I #920 pD 6 0 ! #921 pL 6 0 $ #930 pU 6 6 ! #935 pH 0 6 I #939 pH 0 6 $ #940 pD 6 0 ! #950 pU 6 6 ! #955 pL 6 0 I #960 pD 6 0 ! #961 pL 6 0 $ #970 pU 6 6 ! #975 pH 0 6 I #979 pH 0 6 $ #980 pD 6 0 ! #990 pU 6 6 ! #995 pL 6 0 I #1000 pD 6 0 ! #1001 pL 6 0 $ #1010 pU 6 6 ! #1015 pH 0 6 I #1019 pH 0 6 $ #1020 pD 6 0 ! #1030 pU 6 6 ! #1035 pL 6 0 I #1040 pD 6 0 ! #1041 pL 6 0 $ #1050 pU 6 6 ! #1055 pH 0 6 I #1059 pH 0 6 $ #1060 pD 6 0 ! #1070 pU 6 6 ! #1075 pL 6 0 I #1080 pD 6 0 ! #1081 pL 6 0 $ #1090 pU 6 6 ! #1095 pH 0 6 I #1099 pH 0 6 $ #1100 pD 6 0 ! #1110 pU 6 6 ! #1115 pL 6 0 I #1120 pD 6 0 ! #1121 pL 6 0 $ #1130 pU 6 6 ! #1135 pH 0 6 I #1139 pH 0 6 $ #1140 pD 6 0 ! #1150 pU 6 6 ! #1155 pL 6 0 I #1160 pD 6 0 ! #1161 pL 6 0 $ #1170 pU 6 6 ! #1175 pH 0 6 I #1179 pH 0 6 $ #1180 pD 6 0 ! #1190 pU 6 6 ! #1195 pL 6 0 I #1200 pD 6 0 ! #1201 pL 6 0 $ #1210 pU 6 6 ! #1215 pH 0 6 I #1219 pH 0 6 $ #1220 pD 6 0 ! #1230 pU 6 6 ! #1235 pL 6 0 I #1240 pD 6 0 ! #1241 pL 6 0 $ #1250 pU 6 6 ! #1255 pH 0 6 I #1259 pH 0 6 $ #1260 pD 6 0 ! #1270 pU 6 6 ! #1275 pL 6 0 I #1280 pD 6 0 ! #1281 pL 6 0 $ #1290 pU 6 6 ! #1295 pH 0 6 I #1299 pH 0 6 $ #1300 pD 6 0 ! #1310 pU 6 6 ! #1315 pL 6 0 I #1320 pD 6 0 ! #1321 pL 6 0 $ #1330 pU 6 6 ! #1335 pH 0 6 I #1339 pH 0 6 $ #1340 pD 6 0 ! #1350 pU 6 6 ! #1355 pL 6 0 I #1360 pD 6 0 ! #1361 pL 6 0 $ #1370 pU 6 6 ! #1375 pH 0 6 I #1379 pH 0 6 $ #1380 pD 6 0 ! #1390 pU 6 6 ! #1395 pL 6 0 I #1400 pD 6 0 ! #1401 pL 6 0 $ #1410 pU 6 6 ! #1415 pH 0 6 I #1419 pH 0 6 $ #1420 pD 6 0 ! #1430 pU 6 6 ! #1435 pL 6 0 I #1440 pD 6 0 ! #1441 pL 6 0 $ #1450 pU 6 6 ! #1455 pH 0 6 I #1459 pH 0 6 $ #1460 pD 6 0 ! #1470 pU 6 6 ! #1475 pL 6 0 I #1480 pD 6 0 ! #1481 pL 6 0 $ #1490 pU 6 6 ! #1495 pH 0 6 I #1499 pH 0 6 $ #1500 pD 6 0 ! #1510 pU 6 6 ! #1515 pL 6 0 I #1520 pD 6 0 ! #1521 pL 6 0 $ #1530 pU 6 6 ! #1535 pH 0 6 I #1539 pH 0 6 $ #1540 pD 6 0 ! #1550 pU 6 6 ! #1555 pL 6 0 I #1560 pD 6 0 ! #1561 pL 6 0 $ #1570 pU 6 6 ! #1575 pH 0 6 I #1579 pH 0 6 $ #1580 pD 6 0 ! #1590 pU 6 6 ! #1595 pL 6 0 I #1600 pD 6 0 ! #1601 pL 6 0 $ #1610 pU 6 6 ! #1615 pH 0 6 I #1619 pH 0 6 $ #1620 pD 6 0 ! #1630 pU 6 6 ! #1635 pL 6 0 I #1640 pD 6 0 ! #1641 pL 6 0 $ #1650 pU 6 6 ! #1655 pH 0 6 I #1659 pH 0 6 $ #1660 pD 6 0 ! #1670 pU 6 6 ! #1675 pL 6 0 I #1680 pD 6 0 ! #1681 pL 6 0 $ #1690 pU 6 6 ! #1695 pH 0 6 I #1699 pH 0 6 $ #1700 pD 6 0 ! #1710 pU 6 6 ! #1715 pL 6 0 I #1720 pD 6 0 ! #1721 pL 6 0 $ #1730 pU 6 6 ! #1735 pH 0 6 I #1739 pH 0 6 $ #1740 pD 6 0 ! #1750 pU 6 6 ! #1755 pL 6 0 I #1760 pD 6 0 ! #1761 pL 6 0 $ #1770 pU 6 6 ! #1775 pH 0 6 I #1779 pH 0 6 $ #1780 pD 6 0 ! #1790 pU 6 6 ! #1795 pL 6 0 I #1800 pD 6 0 ! #1801 pL 6 0 $ #1810 pU 6 6 ! #1815 pH 0 6 I #1819 pH 0 6 $ #1820 pD 6 0 ! #1828 pX 6 6 2 pX 6 6 3 #1830 pU 6 6 ! #1835 pL 6 0 I #1837 pLLLLXUUNNNNNN 6666600666666 0000666666666 A #1837 pLLXLXUUNNNNNN 6666600666666 0060666666666 A #1838 pLLXXXUUNNNNNN 6666600666666 0066666666666 A #1838 pLXXXXUUNNNNNN 6666600666666 0666666666666 A #1838 pLX 66 06 B #1838 pXX 66 66 B #1840 pD 6 0 ! #1841 pL 6 0 $ #1850 pU 6 6 ! #1855 pH 0 6 I #1859 pH 0 6 $ #1860 pD 6 0 ! #1870 pU 6 6 ! #1875 pL 6 0 I #1880 pD 6 0 ! #1881 pL 6 0 $ #1890 pU 6 6 ! #1895 pH 0 6 I #1899 pH 0 6 $ #1899 pHHHLLLfLLLLLLLLLUUUUUUUUUUUUUUUU 00066606666666660000000000000000 66600000000000006666666666666666 * #1899 pHHHLLLfLffLLLLLLUUUUUUUUUUUUUUUU 00066606006666660000000000000000 66600000000000006666666666666666 * #1899 pHHHLLLfLffLLLLfLUUUUUUUUUUUUUUUU 00066606006666060000000000000000 66600000000000006666666666666666 * #1899 pHfHLLLfLffLLLLfLUUUUUUUUUUUUUUUU 00066606006666060000000000000000 60600000000000006666666666666666 * #1899 pffHLLLfLffLLLLfLUUUUUUUUUUUUUUUU 00066606006666060000000000000000 00600000000000006666666666666666 * #1899 pN 6 6 S #1900 pffHLLLfLffLLfffLUUUUUUUUUUUUUUUU 00066606006600060000000000000000 00600000000000006666666666666666 * #1900 pffHLLLfLfffffffLUUUUUUUUUUUUUUUU 00066606000000060000000000000000 00600000000000006666666666666666 * #1900 pffHLfffLfffffffLUUUUUUUUUUUUUUUU 00060006000000060000000000000000 00600000000000006666666666666666 * #1900 pD 6 0 ! #1900 pffHffffLfffffffLUUUUUUUUUUUUUUUU 00000006000000060000000000000000 00600000000000006666666666666666 * #1900 pffHffffffffffffLUUUUUUUUUUUUUUUU 00000000000000060000000000000000 00600000000000006666666666666666 * #1900 pfffffffffffffffLUUUUUUUUUUUUUUUU 00000000000000060000000000000000 00000000000000006666666666666666 * #1900 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #1901 pN 6 6 K #1903 pDDDDDDDDHD 5555555505 0000000060 - #1903 pTNNHNHNNTT 0660606600 0666666600 O #1910 pU 6 6 ! #1915 pL 6 0 I #1916 pffffffffffffffff 0000000000000000 0000000000000000 @ pLXXXXUUffffff 6666600000000 0666666000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #1920 pD 6 0 ! #1921 pL 6 0 $ #1930 pU 6 6 ! #1935 pH 0 6 I #1939 pH 0 6 $ #1940 pD 6 0 ! #1950 pU 6 6 ! #1955 pL 6 0 I #1960 pD 6 0 ! #1961 pL 6 0 $ #1964 pDDDDDDDUDDDDDDDD 6666666066666666 0000000600000000 @ pLXXXXUUDDDDDD 6666600666666 0666666000000 A pD 6 0 K pD 6 0 L pTDDHDHDDTT 0660606600 0006060000 O pDHTD 6006 0600 P pD 6 0 S #1970 pU 6 6 ! #1975 pH 0 6 I #1979 pH 0 6 $ #1980 pD 6 0 ! #1988 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #1990 pU 6 6 ! #1995 pL 6 0 I #1999 pLXXXXDUDDDDDD 6666660666666 0666606000000 A #2000 pD 6 0 ! #2001 pL 6 0 $ #2004 pLXXXXDUDUUUDU 6666660600060 0666606066606 A pUHTD 0006 6600 P #2010 pU 6 6 ! #2015 pH 0 6 I #2019 pH 0 6 $ #2020 pD 6 0 ! #2030 pU 6 6 ! #2035 pL 6 0 I #2037 pLXXXLDUDUUUDU 6666660600060 0666006066606 A #2037 pLXLXLDUDUUUDU 6666660600060 0606006066606 A #2037 pLXLLLDUDUUUDU 6666660600060 0600006066606 A #2037 pLLLLLDUDUUUDU 6666660600060 0000006066606 A #2038 pXL 66 60 B #2038 pLL 66 00 B #2039 pLLLLLUDDUUUDU 6666606600060 0000060066606 A #2040 pD 6 0 ! #2041 pL 6 0 $ #2044 pDDDUUDUDDDDDDDUD 6660060666666606 0006606000000060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pTDUHDHDDTT 0600606600 0066060000 O pDHTD 6006 0600 P #2050 pU 6 6 ! #2055 pH 0 6 I #2059 pH 0 6 $ #2060 pD 6 0 ! #2070 pU 6 6 ! #2075 pL 6 0 I #2076 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #2080 pffLfffffffffffff 0060000000000000 0000000000000000 @ #2080 pffLLffffffffffff 0066000000000000 0000000000000000 @ #2080 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #2080 pTffHLHffTT 0000600000 0006060000 O #2080 pD 6 0 ! #2080 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #2080 pLLLLLUDLfffff 6666606600000 0000060000000 A #2081 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #2081 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #2081 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #2081 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #2081 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #2081 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #2081 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #2081 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #2081 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #2081 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #2081 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #2081 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #2081 pLLLLLUDLfffLf 6666606600060 0000060000000 A #2081 pLLLLLUDLfffLL 6666606600066 0000060000000 A #2081 pL 6 0 $ #2081 pLLLLLUDLffLLL 6666606600666 0000060000000 A #2081 pLLLLLUDLLfLLL 6666606660666 0000060000000 A #2081 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #2083 pfLffffLfffffffffNNNNNNNNNNNNNNNN 06000060000000006666666666666666 00000000000000006666666666666666 * #2083 pLLffffLfffffffffNNNNNNNNNNNNNNNN 66000060000000006666666666666666 00000000000000006666666666666666 * #2083 pL 6 0 S #2083 pLLffffLfLLffffffNNNNNNNNNNNNNNNN 66000060660000006666666666666666 00000000000000006666666666666666 * #2083 pLLffffLfLLffffLfNNNNNNNNNNNNNNNN 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pTffHLHfLTT 0000600600 0006060000 O #2084 pTLfHLHfLTT 0600600600 0006060000 O #2084 pLLffffLfLLffffLfNNNNNNCNNNNNNNNN 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNNNNNN 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNNNCNN 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNNNCCN 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNNNCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNNCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNNCCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNNCCCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNNCCNCCCCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pTLfHLHLLTT 0600606600 0006060000 O #2084 pLLffffLfLLffffLfNNNNNNCCCCCCCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLffffLfNNNNNCCCCCCCCCCC 66000060660000606666666666666666 00000000000000006666666666666666 * #2084 pLHTf 6000 0600 P #2084 pLLffffLfLLffLLLfNNNNNCCCCCCCCCCC 66000060660066606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLLLLLLfNNNNNCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLLLLLLfNNNNCCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLLLLLLfNNNCCCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLLLLLLfNNCCCCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pLLffffLfLLLLLLLfNCCCCCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pTLLHLHLLTT 0660606600 0006060000 O #2084 pLLffffLfLLLLLLLfCCCCCCCCCCCCCCCC 66000060666666606666666666666666 00000000000000006666666666666666 * #2084 pLLffLLLfLLLLLLLfCCCCCCCCCCCCCCCC 66006660666666606666666666666666 00000000000000006666666666666666 * #2084 pLLfLLLLfLLLLLLLfCCCCCCCCCCCCCCCC 66066660666666606666666666666666 00000000000000006666666666666666 * #2084 pLLLLLLLfLLLLLLLfCCCCCCCCCCCCCCCC 66666660666666606666666666666666 00000000000000006666666666666666 * #2084 pLLLLLLLLLLLLLLLfCCCCCCCCCCCCCCCC 66666666666666606666666666666666 00000000000000006666666666666666 * #2085 pL 6 0 L #2085 pL 6 0 K #2085 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #2085 pDDDDDDDLHD 5555555605 0000000060 - #2085 pLHTL 6006 0600 P #2090 pU 6 6 ! #2095 pH 0 6 I #2099 pH 0 6 $ #2100 pD 6 0 ! #2110 pU 6 6 ! #2115 pL 6 0 I #2120 pD 6 0 ! #2121 pL 6 0 $ #2130 pU 6 6 ! #2135 pH 0 6 I #2139 pH 0 6 $ #2140 pD 6 0 ! #2150 pU 6 6 ! #2155 pL 6 0 I #2160 pD 6 0 ! #2161 pL 6 0 $ #2170 pU 6 6 ! #2174 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #2175 pH 0 6 I #2179 pH 0 6 $ #2180 pD 6 0 ! #2190 pU 6 6 ! #2195 pL 6 0 I #2200 pD 6 0 ! #2201 pL 6 0 $ #2210 pU 6 6 ! #2215 pH 0 6 I #2219 pH 0 6 $ #2220 pD 6 0 ! #2230 pU 6 6 ! #2235 pL 6 0 I #2240 pD 6 0 ! #2241 pL 6 0 $ #2250 pU 6 6 ! #2255 pH 0 6 I #2259 pH 0 6 $ #2260 pD 6 0 ! #2270 pU 6 6 ! #2275 pL 6 0 I #2279 pLLLLLUULLLLLL 6666600666666 0000066000000 A #2280 pD 6 0 ! #2281 pL 6 0 $ #2290 pU 6 6 ! #2295 pH 0 6 I #2299 pH 0 6 $ #2300 pD 6 0 ! #2310 pU 6 6 ! #2315 pL 6 0 I #2319 pLLLLLDULLLLLL 6666660666666 0000006000000 A #2320 pD 6 0 ! #2321 pL 6 0 $ #2330 pU 6 6 ! #2335 pH 0 6 I #2339 pH 0 6 $ #2340 pD 6 0 ! #2350 pU 6 6 ! #2355 pL 6 0 I #2359 pLfLLLLfLLLLLLLLLBBBBBBBBBBBBBBBB 60666606666666666666666666666666 00000000000000006666666666666666 * #2359 pffLLLLfLLLLLLLLLBBBBBBBBBBBBBBBB 00666606666666666666666666666666 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLLLBBBBBBBBBBBBBBBB 00666606006666666666666666666666 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBBBBBBBBBBB 00666606006666066666666666666666 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUBBBBBBBBB 00666606006666066666660666666666 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBBBBBB 00666606006666066666660066666666 00000000000000006666666666666666 * #2359 pf 0 0 S #2359 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #2359 pTfLHLHLLTT 0060606600 0006060000 O #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUBB 00666606006666066666660066666066 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUUB 00666606006666066666660066666006 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUUU 00666606006666066666660066666000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBBUUUU 00666606006666066666660066660000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBBUUUUU 00666606006666066666660066600000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBBUUUUUU 00666606006666066666660066000000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBBUUBUUUUUUU 00666606006666066666660060000000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBUUUBUUUUUUU 00666606006666066666600060000000 00000000000000006666666666666666 * #2359 pffLLLLfLffLLLLfLBBBBBUUUUUUUUUUU 00666606006666066666600000000000 00000000000000006666666666666666 * #2359 pTfLHLHLfTT 0060606000 0006060000 O #2359 pffLLLLfLffLLfffLBBBBBUUUUUUUUUUU 00666606006600066666600000000000 00000000000000006666666666666666 * #2359 pffLLLLfLfffffffLBBBBBUUUUUUUUUUU 00666606000000066666600000000000 00000000000000006666666666666666 * #2359 pffLLLLfLfffffffLBBBBUUUUUUUUUUUU 00666606000000066666000000000000 00000000000000006666666666666666 * #2359 pffLLLLfLfffffffLBBBUUUUUUUUUUUUU 00666606000000066660000000000000 00000000000000006666666666666666 * #2359 pffLLLLfLfffffffLBBUUUUUUUUUUUUUU 00666606000000066600000000000000 00000000000000006666666666666666 * #2359 pfHTL 0006 0600 P #2359 pffLLLLfLfffffffLBUUUUUUUUUUUUUUU 00666606000000066000000000000000 00000000000000006666666666666666 * #2359 pffLLLLfLfffffffLUUUUUUUUUUUUUUUU 00666606000000060000000000000000 00000000000000006666666666666666 * #2360 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #2360 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #2360 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #2360 pffLLfffLfffffffLUUUUUUUUUUUUUUUU 00660006000000060000000000000000 00000000000000006666666666666666 * #2360 pffLffffLfffffffLUUUUUUUUUUUUUUUU 00600006000000060000000000000000 00000000000000006666666666666666 * #2360 pfffffffLfffffffLUUUUUUUUUUUUUUUU 00000006000000060000000000000000 00000000000000006666666666666666 * #2360 pfffffffffffffffLUUUUUUUUUUUUUUUU 00000000000000060000000000000000 00000000000000006666666666666666 * #2360 pTfLHLHffTT 0060600000 0006060000 O #2360 pD 6 0 ! #2360 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #2360 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #2360 pTfLHfHffTT 0060000000 0006060000 O #2360 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #2360 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #2360 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #2360 pTffHfHffTT 0000000000 0006060000 O #2361 pf 0 0 K #2361 pDDDDDDDDHD 5555555505 0000000060 - #2361 pf 0 0 L #2361 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #2361 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #2361 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #2361 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #2361 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #2361 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #2361 pL 6 0 $ #2361 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #2361 pLLffffffffffffff 6600000000000000 0000000000000000 @ #2361 pLfffffffffffffff 6000000000000000 0000000000000000 @ #2361 pffffffffffffffff 0000000000000000 0000000000000000 @ #2361 pfHTf 0000 0600 P #2361 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #2361 pLLLLLUDfLLLff 6666606066600 0000060000000 A #2361 pLLLLLUDffLLff 6666606006600 0000060000000 A #2361 pLLLLLUDffLfff 6666606006000 0000060000000 A #2362 pLLLLLUDffffff 6666606000000 0000060000000 A #2364 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pUHTU 0000 6606 P pD 6 0 S #2370 pU 6 6 ! #2375 pH 0 6 I #2379 pH 0 6 $ #2380 pD 6 0 ! #2390 pU 6 6 ! #2395 pL 6 0 I #2396 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #2400 pffLfffffffffffff 0060000000000000 0000000000000000 @ #2400 pffLLffffffffffff 0066000000000000 0000000000000000 @ #2400 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #2400 pTffHLHffTT 0000600000 0006060000 O #2400 pD 6 0 ! #2400 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #2400 pLLLLLUDLfffff 6666606600000 0000060000000 A #2401 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #2401 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #2401 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #2401 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #2401 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #2401 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #2401 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #2401 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #2401 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #2401 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #2401 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #2401 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #2401 pLLLLLUDLfffLf 6666606600060 0000060000000 A #2401 pLLLLLUDLfffLL 6666606600066 0000060000000 A #2401 pL 6 0 $ #2401 pLLLLLUDLffLLL 6666606600666 0000060000000 A #2401 pLLLLLUDLLfLLL 6666606660666 0000060000000 A #2401 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #2403 pfLffffLfffffffffUUUUUUUUUUUUUUUU 06000060000000000000000000000000 00000000000000006666666666666666 * #2403 pLLffffLfffffffffUUUUUUUUUUUUUUUU 66000060000000000000000000000000 00000000000000006666666666666666 * #2403 pL 6 0 S #2403 pLLffffLfLLffffffUUUUUUUUUUUUUUUU 66000060660000000000000000000000 00000000000000006666666666666666 * #2403 pLLffffLfLLffffLfUUUUUUUUUUUUUUUU 66000060660000600000000000000000 00000000000000006666666666666666 * #2404 pTffHLHfLTT 0000600600 0006060000 O #2404 pTLfHLHfLTT 0600600600 0006060000 O #2404 pLLffffLfLLffffLfUUUUUUBUUUUUUUUU 66000060660000600000006000000000 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUUUUUU 66000060660000600000006600000000 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUUUBUU 66000060660000600000006600000600 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUUUBBU 66000060660000600000006600000660 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUUUBBB 66000060660000600000006600000666 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUUBBBB 66000060660000600000006600006666 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUUBBBBB 66000060660000600000006600066666 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUUBBBBBB 66000060660000600000006600666666 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUUBBUBBBBBBB 66000060660000600000006606666666 00000000000000006666666666666666 * #2404 pTLfHLHLLTT 0600606600 0006060000 O #2404 pLLffffLfLLffffLfUUUUUUBBBBBBBBBB 66000060660000600000006666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLffffLfUUUUUBBBBBBBBBBB 66000060660000600000066666666666 00000000000000006666666666666666 * #2404 pLHTf 6000 0600 P #2404 pLLffffLfLLffLLLfUUUUUBBBBBBBBBBB 66000060660066600000066666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLLLLLLfUUUUUBBBBBBBBBBB 66000060666666600000066666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLLLLLLfUUUUBBBBBBBBBBBB 66000060666666600000666666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLLLLLLfUUUBBBBBBBBBBBBB 66000060666666600006666666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLLLLLLfUUBBBBBBBBBBBBBB 66000060666666600066666666666666 00000000000000006666666666666666 * #2404 pLLffffLfLLLLLLLfUBBBBBBBBBBBBBBB 66000060666666600666666666666666 00000000000000006666666666666666 * #2404 pTLLHLHLLTT 0660606600 0006060000 O #2404 pLLffffLfLLLLLLLfBBBBBBBBBBBBBBBB 66000060666666606666666666666666 00000000000000006666666666666666 * #2404 pLLffLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66006660666666606666666666666666 00000000000000006666666666666666 * #2404 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66066660666666606666666666666666 00000000000000006666666666666666 * #2404 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66666660666666606666666666666666 00000000000000006666666666666666 * #2404 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBBBBB 66666666666666606666666666666666 00000000000000006666666666666666 * #2405 pL 6 0 L #2405 pL 6 0 K #2405 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #2405 pDDDDDDDLHD 5555555605 0000000060 - #2405 pLHTL 6006 0600 P #2410 pU 6 6 ! #2415 pH 0 6 I #2419 pH 0 6 $ #2420 pD 6 0 ! #2430 pU 6 6 ! #2435 pL 6 0 I #2440 pD 6 0 ! #2441 pL 6 0 $ #2448 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #2450 pU 6 6 ! #2455 pH 0 6 I #2459 pH 0 6 $ #2460 pD 6 0 ! #2470 pU 6 6 ! #2475 pL 6 0 I #2480 pD 6 0 ! #2481 pL 6 0 $ #2490 pU 6 6 ! #2494 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #2495 pH 0 6 I #2499 pH 0 6 $ #2500 pD 6 0 ! #2510 pU 6 6 ! #2515 pL 6 0 I #2520 pD 6 0 ! #2521 pL 6 0 $ #2530 pU 6 6 ! #2535 pH 0 6 I #2539 pH 0 6 $ #2540 pD 6 0 ! #2550 pU 6 6 ! #2555 pL 6 0 I #2560 pD 6 0 ! #2561 pL 6 0 $ #2570 pU 6 6 ! #2575 pH 0 6 I #2579 pH 0 6 $ #2580 pD 6 0 ! #2590 pU 6 6 ! #2595 pL 6 0 I #2600 pD 6 0 ! #2601 pL 6 0 $ #2610 pU 6 6 ! #2615 pH 0 6 I #2619 pH 0 6 $ #2620 pD 6 0 ! #2630 pU 6 6 ! #2635 pL 6 0 I #2640 pD 6 0 ! #2641 pL 6 0 $ #2650 pU 6 6 ! #2655 pH 0 6 I #2659 pH 0 6 $ #2660 pD 6 0 ! #2670 pU 6 6 ! #2675 pL 6 0 I #2680 pD 6 0 ! #2681 pL 6 0 $ #2690 pU 6 6 ! #2695 pH 0 6 I #2699 pH 0 6 $ #2700 pD 6 0 ! #2710 pU 6 6 ! #2715 pL 6 0 I #2720 pD 6 0 ! #2721 pL 6 0 $ #2730 pU 6 6 ! #2735 pH 0 6 I #2739 pH 0 6 $ #2740 pD 6 0 ! #2750 pU 6 6 ! #2755 pL 6 0 I #2760 pD 6 0 ! #2761 pL 6 0 $ #2770 pU 6 6 ! #2775 pH 0 6 I #2779 pH 0 6 $ #2780 pD 6 0 ! #2790 pU 6 6 ! #2795 pL 6 0 I #2800 pD 6 0 ! #2801 pL 6 0 $ #2810 pU 6 6 ! #2815 pH 0 6 I #2819 pH 0 6 $ #2820 pD 6 0 ! #2830 pU 6 6 ! #2835 pL 6 0 I #2839 pLLLLLUDLHLLLL 6666606606666 0000060060000 A #2839 pLLLLLUULHLLLL 6666600606666 0000066060000 A #2840 pD 6 0 ! #2841 pL 6 0 $ #2842 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #2842 pLLLLLLLLLLLLLLLLBBBBBBBB1BBBB1BB 66666666666666666666666606666066 00000000000000006666666666666666 * #2842 pLLLLLLLLLLLLLLLLBBBBBBB11BBBB1BB 66666666666666666666666006666066 00000000000000006666666666666666 * #2842 pTLLHLHLHTT 0660606000 0006060600 O #2842 pLHTH 6000 0606 P #2850 pU 6 6 ! #2855 pH 0 6 I #2859 pH 0 6 $ #2860 pD 6 0 ! #2870 pU 6 6 ! #2875 pL 6 0 I #2878 pLLLLLUULLLLLL 6666600666666 0000066000000 A #2879 pLLLLLDULLLLLL 6666660666666 0000006000000 A #2880 pD 6 0 ! #2881 pL 6 0 $ #2883 pLLLLLLLLLLLLLLLLBBBBBBB1BBBBB1BB 66666666666666666666666066666066 00000000000000006666666666666666 * #2883 pLLLLLLLLLLLLLLLLBBBBBBB1BBBBBBBB 66666666666666666666666066666666 00000000000000006666666666666666 * #2883 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #2883 pTLLHLHLLTT 0660606600 0006060000 O #2884 pLHTL 6006 0600 P #2890 pU 6 6 ! #2895 pH 0 6 I #2899 pH 0 6 $ #2900 pD 6 0 ! #2910 pU 6 6 ! #2915 pL 6 0 I #2919 pLfLLLLfLLLLLLLLLBBBBBBBBBBBBBBBB 60666606666666666666666666666666 00000000000000006666666666666666 * #2919 pffLLLLfLLLLLLLLLBBBBBBBBBBBBBBBB 00666606666666666666666666666666 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLLLBBBBBBBBBBBBBBBB 00666606006666666666666666666666 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBBBBBBBBBBB 00666606006666066666666666666666 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUBBBBBBBBB 00666606006666066666660666666666 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBBBBBB 00666606006666066666660066666666 00000000000000006666666666666666 * #2919 pf 0 0 S #2919 pTfLHLHLLTT 0060606600 0006060000 O #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUBB 00666606006666066666660066666066 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUUB 00666606006666066666660066666006 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBBBUUU 00666606006666066666660066666000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBBUUUU 00666606006666066666660066660000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBBUUUUU 00666606006666066666660066600000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBBUUUUUU 00666606006666066666660066000000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBBUUBUUUUUUU 00666606006666066666660060000000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBUUUBUUUUUUU 00666606006666066666600060000000 00000000000000006666666666666666 * #2919 pffLLLLfLffLLLLfLBBBBBUUUUUUUUUUU 00666606006666066666600000000000 00000000000000006666666666666666 * #2919 pTfLHLHLfTT 0060606000 0006060000 O #2919 pffLLLLfLffLLfffLBBBBBUUUUUUUUUUU 00666606006600066666600000000000 00000000000000006666666666666666 * #2919 pffLLLLfLfffffffLBBBBBUUUUUUUUUUU 00666606000000066666600000000000 00000000000000006666666666666666 * #2919 pffLLLLfLfffffffLBBBBUUUUUUUUUUUU 00666606000000066666000000000000 00000000000000006666666666666666 * #2919 pffLLLLfLfffffffLBBBUUUUUUUUUUUUU 00666606000000066660000000000000 00000000000000006666666666666666 * #2919 pffLLLLfLfffffffLBBUUUUUUUUUUUUUU 00666606000000066600000000000000 00000000000000006666666666666666 * #2919 pfHTL 0006 0600 P #2919 pffLLLLfLfffffffLBUUUUUUUUUUUUUUU 00666606000000066000000000000000 00000000000000006666666666666666 * #2919 pffLLLLfLfffffffLUUUUUUUUUUUUUUUU 00666606000000060000000000000000 00000000000000006666666666666666 * #2920 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #2920 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #2920 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #2920 pffLLfffLfffffffLUUUUUUUUUUUUUUUU 00660006000000060000000000000000 00000000000000006666666666666666 * #2920 pffLffffLfffffffLUUUUUUUUUUUUUUUU 00600006000000060000000000000000 00000000000000006666666666666666 * #2920 pfffffffLfffffffLUUUUUUUUUUUUUUUU 00000006000000060000000000000000 00000000000000006666666666666666 * #2920 pfffffffffffffffLUUUUUUUUUUUUUUUU 00000000000000060000000000000000 00000000000000006666666666666666 * #2920 pTfLHLHffTT 0060600000 0006060000 O #2920 pD 6 0 ! #2920 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #2920 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #2920 pTfLHfHffTT 0060000000 0006060000 O #2920 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #2920 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #2920 pLLLLLDUfLLLLL 6666660066666 0000006000000 A #2920 pTffHfHffTT 0000000000 0006060000 O #2921 pf 0 0 K #2921 pDDDDDDDDHD 5555555505 0000000060 - #2921 pf 0 0 L #2921 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #2921 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #2921 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #2921 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #2921 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #2921 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #2921 pL 6 0 $ #2921 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #2921 pLLffffffffffffff 6600000000000000 0000000000000000 @ #2921 pLfffffffffffffff 6000000000000000 0000000000000000 @ #2921 pffffffffffffffff 0000000000000000 0000000000000000 @ #2921 pfHTf 0000 0600 P #2921 pLLLLLDUfLLLfL 6666660066606 0000006000000 A #2921 pLLLLLDUfLLLff 6666660066600 0000006000000 A #2921 pLLLLLDUffLLff 6666660006600 0000006000000 A #2921 pLLLLLDUffLfff 6666660006000 0000006000000 A #2922 pLLLLLDUffffff 6666660000000 0000006000000 A #2924 pDUUUUDUUUUDUDUUD 6000060000606006 0666606666060660 @ pLLLLLDUUDDUDD 6666660066066 0000006600600 A pU 0 6 K pU 0 6 L pTUUHDHDDTT 0000606600 0666060000 O pDHTD 6006 0600 P pD 6 0 S #2930 pU 6 6 ! #2935 pH 0 6 I #2939 pH 0 6 $ #2940 pD 6 0 ! #2950 pU 6 6 ! #2955 pL 6 0 I #2959 pLLLLLUDUDDUDD 6666606066066 0000060600600 A #2960 pD 6 0 ! #2961 pL 6 0 $ #2964 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pDHTU 6000 0606 P #2970 pU 6 6 ! #2975 pH 0 6 I #2979 pH 0 6 $ #2980 pD 6 0 ! #2990 pU 6 6 ! #2995 pL 6 0 I #2996 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #2999 pLLLLLUUffffff 6666600000000 0000066000000 A #3000 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3000 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3000 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3000 pTffHLHffTT 0000600000 0006060000 O #3000 pD 6 0 ! #3000 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3000 pLLLLLUULfffff 6666600600000 0000066000000 A #3001 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3001 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3001 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3001 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3001 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3001 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3001 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3001 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3001 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3001 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3001 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3001 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3001 pLLLLLUULfffLf 6666600600060 0000066000000 A #3001 pLLLLLUULfffLL 6666600600066 0000066000000 A #3001 pL 6 0 $ #3001 pLLLLLUULffLLL 6666600600666 0000066000000 A #3001 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3001 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3003 pfLffffLfffffffffUUUUUUUUUUUUUUUU 06000060000000000000000000000000 00000000000000006666666666666666 * #3003 pLLffffLfffffffffUUUUUUUUUUUUUUUU 66000060000000000000000000000000 00000000000000006666666666666666 * #3003 pL 6 0 S #3003 pLLffffLfLLffffffUUUUUUUUUUUUUUUU 66000060660000000000000000000000 00000000000000006666666666666666 * #3003 pLLffffLfLLffffLfUUUUUUUUUUUUUUUU 66000060660000600000000000000000 00000000000000006666666666666666 * #3004 pTffHLHfLTT 0000600600 0006060000 O #3004 pTLfHLHfLTT 0600600600 0006060000 O #3004 pLLffffLfLLffffLfUUUUUUBUUUUUUUUU 66000060660000600000006000000000 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUUUUUU 66000060660000600000006600000000 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUUUBUU 66000060660000600000006600000600 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUUUBBU 66000060660000600000006600000660 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUUUBBB 66000060660000600000006600000666 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUUBBBB 66000060660000600000006600006666 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUUBBBBB 66000060660000600000006600066666 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUUBBBBBB 66000060660000600000006600666666 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUUBBUBBBBBBB 66000060660000600000006606666666 00000000000000006666666666666666 * #3004 pTLfHLHLLTT 0600606600 0006060000 O #3004 pLLffffLfLLffffLfUUUUUUBBBBBBBBBB 66000060660000600000006666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLffffLfUUUUUBBBBBBBBBBB 66000060660000600000066666666666 00000000000000006666666666666666 * #3004 pLHTf 6000 0600 P #3004 pLLffffLfLLffLLLfUUUUUBBBBBBBBBBB 66000060660066600000066666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLLLLLLfUUUUUBBBBBBBBBBB 66000060666666600000066666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLLLLLLfUUUUBBBBBBBBBBBB 66000060666666600000666666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLLLLLLfUUUBBBBBBBBBBBBB 66000060666666600006666666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLLLLLLfUUBBBBBBBBBBBBBB 66000060666666600066666666666666 00000000000000006666666666666666 * #3004 pLLffffLfLLLLLLLfUBBBBBBBBBBBBBBB 66000060666666600666666666666666 00000000000000006666666666666666 * #3004 pTLLHLHLLTT 0660606600 0006060000 O #3004 pLLffffLfLLLLLLLfBBBBBBBBBBBBBBBB 66000060666666606666666666666666 00000000000000006666666666666666 * #3004 pLLffLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66006660666666606666666666666666 00000000000000006666666666666666 * #3004 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66066660666666606666666666666666 00000000000000006666666666666666 * #3004 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66666660666666606666666666666666 00000000000000006666666666666666 * #3004 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBBBBB 66666666666666606666666666666666 00000000000000006666666666666666 * #3005 pL 6 0 L #3005 pL 6 0 K #3005 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #3005 pDDDDDDDLHD 5555555605 0000000060 - #3005 pLHTL 6006 0600 P #3008 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3010 pU 6 6 ! #3015 pH 0 6 I #3019 pH 0 6 $ #3020 pD 6 0 ! #3030 pU 6 6 ! #3035 pL 6 0 I #3039 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3040 pD 6 0 ! #3041 pL 6 0 $ #3050 pU 6 6 ! #3055 pH 0 6 I #3059 pH 0 6 $ #3060 pD 6 0 ! #3070 pU 6 6 ! #3075 pL 6 0 I #3079 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCCCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCCCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLLLCCCCCCCCCCCCCCCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCCCCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNCCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pf 0 0 S #3079 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3079 pTfLHLHLLTT 0060606600 0006060000 O #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCCNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCCNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCCNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCCNNCNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCNNNCNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3079 pTfLHLHLfTT 0060606000 0006060000 O #3079 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3079 pfHTL 0006 0600 P #3079 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3079 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3080 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3080 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3080 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3080 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3080 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3080 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3080 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3080 pTfLHLHffTT 0060600000 0006060000 O #3080 pD 6 0 ! #3080 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3080 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3080 pTfLHfHffTT 0060000000 0006060000 O #3080 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3080 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3080 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3080 pTffHfHffTT 0000000000 0006060000 O #3081 pf 0 0 K #3081 pDDDDDDDDHD 5555555505 0000000060 - #3081 pf 0 0 L #3081 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3081 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3081 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3081 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3081 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3081 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3081 pL 6 0 $ #3081 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3081 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3081 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3081 pffffffffffffffff 0000000000000000 0000000000000000 @ #3081 pfHTf 0000 0600 P #3081 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3081 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3081 pLLLLLUDffLLff 6666606006600 0000060000000 A #3081 pLLLLLUDffLfff 6666606006000 0000060000000 A #3082 pLLLLLUDffffff 6666606000000 0000060000000 A #3084 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pUHTU 0000 6606 P pD 6 0 S #3090 pU 6 6 ! #3094 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3095 pH 0 6 I #3099 pH 0 6 $ #3100 pD 6 0 ! #3110 pU 6 6 ! #3115 pL 6 0 I #3116 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3119 pLLLLLUUffffff 6666600000000 0000066000000 A #3120 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3120 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3120 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3120 pTffHLHffTT 0000600000 0006060000 O #3120 pD 6 0 ! #3120 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3120 pLLLLLUULfffff 6666600600000 0000066000000 A #3121 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3121 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3121 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3121 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3121 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3121 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3121 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3121 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3121 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3121 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3121 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3121 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3121 pLLLLLUULfffLf 6666600600060 0000066000000 A #3121 pLLLLLUULfffLL 6666600600066 0000066000000 A #3121 pL 6 0 $ #3121 pLLLLLUULffLLL 6666600600666 0000066000000 A #3121 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3121 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3123 pfLffffLfffffffffUUUUUUUUUUUUUUUU 06000060000000000000000000000000 00000000000000006666666666666666 * #3123 pLLffffLfffffffffUUUUUUUUUUUUUUUU 66000060000000000000000000000000 00000000000000006666666666666666 * #3123 pL 6 0 S #3123 pLLffffLfLLffffffUUUUUUUUUUUUUUUU 66000060660000000000000000000000 00000000000000006666666666666666 * #3123 pLLffffLfLLffffLfUUUUUUUUUUUUUUUU 66000060660000600000000000000000 00000000000000006666666666666666 * #3124 pTffHLHfLTT 0000600600 0006060000 O #3124 pTLfHLHfLTT 0600600600 0006060000 O #3124 pLLffffLfLLffffLfUUUUUUBUUUUUUUUU 66000060660000600000006000000000 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUUUUUU 66000060660000600000006600000000 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUUUBUU 66000060660000600000006600000600 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUUUBBU 66000060660000600000006600000660 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUUUBBB 66000060660000600000006600000666 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUUBBBB 66000060660000600000006600006666 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUUBBBBB 66000060660000600000006600066666 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUUBBBBBB 66000060660000600000006600666666 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUUBBUBBBBBBB 66000060660000600000006606666666 00000000000000006666666666666666 * #3124 pTLfHLHLLTT 0600606600 0006060000 O #3124 pLLffffLfLLffffLfUUUUUUBBBBBBBBBB 66000060660000600000006666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLffffLfUUUUUBBBBBBBBBBB 66000060660000600000066666666666 00000000000000006666666666666666 * #3124 pLHTf 6000 0600 P #3124 pLLffffLfLLffLLLfUUUUUBBBBBBBBBBB 66000060660066600000066666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLLLLLLfUUUUUBBBBBBBBBBB 66000060666666600000066666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLLLLLLfUUUUBBBBBBBBBBBB 66000060666666600000666666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLLLLLLfUUUBBBBBBBBBBBBB 66000060666666600006666666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLLLLLLfUUBBBBBBBBBBBBBB 66000060666666600066666666666666 00000000000000006666666666666666 * #3124 pLLffffLfLLLLLLLfUBBBBBBBBBBBBBBB 66000060666666600666666666666666 00000000000000006666666666666666 * #3124 pTLLHLHLLTT 0660606600 0006060000 O #3124 pLLffffLfLLLLLLLfBBBBBBBBBBBBBBBB 66000060666666606666666666666666 00000000000000006666666666666666 * #3124 pLLffLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66006660666666606666666666666666 00000000000000006666666666666666 * #3124 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66066660666666606666666666666666 00000000000000006666666666666666 * #3124 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66666660666666606666666666666666 00000000000000006666666666666666 * #3124 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBBBBB 66666666666666606666666666666666 00000000000000006666666666666666 * #3125 pL 6 0 L #3125 pL 6 0 K #3125 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #3125 pDDDDDDDLHD 5555555605 0000000060 - #3125 pLHTL 6006 0600 P #3130 pU 6 6 ! #3135 pH 0 6 I #3139 pH 0 6 $ #3140 pD 6 0 ! #3150 pU 6 6 ! #3155 pL 6 0 I #3159 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3160 pD 6 0 ! #3161 pL 6 0 $ #3168 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3170 pU 6 6 ! #3175 pH 0 6 I #3179 pH 0 6 $ #3180 pD 6 0 ! #3190 pU 6 6 ! #3195 pL 6 0 I #3199 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCCCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCCCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLLLCCCCCCCCCCCCCCCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCCCCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNCCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCCCCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pf 0 0 S #3199 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3199 pTfLHLHLLTT 0060606600 0006060000 O #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCCCNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCCNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCCNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCCNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCCNNCNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCNNNCNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3199 pTfLHLHLfTT 0060606000 0006060000 O #3199 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3199 pfHTL 0006 0600 P #3199 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3199 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3200 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3200 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3200 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3200 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3200 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3200 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3200 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3200 pTfLHLHffTT 0060600000 0006060000 O #3200 pD 6 0 ! #3200 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3200 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3200 pTfLHfHffTT 0060000000 0006060000 O #3200 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3200 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3200 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3200 pTffHfHffTT 0000000000 0006060000 O #3201 pf 0 0 K #3201 pDDDDDDDDHD 5555555505 0000000060 - #3201 pf 0 0 L #3201 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3201 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3201 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3201 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3201 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3201 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3201 pL 6 0 $ #3201 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3201 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3201 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3201 pffffffffffffffff 0000000000000000 0000000000000000 @ #3201 pfHTf 0000 0600 P #3201 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3201 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3201 pLLLLLUDffLLff 6666606006600 0000060000000 A #3201 pLLLLLUDffLfff 6666606006000 0000060000000 A #3202 pLLLLLUDffffff 6666606000000 0000060000000 A #3204 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pDHTU 6000 0606 P pD 6 0 S #3210 pU 6 6 ! #3214 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3215 pH 0 6 I #3219 pH 0 6 $ #3220 pD 6 0 ! #3230 pU 6 6 ! #3235 pL 6 0 I #3236 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3239 pLLLLLUUffffff 6666600000000 0000066000000 A #3240 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3240 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3240 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3240 pTffHLHffTT 0000600000 0006060000 O #3240 pD 6 0 ! #3240 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3240 pLLLLLUULfffff 6666600600000 0000066000000 A #3241 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3241 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3241 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3241 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3241 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3241 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3241 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3241 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3241 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3241 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3241 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3241 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3241 pLLLLLUULfffLf 6666600600060 0000066000000 A #3241 pLLLLLUULfffLL 6666600600066 0000066000000 A #3241 pL 6 0 $ #3241 pLLLLLUULffLLL 6666600600666 0000066000000 A #3241 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3241 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3243 pfLffffLfffffffffUUUUUUUUUUUUUUUU 06000060000000000000000000000000 00000000000000006666666666666666 * #3243 pLLffffLfffffffffUUUUUUUUUUUUUUUU 66000060000000000000000000000000 00000000000000006666666666666666 * #3243 pL 6 0 S #3243 pLLffffLfLLffffffUUUUUUUUUUUUUUUU 66000060660000000000000000000000 00000000000000006666666666666666 * #3243 pLLffffLfLLffffLfUUUUUUUUUUUUUUUU 66000060660000600000000000000000 00000000000000006666666666666666 * #3244 pTffHLHfLTT 0000600600 0006060000 O #3244 pTLfHLHfLTT 0600600600 0006060000 O #3244 pLLffffLfLLffffLfUUUUUUBUUUUUUUUU 66000060660000600000006000000000 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUUUUUU 66000060660000600000006600000000 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUUUBUU 66000060660000600000006600000600 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUUUBBU 66000060660000600000006600000660 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUUUBBB 66000060660000600000006600000666 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUUBBBB 66000060660000600000006600006666 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUUBBBBB 66000060660000600000006600066666 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUUBBBBBB 66000060660000600000006600666666 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUUBBUBBBBBBB 66000060660000600000006606666666 00000000000000006666666666666666 * #3244 pTLfHLHLLTT 0600606600 0006060000 O #3244 pLLffffLfLLffffLfUUUUUUBBBBBBBBBB 66000060660000600000006666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLffffLfUUUUUBBBBBBBBBBB 66000060660000600000066666666666 00000000000000006666666666666666 * #3244 pLHTf 6000 0600 P #3244 pLLffffLfLLffLLLfUUUUUBBBBBBBBBBB 66000060660066600000066666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLLLLLLfUUUUUBBBBBBBBBBB 66000060666666600000066666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLLLLLLfUUUUBBBBBBBBBBBB 66000060666666600000666666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLLLLLLfUUUBBBBBBBBBBBBB 66000060666666600006666666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLLLLLLfUUBBBBBBBBBBBBBB 66000060666666600066666666666666 00000000000000006666666666666666 * #3244 pLLffffLfLLLLLLLfUBBBBBBBBBBBBBBB 66000060666666600666666666666666 00000000000000006666666666666666 * #3244 pTLLHLHLLTT 0660606600 0006060000 O #3244 pLLffffLfLLLLLLLfBBBBBBBBBBBBBBBB 66000060666666606666666666666666 00000000000000006666666666666666 * #3244 pLLffLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66006660666666606666666666666666 00000000000000006666666666666666 * #3244 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66066660666666606666666666666666 00000000000000006666666666666666 * #3244 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBBBBB 66666660666666606666666666666666 00000000000000006666666666666666 * #3244 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBBBBB 66666666666666606666666666666666 00000000000000006666666666666666 * #3245 pL 6 0 L #3245 pL 6 0 K #3245 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBBBBB 66666666666666666666666666666666 00000000000000006666666666666666 * #3245 pDDDDDDDLHD 5555555605 0000000060 - #3245 pLHTL 6006 0600 P #3250 pU 6 6 ! #3255 pH 0 6 I #3259 pH 0 6 $ #3260 pD 6 0 ! #3270 pU 6 6 ! #3275 pL 6 0 I #3279 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3280 pD 6 0 ! #3281 pL 6 0 $ #3282 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3282 pLHTH 6000 0606 P #3288 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3290 pU 6 6 ! #3295 pH 0 6 I #3299 pH 0 6 $ #3300 pD 6 0 ! #3310 pU 6 6 ! #3315 pL 6 0 I #3319 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLLLCCCCCCCCCCCCCcCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCCCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pf 0 0 S #3319 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3319 pTfLHLHLLTT 0060606600 0006060000 O #3319 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCCCCNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCCCNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCCNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCCNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCNNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3319 pTfLHLHLfTT 0060606000 0006060000 O #3319 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3319 pfHTH 0000 0606 P #3319 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3319 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3320 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3320 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3320 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3320 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3320 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3320 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3320 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3320 pTfLHLHffTT 0060600000 0006060000 O #3320 pD 6 0 ! #3320 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3320 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3320 pTfLHfHffTT 0060000000 0006060000 O #3320 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3320 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3320 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3320 pTffHfHffTT 0000000000 0006060000 O #3321 pf 0 0 K #3321 pDDDDDDDDHD 5555555505 0000000060 - #3321 pf 0 0 L #3321 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3321 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3321 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3321 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3321 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3321 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3321 pL 6 0 $ #3321 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3321 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3321 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3321 pffffffffffffffff 0000000000000000 0000000000000000 @ #3321 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3321 pfHTf 0000 0600 P #3321 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3321 pLLLLLUDffLLff 6666606006600 0000060000000 A #3321 pLLLLLUDffLfff 6666606006000 0000060000000 A #3322 pLLLLLUDffffff 6666606000000 0000060000000 A #3324 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pUHTU 0000 6606 P pD 6 0 S #3330 pU 6 6 ! #3334 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3335 pH 0 6 I #3339 pH 0 6 $ #3340 pD 6 0 ! #3350 pU 6 6 ! #3355 pL 6 0 I #3356 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3359 pLLLLLUUffffff 6666600000000 0000066000000 A #3360 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3360 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3360 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3360 pTffHLHffTT 0000600000 0006060000 O #3360 pD 6 0 ! #3360 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3360 pLLLLLUULfffff 6666600600000 0000066000000 A #3361 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3361 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3361 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3361 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3361 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3361 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3361 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3361 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3361 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3361 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3361 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3361 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3361 pLLLLLUULfffLf 6666600600060 0000066000000 A #3361 pLLLLLUULfffLL 6666600600066 0000066000000 A #3361 pL 6 0 $ #3361 pLLLLLUULffLLL 6666600600666 0000066000000 A #3361 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3361 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3363 pffffffffffffffffUUUUUUUUUUUUU1UU 00000000000000000000000000000000 00000000000000006666666666666666 * #3363 pfLffffLfffffffffUUUUUUUUUUUUU1UU 06000060000000000000000000000000 00000000000000006666666666666666 * #3363 pLLffffLfffffffffUUUUUUUUUUUUU1UU 66000060000000000000000000000000 00000000000000006666666666666666 * #3363 pL 6 0 S #3363 pLLffffLfLLffffffUUUUUUUUUUUUU1UU 66000060660000000000000000000000 00000000000000006666666666666666 * #3363 pLLffffLfLLffffLfUUUUUUUUUUUUU1UU 66000060660000600000000000000000 00000000000000006666666666666666 * #3364 pTffHLHfLTT 0000600600 0006060000 O #3364 pTLfHLHfLTT 0600600600 0006060000 O #3364 pLLffffLfLLffffLfUUUUUUBUUUUUU1UU 66000060660000600000006000000000 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUUUU1UU 66000060660000600000006600000000 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUUUU1BU 66000060660000600000006600000060 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUUUU1BB 66000060660000600000006600000066 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUUUB1BB 66000060660000600000006600006066 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUUBB1BB 66000060660000600000006600066066 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUUBBB1BB 66000060660000600000006600666066 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUUBBUBBBB1BB 66000060660000600000006606666066 00000000000000006666666666666666 * #3364 pTLfHLHLLTT 0600606600 0006060000 O #3364 pLLffffLfLLffffLfUUUUUUBBBBBBB1BB 66000060660000600000006666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLffffLfUUUUUBBBBBBBB1BB 66000060660000600000066666666066 00000000000000006666666666666666 * #3364 pLHTf 6000 0600 P #3364 pLLffffLfLLffLLLfUUUUUBBBBBBBB1BB 66000060660066600000066666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLLLLLLfUUUUUBBBBBBBB1BB 66000060666666600000066666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLLLLLLfUUUUBBBBBBBBB1BB 66000060666666600000666666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLLLLLLfUUUBBBBBBBBBB1BB 66000060666666600006666666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLLLLLLfUUBBBBBBBBBBB1BB 66000060666666600066666666666066 00000000000000006666666666666666 * #3364 pLLffffLfLLLLLLLfUBBBBBBBBBBBB1BB 66000060666666600666666666666066 00000000000000006666666666666666 * #3364 pTLLHLHLLTT 0660606600 0006060000 O #3364 pLLffffLfLLLLLLLfBBBBBBBBBBBBB1BB 66000060666666606666666666666066 00000000000000006666666666666666 * #3364 pLLffLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66006660666666606666666666666066 00000000000000006666666666666666 * #3364 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66066660666666606666666666666066 00000000000000006666666666666666 * #3364 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66666660666666606666666666666066 00000000000000006666666666666666 * #3364 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBB1BB 66666666666666606666666666666066 00000000000000006666666666666666 * #3365 pL 6 0 L #3365 pL 6 0 K #3365 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3365 pDDDDDDDLHD 5555555605 0000000060 - #3365 pLHTH 6000 0606 P #3370 pU 6 6 ! #3375 pH 0 6 I #3379 pH 0 6 $ #3380 pD 6 0 ! #3390 pU 6 6 ! #3395 pL 6 0 I #3399 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3400 pD 6 0 ! #3401 pL 6 0 $ #3408 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3410 pU 6 6 ! #3415 pH 0 6 I #3419 pH 0 6 $ #3420 pD 6 0 ! #3430 pU 6 6 ! #3435 pL 6 0 I #3439 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLLLCCCCCCCCCCCCCcCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCCCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pf 0 0 S #3439 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3439 pTfLHLHLLTT 0060606600 0006060000 O #3439 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCCCCNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCCCNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCCNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCCNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCNNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3439 pTfLHLHLfTT 0060606000 0006060000 O #3439 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3439 pfHTH 0000 0606 P #3439 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3439 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3440 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3440 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3440 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3440 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3440 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3440 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3440 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3440 pTfLHLHffTT 0060600000 0006060000 O #3440 pD 6 0 ! #3440 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3440 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3440 pTfLHfHffTT 0060000000 0006060000 O #3440 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3440 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3440 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3440 pTffHfHffTT 0000000000 0006060000 O #3441 pf 0 0 K #3441 pDDDDDDDDHD 5555555505 0000000060 - #3441 pf 0 0 L #3441 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3441 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3441 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3441 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3441 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3441 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3441 pL 6 0 $ #3441 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3441 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3441 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3441 pffffffffffffffff 0000000000000000 0000000000000000 @ #3441 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3441 pfHTf 0000 0600 P #3441 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3441 pLLLLLUDffLLff 6666606006600 0000060000000 A #3441 pLLLLLUDffLfff 6666606006000 0000060000000 A #3442 pLLLLLUDffffff 6666606000000 0000060000000 A #3444 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pDHTU 6000 0606 P pD 6 0 S #3450 pU 6 6 ! #3454 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3455 pH 0 6 I #3459 pH 0 6 $ #3460 pD 6 0 ! #3470 pU 6 6 ! #3475 pL 6 0 I #3476 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3480 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3480 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3480 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3480 pTffHLHffTT 0000600000 0006060000 O #3480 pD 6 0 ! #3480 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3480 pLLLLLUDLfffff 6666606600000 0000060000000 A #3481 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3481 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3481 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3481 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3481 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3481 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3481 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3481 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3481 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3481 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3481 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3481 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3481 pLLLLLUDLfffLf 6666606600060 0000060000000 A #3481 pLLLLLUDLfffLL 6666606600066 0000060000000 A #3481 pL 6 0 $ #3481 pLLLLLUDLffLLL 6666606600666 0000060000000 A #3481 pLLLLLUDLLfLLL 6666606660666 0000060000000 A #3481 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3483 pffffffffffffffffUUUUUUUUUUUUU1UU 00000000000000000000000000000000 00000000000000006666666666666666 * #3483 pfLffffLfffffffffUUUUUUUUUUUUU1UU 06000060000000000000000000000000 00000000000000006666666666666666 * #3483 pLLffffLfffffffffUUUUUUUUUUUUU1UU 66000060000000000000000000000000 00000000000000006666666666666666 * #3483 pL 6 0 S #3483 pLLffffLfLLffffffUUUUUUUUUUUUU1UU 66000060660000000000000000000000 00000000000000006666666666666666 * #3483 pLLffffLfLLffffLfUUUUUUUUUUUUU1UU 66000060660000600000000000000000 00000000000000006666666666666666 * #3484 pTffHLHfLTT 0000600600 0006060000 O #3484 pTLfHLHfLTT 0600600600 0006060000 O #3484 pLLffffLfLLffffLfUUUUUUBUUUUUU1UU 66000060660000600000006000000000 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUUUU1UU 66000060660000600000006600000000 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUUUU1BU 66000060660000600000006600000060 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUUUU1BB 66000060660000600000006600000066 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUUUB1BB 66000060660000600000006600006066 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUUBB1BB 66000060660000600000006600066066 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUUBBB1BB 66000060660000600000006600666066 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUUBBUBBBB1BB 66000060660000600000006606666066 00000000000000006666666666666666 * #3484 pTLfHLHLLTT 0600606600 0006060000 O #3484 pLLffffLfLLffffLfUUUUUUBBBBBBB1BB 66000060660000600000006666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLffffLfUUUUUBBBBBBBB1BB 66000060660000600000066666666066 00000000000000006666666666666666 * #3484 pLHTf 6000 0600 P #3484 pLLffffLfLLffLLLfUUUUUBBBBBBBB1BB 66000060660066600000066666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLLLLLLfUUUUUBBBBBBBB1BB 66000060666666600000066666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLLLLLLfUUUUBBBBBBBBB1BB 66000060666666600000666666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLLLLLLfUUUBBBBBBBBBB1BB 66000060666666600006666666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLLLLLLfUUBBBBBBBBBBB1BB 66000060666666600066666666666066 00000000000000006666666666666666 * #3484 pLLffffLfLLLLLLLfUBBBBBBBBBBBB1BB 66000060666666600666666666666066 00000000000000006666666666666666 * #3484 pTLLHLHLLTT 0660606600 0006060000 O #3484 pLLffffLfLLLLLLLfBBBBBBBBBBBBB1BB 66000060666666606666666666666066 00000000000000006666666666666666 * #3484 pLLffLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66006660666666606666666666666066 00000000000000006666666666666666 * #3484 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66066660666666606666666666666066 00000000000000006666666666666666 * #3484 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66666660666666606666666666666066 00000000000000006666666666666666 * #3484 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBB1BB 66666666666666606666666666666066 00000000000000006666666666666666 * #3485 pL 6 0 L #3485 pL 6 0 K #3485 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3485 pDDDDDDDLHD 5555555605 0000000060 - #3485 pLHTH 6000 0606 P #3490 pU 6 6 ! #3495 pH 0 6 I #3499 pH 0 6 $ #3500 pD 6 0 ! #3510 pU 6 6 ! #3515 pL 6 0 I #3519 pLLLLLUDLHLLLL 6666606606666 0000060060000 A #3519 pLLLLLUULHLLLL 6666600606666 0000066060000 A #3520 pD 6 0 ! #3521 pL 6 0 $ #3522 pLLLLLLLLLLLLLLLLBBBBBBBB1BBBB1BB 66666666666666666666666606666066 00000000000000006666666666666666 * #3522 pLLLLLLLLLLLLLLLLBBBBBBB11BBBB1BB 66666666666666666666666006666066 00000000000000006666666666666666 * #3522 pTLLHLHLHTT 0660606000 0006060600 O #3528 pLLLLLLLLLLLLLLLLCCCCCCCccCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3530 pU 6 6 ! #3535 pH 0 6 I #3539 pH 0 6 $ #3540 pD 6 0 ! #3550 pU 6 6 ! #3555 pL 6 0 I #3558 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3559 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3560 pD 6 0 ! #3561 pL 6 0 $ #3563 pLLLLLLLLLLLLLLLLCCCCCCCcCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3563 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3563 pTLLHLHLLTT 0660606600 0006060000 O #3570 pU 6 6 ! #3574 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3575 pH 0 6 I #3579 pH 0 6 $ #3580 pD 6 0 ! #3590 pU 6 6 ! #3595 pL 6 0 I #3599 pLfLLLLfLLLLLLLLLBBBBBBBBBBBBB1BB 60666606666666666666666666666066 00000000000000006666666666666666 * #3599 pffLLLLfLLLLLLLLLBBBBBBBBBBBBB1BB 00666606666666666666666666666066 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLLLBBBBBBBBBBBBB1BB 00666606006666666666666666666066 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBBBBBBBB1BB 00666606006666066666666666666066 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUBBBBBB1BB 00666606006666066666660666666066 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBBBBB1BB 00666606006666066666660066666066 00000000000000006666666666666666 * #3599 pf 0 0 S #3599 pTfLHLHLLTT 0060606600 0006060000 O #3599 pffLLLLfLffLLLLfLBBBBBBUUBBBBB1UB 00666606006666066666660066666006 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBBBBB1UU 00666606006666066666660066666000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBBBBU1UU 00666606006666066666660066660000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBBBUU1UU 00666606006666066666660066600000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBBUUU1UU 00666606006666066666660066000000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBBUUBUUUU1UU 00666606006666066666660060000000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBUUUBUUUU1UU 00666606006666066666600060000000 00000000000000006666666666666666 * #3599 pffLLLLfLffLLLLfLBBBBBUUUUUUUUUUU 00666606006666066666600000000000 00000000000000006666666666666666 * #3599 pTfLHLHLfTT 0060606000 0006060000 O #3599 pffLLLLfLffLLfffLBBBBBUUUUUUUUUUU 00666606006600066666600000000000 00000000000000006666666666666666 * #3599 pffLLLLfLfffffffLBBBBBUUUUUUUUUUU 00666606000000066666600000000000 00000000000000006666666666666666 * #3599 pffLLLLfLfffffffLBBBBUUUUUUUUUUUU 00666606000000066666000000000000 00000000000000006666666666666666 * #3599 pffLLLLfLfffffffLBBBUUUUUUUUUUUUU 00666606000000066660000000000000 00000000000000006666666666666666 * #3599 pffLLLLfLfffffffLBBUUUUUUUUUUUUUU 00666606000000066600000000000000 00000000000000006666666666666666 * #3599 pfHTH 0000 0606 P #3599 pffLLLLfLfffffffLBUUUUUUUUUUUUUUU 00666606000000066000000000000000 00000000000000006666666666666666 * #3599 pffLLLLfLfffffffLUUUUUUUUUUUUUUUU 00666606000000060000000000000000 00000000000000006666666666666666 * #3600 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3600 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3600 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3600 pffLLfffLfffffffLUUUUUUUUUUUUUUUU 00660006000000060000000000000000 00000000000000006666666666666666 * #3600 pffLffffLfffffffLUUUUUUUUUUUUUUUU 00600006000000060000000000000000 00000000000000006666666666666666 * #3600 pfffffffLfffffffLUUUUUUUUUUUUUUUU 00000006000000060000000000000000 00000000000000006666666666666666 * #3600 pfffffffffffffffLUUUUUUUUUUUUUUUU 00000000000000060000000000000000 00000000000000006666666666666666 * #3600 pTfLHLHffTT 0060600000 0006060000 O #3600 pD 6 0 ! #3600 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3600 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3600 pTfLHfHffTT 0060000000 0006060000 O #3600 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3600 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3600 pLLLLLDUfLLLLL 6666660066666 0000006000000 A #3600 pTffHfHffTT 0000000000 0006060000 O #3601 pf 0 0 K #3601 pDDDDDDDDHD 5555555505 0000000060 - #3601 pf 0 0 L #3601 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3601 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3601 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3601 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3601 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3601 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3601 pL 6 0 $ #3601 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3601 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3601 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3601 pffffffffffffffff 0000000000000000 0000000000000000 @ #3601 pLLLLLDUfLLLfL 6666660066606 0000006000000 A #3601 pfHTf 0000 0600 P #3601 pLLLLLDUfLLLff 6666660066600 0000006000000 A #3601 pLLLLLDUffLLff 6666660006600 0000006000000 A #3601 pLLLLLDUffLfff 6666660006000 0000006000000 A #3602 pLLLLLDUffffff 6666660000000 0000006000000 A #3604 pDUUUUDUUUUDUDUUD 6000060000606006 0666606666060660 @ pLLLLLDUUDDUDD 6666660066066 0000006600600 A pU 0 6 K pU 0 6 L pTUUHDHDDTT 0000606600 0666060000 O pDHTD 6006 0600 P pD 6 0 S #3610 pU 6 6 ! #3615 pH 0 6 I #3619 pH 0 6 $ #3620 pD 6 0 ! #3630 pU 6 6 ! #3635 pL 6 0 I #3639 pLLLLLUDUDDUDD 6666606066066 0000060600600 A #3640 pD 6 0 ! #3641 pL 6 0 $ #3644 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pUHTU 0000 6606 P #3650 pU 6 6 ! #3655 pH 0 6 I #3659 pH 0 6 $ #3660 pD 6 0 ! #3670 pU 6 6 ! #3675 pL 6 0 I #3676 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3679 pLLLLLUUffffff 6666600000000 0000066000000 A #3680 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3680 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3680 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3680 pTffHLHffTT 0000600000 0006060000 O #3680 pD 6 0 ! #3680 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3680 pLLLLLUULfffff 6666600600000 0000066000000 A #3681 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3681 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3681 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3681 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3681 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3681 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3681 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3681 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3681 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3681 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3681 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3681 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3681 pLLLLLUULfffLf 6666600600060 0000066000000 A #3681 pLLLLLUULfffLL 6666600600066 0000066000000 A #3681 pL 6 0 $ #3681 pLLLLLUULffLLL 6666600600666 0000066000000 A #3681 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3681 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3683 pffffffffffffffffUUUUUUUUUUUUU1UU 00000000000000000000000000000000 00000000000000006666666666666666 * #3683 pfLffffLfffffffffUUUUUUUUUUUUU1UU 06000060000000000000000000000000 00000000000000006666666666666666 * #3683 pLLffffLfffffffffUUUUUUUUUUUUU1UU 66000060000000000000000000000000 00000000000000006666666666666666 * #3683 pL 6 0 S #3683 pLLffffLfLLffffffUUUUUUUUUUUUU1UU 66000060660000000000000000000000 00000000000000006666666666666666 * #3683 pLLffffLfLLffffLfUUUUUUUUUUUUU1UU 66000060660000600000000000000000 00000000000000006666666666666666 * #3684 pTffHLHfLTT 0000600600 0006060000 O #3684 pTLfHLHfLTT 0600600600 0006060000 O #3684 pLLffffLfLLffffLfUUUUUUBUUUUUU1UU 66000060660000600000006000000000 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUUUU1UU 66000060660000600000006600000000 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUUUU1BU 66000060660000600000006600000060 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUUUU1BB 66000060660000600000006600000066 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUUUB1BB 66000060660000600000006600006066 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUUBB1BB 66000060660000600000006600066066 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUUBBB1BB 66000060660000600000006600666066 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUUBBUBBBB1BB 66000060660000600000006606666066 00000000000000006666666666666666 * #3684 pTLfHLHLLTT 0600606600 0006060000 O #3684 pLLffffLfLLffffLfUUUUUUBBBBBBB1BB 66000060660000600000006666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLffffLfUUUUUBBBBBBBB1BB 66000060660000600000066666666066 00000000000000006666666666666666 * #3684 pLHTf 6000 0600 P #3684 pLLffffLfLLffLLLfUUUUUBBBBBBBB1BB 66000060660066600000066666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLLLLLLfUUUUUBBBBBBBB1BB 66000060666666600000066666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLLLLLLfUUUUBBBBBBBBB1BB 66000060666666600000666666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLLLLLLfUUUBBBBBBBBBB1BB 66000060666666600006666666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLLLLLLfUUBBBBBBBBBBB1BB 66000060666666600066666666666066 00000000000000006666666666666666 * #3684 pLLffffLfLLLLLLLfUBBBBBBBBBBBB1BB 66000060666666600666666666666066 00000000000000006666666666666666 * #3684 pTLLHLHLLTT 0660606600 0006060000 O #3684 pLLffffLfLLLLLLLfBBBBBBBBBBBBB1BB 66000060666666606666666666666066 00000000000000006666666666666666 * #3684 pLLffLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66006660666666606666666666666066 00000000000000006666666666666666 * #3684 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66066660666666606666666666666066 00000000000000006666666666666666 * #3684 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66666660666666606666666666666066 00000000000000006666666666666666 * #3684 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBB1BB 66666666666666606666666666666066 00000000000000006666666666666666 * #3685 pL 6 0 L #3685 pL 6 0 K #3685 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3685 pDDDDDDDLHD 5555555605 0000000060 - #3685 pLHTH 6000 0606 P #3688 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3690 pU 6 6 ! #3695 pH 0 6 I #3699 pH 0 6 $ #3700 pD 6 0 ! #3710 pU 6 6 ! #3715 pL 6 0 I #3719 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3720 pD 6 0 ! #3721 pL 6 0 $ #3730 pU 6 6 ! #3735 pH 0 6 I #3739 pH 0 6 $ #3740 pD 6 0 ! #3750 pU 6 6 ! #3755 pL 6 0 I #3759 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLLLCCCCCCCCCCCCCcCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCCCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pf 0 0 S #3759 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3759 pTfLHLHLLTT 0060606600 0006060000 O #3759 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCCCCNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCCCNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCCNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCCNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCNNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3759 pTfLHLHLfTT 0060606000 0006060000 O #3759 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3759 pfHTH 0000 0606 P #3759 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3759 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3760 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3760 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3760 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3760 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3760 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3760 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3760 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3760 pTfLHLHffTT 0060600000 0006060000 O #3760 pD 6 0 ! #3760 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3760 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3760 pTfLHfHffTT 0060000000 0006060000 O #3760 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3760 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3760 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3760 pTffHfHffTT 0000000000 0006060000 O #3761 pf 0 0 K #3761 pDDDDDDDDHD 5555555505 0000000060 - #3761 pf 0 0 L #3761 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3761 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3761 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3761 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3761 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3761 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3761 pL 6 0 $ #3761 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3761 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3761 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3761 pffffffffffffffff 0000000000000000 0000000000000000 @ #3761 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3761 pfHTf 0000 0600 P #3761 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3761 pLLLLLUDffLLff 6666606006600 0000060000000 A #3761 pLLLLLUDffLfff 6666606006000 0000060000000 A #3762 pLLLLLUDffffff 6666606000000 0000060000000 A #3764 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pDHTU 6000 0606 P pD 6 0 S #3770 pU 6 6 ! #3774 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3775 pH 0 6 I #3779 pH 0 6 $ #3780 pD 6 0 ! #3790 pU 6 6 ! #3795 pL 6 0 I #3796 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3799 pLLLLLUUffffff 6666600000000 0000066000000 A #3800 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3800 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3800 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3800 pTffHLHffTT 0000600000 0006060000 O #3800 pD 6 0 ! #3800 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3800 pLLLLLUULfffff 6666600600000 0000066000000 A #3801 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3801 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3801 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3801 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3801 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3801 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3801 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3801 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3801 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3801 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3801 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3801 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3801 pLLLLLUULfffLf 6666600600060 0000066000000 A #3801 pLLLLLUULfffLL 6666600600066 0000066000000 A #3801 pL 6 0 $ #3801 pLLLLLUULffLLL 6666600600666 0000066000000 A #3801 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3801 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3803 pffffffffffffffffUUUUUUUUUUUUU1UU 00000000000000000000000000000000 00000000000000006666666666666666 * #3803 pfLffffLfffffffffUUUUUUUUUUUUU1UU 06000060000000000000000000000000 00000000000000006666666666666666 * #3803 pLLffffLfffffffffUUUUUUUUUUUUU1UU 66000060000000000000000000000000 00000000000000006666666666666666 * #3803 pL 6 0 S #3803 pLLffffLfLLffffffUUUUUUUUUUUUU1UU 66000060660000000000000000000000 00000000000000006666666666666666 * #3803 pLLffffLfLLffffLfUUUUUUUUUUUUU1UU 66000060660000600000000000000000 00000000000000006666666666666666 * #3804 pTffHLHfLTT 0000600600 0006060000 O #3804 pTLfHLHfLTT 0600600600 0006060000 O #3804 pLLffffLfLLffffLfUUUUUUBUUUUUU1UU 66000060660000600000006000000000 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUUUU1UU 66000060660000600000006600000000 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUUUU1BU 66000060660000600000006600000060 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUUUU1BB 66000060660000600000006600000066 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUUUB1BB 66000060660000600000006600006066 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUUBB1BB 66000060660000600000006600066066 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUUBBB1BB 66000060660000600000006600666066 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUUBBUBBBB1BB 66000060660000600000006606666066 00000000000000006666666666666666 * #3804 pTLfHLHLLTT 0600606600 0006060000 O #3804 pLLffffLfLLffffLfUUUUUUBBBBBBB1BB 66000060660000600000006666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLffffLfUUUUUBBBBBBBB1BB 66000060660000600000066666666066 00000000000000006666666666666666 * #3804 pLHTf 6000 0600 P #3804 pLLffffLfLLffLLLfUUUUUBBBBBBBB1BB 66000060660066600000066666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLLLLLLfUUUUUBBBBBBBB1BB 66000060666666600000066666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLLLLLLfUUUUBBBBBBBBB1BB 66000060666666600000666666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLLLLLLfUUUBBBBBBBBBB1BB 66000060666666600006666666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLLLLLLfUUBBBBBBBBBBB1BB 66000060666666600066666666666066 00000000000000006666666666666666 * #3804 pLLffffLfLLLLLLLfUBBBBBBBBBBBB1BB 66000060666666600666666666666066 00000000000000006666666666666666 * #3804 pTLLHLHLLTT 0660606600 0006060000 O #3804 pLLffffLfLLLLLLLfBBBBBBBBBBBBB1BB 66000060666666606666666666666066 00000000000000006666666666666666 * #3804 pLLffLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66006660666666606666666666666066 00000000000000006666666666666666 * #3804 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66066660666666606666666666666066 00000000000000006666666666666666 * #3804 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66666660666666606666666666666066 00000000000000006666666666666666 * #3804 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBB1BB 66666666666666606666666666666066 00000000000000006666666666666666 * #3805 pL 6 0 L #3805 pL 6 0 K #3805 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3805 pDDDDDDDLHD 5555555605 0000000060 - #3805 pLHTH 6000 0606 P #3810 pU 6 6 ! #3815 pH 0 6 I #3819 pH 0 6 $ #3820 pD 6 0 ! #3830 pU 6 6 ! #3835 pL 6 0 I #3839 pLLLLLDULLLLLL 6666660666666 0000006000000 A #3840 pD 6 0 ! #3841 pL 6 0 $ #3848 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCCcCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3850 pU 6 6 ! #3855 pH 0 6 I #3859 pH 0 6 $ #3860 pD 6 0 ! #3870 pU 6 6 ! #3875 pL 6 0 I #3879 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLLLLLLLLLCCCCCCCCCCCCCcCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLLLCCCCCCCCCCCCCcCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCCCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNCCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pf 0 0 S #3879 pLLLLLUDLLLLLL 6666606666666 0000060000000 A #3879 pTfLHLHLLTT 0060606600 0006060000 O #3879 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCCCCCcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCCCCNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCCCNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCCNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCCNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCNNNCNNNNcNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3879 pTfLHLHLfTT 0060606000 0006060000 O #3879 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3879 pfHTH 0000 0606 P #3879 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3879 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3880 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #3880 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #3880 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #3880 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #3880 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #3880 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #3880 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #3880 pTfLHLHffTT 0060600000 0006060000 O #3880 pD 6 0 ! #3880 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #3880 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #3880 pTfLHfHffTT 0060000000 0006060000 O #3880 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #3880 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #3880 pLLLLLUDfLLLLL 6666606066666 0000060000000 A #3880 pTffHfHffTT 0000000000 0006060000 O #3881 pf 0 0 K #3881 pDDDDDDDDHD 5555555505 0000000060 - #3881 pf 0 0 L #3881 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #3881 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #3881 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #3881 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #3881 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #3881 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #3881 pL 6 0 $ #3881 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #3881 pLLffffffffffffff 6600000000000000 0000000000000000 @ #3881 pLfffffffffffffff 6000000000000000 0000000000000000 @ #3881 pffffffffffffffff 0000000000000000 0000000000000000 @ #3881 pLLLLLUDfLLLfL 6666606066606 0000060000000 A #3881 pfHTf 0000 0600 P #3881 pLLLLLUDfLLLff 6666606066600 0000060000000 A #3881 pLLLLLUDffLLff 6666606006600 0000060000000 A #3881 pLLLLLUDffLfff 6666606006000 0000060000000 A #3882 pLLLLLUDffffff 6666606000000 0000060000000 A #3884 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pUHTU 0000 6606 P pD 6 0 S #3890 pU 6 6 ! #3894 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #3895 pH 0 6 I #3899 pH 0 6 $ #3900 pD 6 0 ! #3910 pU 6 6 ! #3915 pL 6 0 I #3916 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #3919 pLLLLLUUffffff 6666600000000 0000066000000 A #3920 pffLfffffffffffff 0060000000000000 0000000000000000 @ #3920 pffLLffffffffffff 0066000000000000 0000000000000000 @ #3920 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #3920 pTffHLHffTT 0000600000 0006060000 O #3920 pD 6 0 ! #3920 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #3920 pLLLLLUULfffff 6666600600000 0000066000000 A #3921 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #3921 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #3921 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #3921 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #3921 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #3921 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #3921 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #3921 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #3921 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #3921 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #3921 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #3921 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #3921 pLLLLLUULfffLf 6666600600060 0000066000000 A #3921 pLLLLLUULfffLL 6666600600066 0000066000000 A #3921 pL 6 0 $ #3921 pLLLLLUULffLLL 6666600600666 0000066000000 A #3921 pLLLLLUULLfLLL 6666600660666 0000066000000 A #3921 pLLLLLUULLLLLL 6666600666666 0000066000000 A #3923 pffffffffffffffffUUUUUUUUUUUUU1UU 00000000000000000000000000000000 00000000000000006666666666666666 * #3923 pfLffffLfffffffffUUUUUUUUUUUUU1UU 06000060000000000000000000000000 00000000000000006666666666666666 * #3923 pLLffffLfffffffffUUUUUUUUUUUUU1UU 66000060000000000000000000000000 00000000000000006666666666666666 * #3923 pL 6 0 S #3923 pLLffffLfLLffffffUUUUUUUUUUUUU1UU 66000060660000000000000000000000 00000000000000006666666666666666 * #3923 pLLffffLfLLffffLfUUUUUUUUUUUUU1UU 66000060660000600000000000000000 00000000000000006666666666666666 * #3924 pTffHLHfLTT 0000600600 0006060000 O #3924 pTLfHLHfLTT 0600600600 0006060000 O #3924 pLLffffLfLLffffLfUUUUUUBUUUUUU1UU 66000060660000600000006000000000 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUUUU1UU 66000060660000600000006600000000 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUUUU1BU 66000060660000600000006600000060 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUUUU1BB 66000060660000600000006600000066 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUUUB1BB 66000060660000600000006600006066 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUUBB1BB 66000060660000600000006600066066 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUUBBB1BB 66000060660000600000006600666066 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUUBBUBBBB1BB 66000060660000600000006606666066 00000000000000006666666666666666 * #3924 pTLfHLHLLTT 0600606600 0006060000 O #3924 pLLffffLfLLffffLfUUUUUUBBBBBBB1BB 66000060660000600000006666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLffffLfUUUUUBBBBBBBB1BB 66000060660000600000066666666066 00000000000000006666666666666666 * #3924 pLHTf 6000 0600 P #3924 pLLffffLfLLffLLLfUUUUUBBBBBBBB1BB 66000060660066600000066666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLLLLLLfUUUUUBBBBBBBB1BB 66000060666666600000066666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLLLLLLfUUUUBBBBBBBBB1BB 66000060666666600000666666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLLLLLLfUUUBBBBBBBBBB1BB 66000060666666600006666666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLLLLLLfUUBBBBBBBBBBB1BB 66000060666666600066666666666066 00000000000000006666666666666666 * #3924 pLLffffLfLLLLLLLfUBBBBBBBBBBBB1BB 66000060666666600666666666666066 00000000000000006666666666666666 * #3924 pTLLHLHLLTT 0660606600 0006060000 O #3924 pLLffffLfLLLLLLLfBBBBBBBBBBBBB1BB 66000060666666606666666666666066 00000000000000006666666666666666 * #3924 pLLffLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66006660666666606666666666666066 00000000000000006666666666666666 * #3924 pLLfLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66066660666666606666666666666066 00000000000000006666666666666666 * #3924 pLLLLLLLfLLLLLLLfBBBBBBBBBBBBB1BB 66666660666666606666666666666066 00000000000000006666666666666666 * #3924 pLLLLLLLLLLLLLLLfBBBBBBBBBBBBB1BB 66666666666666606666666666666066 00000000000000006666666666666666 * #3925 pL 6 0 L #3925 pL 6 0 K #3925 pLLLLLLLLLLLLLLLLBBBBBBBBBBBBB1BB 66666666666666666666666666666066 00000000000000006666666666666666 * #3925 pDDDDDDDLHD 5555555605 0000000060 - #3925 pLHTH 6000 0606 P #3930 pU 6 6 ! #3935 pH 0 6 I #3939 pH 0 6 $ #3940 pD 6 0 ! #3950 pU 6 6 ! #3955 pL 6 0 I #3959 pLLLLLUULLLHLL 6666600666066 0000066000600 A #3959 pLLLLLDULLLHLL 6666660666066 0000006000600 A #3960 pD 6 0 ! #3961 pL 6 0 $ #3962 pLLLLLLLLLLLLLLLLBBBBBBBBBBBB11BB 66666666666666666666666666660066 00000000000000006666666666666666 * #3963 pLLLLLLLLLLLLLLLLBBBBBBBBBBBB1BBB 66666666666666666666666666660666 00000000000000006666666666666666 * #3964 pLHTL 6006 0600 P #3968 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCcCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #3970 pU 6 6 ! #3975 pH 0 6 I #3979 pH 0 6 $ #3980 pD 6 0 ! #3990 pU 6 6 ! #3995 pL 6 0 I #3999 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCcCCC 60666606666666666666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLLLLLLLLLCCCCCCCCCCCCcCCC 00666606666666666666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLLLCCCCCCCCCCCCcCCC 00666606006666666666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCCCCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNCCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pf 0 0 S #3999 pLLLLLUDLLLHLL 6666606666066 0000060000600 A #3999 pTfLHLHLLTT 0060606600 0006060000 O #3999 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNCC 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNNC 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCCCNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCCNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCCNNCNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCNNNCNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCNNNNNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #3999 pTfLHLHLfTT 0060606000 0006060000 O #3999 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3999 pfHTL 0006 0600 P #3999 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #3999 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4000 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #4000 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #4000 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #4000 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #4000 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #4000 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #4000 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #4000 pTfLHLHffTT 0060600000 0006060000 O #4000 pD 6 0 ! #4000 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #4000 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #4000 pTfLHfHffTT 0060000000 0006060000 O #4000 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #4000 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #4000 pLLLLLUDfLLHLL 6666606066066 0000060000600 A #4000 pTffHfHffTT 0000000000 0006060000 O #4001 pf 0 0 K #4001 pDDDDDDDDHD 5555555505 0000000060 - #4001 pf 0 0 L #4001 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #4001 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #4001 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #4001 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #4001 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #4001 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #4001 pLLLLLUDfLLfLL 6666606066066 0000060000000 A #4001 pL 6 0 $ #4001 pLLffffffffffffLf 6600000000000060 0000000000000000 @ #4001 pLLffffffffffffff 6600000000000000 0000000000000000 @ #4001 pLfffffffffffffff 6000000000000000 0000000000000000 @ #4001 pffffffffffffffff 0000000000000000 0000000000000000 @ #4001 pfHTf 0000 0600 P #4001 pLLLLLUDfLLffL 6666606066006 0000060000000 A #4001 pLLLLLUDfLLfff 6666606066000 0000060000000 A #4001 pLLLLLUDffLfff 6666606006000 0000060000000 A #4002 pLLLLLUDffffff 6666606000000 0000060000000 A #4004 pDDDUUDUUDDUDDDUD 6660060066066606 0006606600600060 @ pLLLLLUDDDDDDU 6666606666660 0000060000006 A pD 6 0 K pD 6 0 L pTDUHDHDDTT 0600606600 0066060000 O pDHTU 6000 0606 P pD 6 0 S #4010 pU 6 6 ! #4014 pffffffffffffffffUUUUUUUUUUUUUUUU 00000000000000000000000000000000 00000000000000006666666666666666 * #4015 pH 0 6 I #4019 pH 0 6 $ #4020 pD 6 0 ! #4030 pU 6 6 ! #4035 pL 6 0 I #4036 pffffffffffffffff 0000000000000000 0000000000000000 @ pLLLLLUDffffff 6666606000000 0000060000000 A pf 0 0 K pf 0 0 L pTffHfHffTT 0000000000 0006060000 O pfHTf 0000 0600 P pf 0 0 S #4039 pLLLLLUUffffff 6666600000000 0000066000000 A #4040 pffLfffffffffffff 0060000000000000 0000000000000000 @ #4040 pffLLffffffffffff 0066000000000000 0000000000000000 @ #4040 pffLLLfffffffffff 0066600000000000 0000000000000000 @ #4040 pTffHLHffTT 0000600000 0006060000 O #4040 pD 6 0 ! #4040 pffLLLLffffffffff 0066660000000000 0000000000000000 @ #4040 pLLLLLUULfffff 6666600600000 0000066000000 A #4041 pffLLLLLfffffffff 0066666000000000 0000000000000000 @ #4041 pffLLLLLLffffffff 0066666600000000 0000000000000000 @ #4041 pffLLLLLLffLfffff 0066666600600000 0000000000000000 @ #4041 pffLLLLLLLfLfffff 0066666660600000 0000000000000000 @ #4041 pffLLLLLLLfLffLff 0066666660600600 0000000000000000 @ #4041 pffLLLLLLLfLfLLff 0066666660606600 0000000000000000 @ #4041 pffLLLLLLLfLLLLff 0066666660666600 0000000000000000 @ #4041 pffLLLLLLLLLLLLff 0066666666666600 0000000000000000 @ #4041 pffLLLLLLLLLLLLfL 0066666666666606 0000000000000000 @ #4041 pffLLLLLLLLLLLLLL 0066666666666666 0000000000000000 @ #4041 pfLLLLLLLLLLLLLLL 0666666666666666 0000000000000000 @ #4041 pLLLLLLLLLLLLLLLL 6666666666666666 0000000000000000 @ #4041 pLLLLLUULfffLf 6666600600060 0000066000000 A #4041 pLLLLLUULfffLL 6666600600066 0000066000000 A #4041 pL 6 0 $ #4041 pLLLLLUULLffLL 6666600660066 0000066000000 A #4041 pLLLLLUULLLfLL 6666600666066 0000066000000 A #4042 pLLLLLUULLLHLL 6666600666066 0000066000600 A #4043 pfLffffLfffffffffUUUUUUUUUUUUUUUU 06000060000000000000000000000000 00000000000000006666666666666666 * #4043 pLLffffLfffffffffUUUUUUUUUUUUUUUU 66000060000000000000000000000000 00000000000000006666666666666666 * #4043 pL 6 0 S #4043 pLLffffLfLLffffffUUUUUUUUUUUUUUUU 66000060660000000000000000000000 00000000000000006666666666666666 * #4043 pLLffffLfLLffffLfUUUUUUUUUUUUUUUU 66000060660000600000000000000000 00000000000000006666666666666666 * #4044 pTffHLHfLTT 0000600600 0006060000 O #4044 pLLffffLfLLffffLfUUUUUUUUUUUU1UUU 66000060660000600000000000000000 00000000000000006666666666666666 * #4044 pTLfHLHfLTT 0600600600 0006060000 O #4044 pLLffffLfLLffffLfUUUUUUBUUUUU1UUU 66000060660000600000006000000000 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUUU1UUU 66000060660000600000006600000000 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUUU1BUU 66000060660000600000006600000600 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUUU1BBU 66000060660000600000006600000660 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUUU1BBB 66000060660000600000006600000666 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUUB1BBB 66000060660000600000006600060666 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUUBB1BBB 66000060660000600000006600660666 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUUBBUBBB1BBB 66000060660000600000006606660666 00000000000000006666666666666666 * #4044 pTLfHLHLLTT 0600606600 0006060000 O #4044 pLLffffLfLLffffLfUUUUUUBBBBBB1BBB 66000060660000600000006666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLffffLfUUUUUBBBBBBB1BBB 66000060660000600000066666660666 00000000000000006666666666666666 * #4044 pLHTf 6000 0600 P #4044 pLLffffLfLLffLLLfUUUUUBBBBBBB1BBB 66000060660066600000066666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLLLLLLfUUUUUBBBBBBB1BBB 66000060666666600000066666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLLLLLLfUUUUBBBBBBBB1BBB 66000060666666600000666666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLLLLLLfUUUBBBBBBBBB1BBB 66000060666666600006666666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLLLLLLfUUBBBBBBBBBB1BBB 66000060666666600066666666660666 00000000000000006666666666666666 * #4044 pLLffffLfLLLLLLLfUBBBBBBBBBBB1BBB 66000060666666600666666666660666 00000000000000006666666666666666 * #4044 pTLLHLHLLTT 0660606600 0006060000 O #4044 pLLffffLfLLLLLLLfBBBBBBBBBBBB1BBB 66000060666666606666666666660666 00000000000000006666666666666666 * #4044 pLLffLLLfLLLLLLLfBBBBBBBBBBBB1BBB 66006660666666606666666666660666 00000000000000006666666666666666 * #4044 pLLfLLLLfLLLLLLLfBBBBBBBBBBBB1BBB 66066660666666606666666666660666 00000000000000006666666666666666 * #4044 pLLLLLLLfLLLLLLLfBBBBBBBBBBBB1BBB 66666660666666606666666666660666 00000000000000006666666666666666 * #4044 pLLLLLLLLLLLLLLLfBBBBBBBBBBBB1BBB 66666666666666606666666666660666 00000000000000006666666666666666 * #4045 pL 6 0 L #4045 pL 6 0 K #4045 pLLLLLLLLLLLLLLLLBBBBBBBBBBBB1BBB 66666666666666666666666666660666 00000000000000006666666666666666 * #4045 pDDDDDDDLHD 5555555605 0000000060 - #4045 pLHTL 6006 0600 P #4050 pU 6 6 ! #4055 pH 0 6 I #4059 pH 0 6 $ #4060 pD 6 0 ! #4070 pU 6 6 ! #4075 pL 6 0 I #4079 pLLLLLDULLLHLL 6666660666066 0000006000600 A #4080 pD 6 0 ! #4081 pL 6 0 $ #4088 pLLLLLLLLLLLLLLLLCCCCCCCCCCCCcCCC 66666666666666666666666666666666 00000000000000006666666666666666 * #4090 pU 6 6 ! #4095 pH 0 6 I #4099 pH 0 6 $ #4100 pD 6 0 ! #4110 pU 6 6 ! #4115 pL 6 0 I #4119 pLfLLLLfLLLLLLLLLCCCCCCCCCCCCcCCC 60666606666666666666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLLLLLLLLLCCCCCCCCCCCCcCCC 00666606666666666666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLLLCCCCCCCCCCCCcCCC 00666606006666666666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCCCCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNCCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCCCCcCCC 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pf 0 0 S #4119 pLLLLLUDLLLHLL 6666606666066 0000060000600 A #4119 pTfLHLHLLTT 0060606600 0006060000 O #4119 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNCC 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNNC 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCCCCcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCCCNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCCNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCCNNCNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCNNNCNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCNNNNNNNcNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLffLLLLfLCCCCCNNNNNNNNNNN 00666606006666066666666666666666 00000000000000006666666666666666 * #4119 pTfLHLHLfTT 0060606000 0006060000 O #4119 pffLLLLfLffLLfffLCCCCCNNNNNNNNNNN 00666606006600066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLfffffffLCCCCCNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLfffffffLCCCCNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLfffffffLCCCNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLfffffffLCCNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4119 pfHTL 0006 0600 P #4119 pffLLLLfLfffffffLCNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4119 pffLLLLfLfffffffLNNNNNNNNNNNNNNNN 00666606000000066666666666666666 00000000000000006666666666666666 * #4120 pLLfLLLLLLLLLLLLL 6606666666666666 0000000000000000 @ #4120 pLLffLLLLLLLLLLLL 6600666666666666 0000000000000000 @ #4120 pLLfffLLLLLLLLLLL 6600066666666666 0000000000000000 @ #4120 pffLLfffLfffffffLNNNNNNNNNNNNNNNN 00660006000000066666666666666666 00000000000000006666666666666666 * #4120 pffLffffLfffffffLNNNNNNNNNNNNNNNN 00600006000000066666666666666666 00000000000000006666666666666666 * #4120 pfffffffLfffffffLNNNNNNNNNNNNNNNN 00000006000000066666666666666666 00000000000000006666666666666666 * #4120 pfffffffffffffffLNNNNNNNNNNNNNNNN 00000000000000066666666666666666 00000000000000006666666666666666 * #4120 pTfLHLHffTT 0060600000 0006060000 O #4120 pD 6 0 ! #4120 pLLfffLLLLLfLLLLL 6600066666066666 0000000000000000 @ #4120 pLLfffLLLfLfLLLLL 6600066606066666 0000000000000000 @ #4120 pTfLHfHffTT 0060000000 0006060000 O #4120 pffffffffffffffffNNNNNNNNNNNNNNNN 00000000000000006666666666666666 00000000000000006666666666666666 * #4120 pLLffffLLfLfLLLLL 6600006606066666 0000000000000000 @ #4120 pLLLLLUDfLLHLL 6666606066066 0000060000600 A #4120 pTffHfHffTT 0000000000 0006060000 O #4121 pf 0 0 K #4121 pDDDDDDDDHD 5555555505 0000000060 - #4121 pf 0 0 L #4121 pLLfffffLfLfLLLLL 6600000606066666 0000000000000000 @ #4121 pLLfffffffLfLLLLL 6600000006066666 0000000000000000 @ #4121 pLLfffffffLfLLfLL 6600000006066066 0000000000000000 @ #4121 pLLfffffffLfLffLL 6600000006060066 0000000000000000 @ #4121 pLLfffffffLffffLL 6600000006000066 0000000000000000 @ #4121 pLLffffffffffffLL 6600000000000066 0000000000000000 @ #4121 pLLLLLUDfLLfLL 6666606066066 0000060000000 A 0000000000066 0000000000000000 @ #4001 pLLLLLUDfLLfLL 6666606066066 0000060000000 A #4001 pL 6 0 $ #4001 pLLfINTERFACES/FSDB/FSDBVERILOG/exp1fsdb2vcd.vtran000064400001440000012000000051011103104161000211440ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Novas FSDB # # translating to Verilog Test Bench. # # Translation: FSDB < to > Test Bench # # Original File: "exp1.vcd.fsdb" # # Target File: "exp1out.vcd " # # Command File: "exp12vcd.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp1.vcd.fsdb"; {#### INPUT VECTOR FILE ####} script_format novas_fsdb ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FSDB # # vector data to translate into Verilog Test Bench format # #======================================================================# } proc_block begin; { #### state character translations for 'FSDB'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/FSDB/FSDBVERILOG/exp2fsdb2vcd.vtran000064400001440000012000000051021103104161000211460ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Novas FSDB # # translating to Verilog Test Bench. # # Translation: FSDB < to > Test Bench # # Original File: "exp2.evcd.fsdb" # # Target File: "exp2.ver " # # Command File: "exp22vcd.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp2.evcd.fsdb"; {#### INPUT VECTOR FILE ####} script_format novas_fsdb ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FSDB # # vector data to translate into Verilog Test Bench format # #======================================================================# } proc_block begin; { #### state character translations for 'FSDB'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp2.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/FSDB/FSDBVERILOG/exp2.evcd.fsdb000064400001440000012000000150601103104161000202400ustar00jcosleystaff00000400000023HÙ>EZv™/1nsSep 12, 2003 09:56:21Leapfrogf¾@ÿÿÿÿÿÿÿÿ/’IÿI Tue Nov 14 18:08:25 2006unknownsun4uSunOS5.7 Generic_106541-02FSDB_ENV_SYNC_CONTROL=NULL, FSDB_ENV_DUMP_SEQ_NUM=NULL, FSDB_ENV_MAX_GLITCH_NUM=NULL, FSDB_ENV_WRITER_MEM_LIMIT=NULL, FSDB_ENV_NOVAS_LOCK=NULL, FSDB_ENV_LOCK_FILE_LOC=NULLident_ffw_SOL2_DEB_6.1_4.1_SUNOS5.8_/opt/SUNWspro42/SC4.2/bin/cc_10172006 þsystem`topE ýýÿ! ¿clki@h2x@vcxo_ctrl@bX o@test@RopHdevid[3:0]AOsp_only@hrst_@ a1… Xc13@ ˆ1@ q9_0[9‡ fa22@ˆJ uart_rËt Wsbp@ˆ n@em1_N@î&e&aeîer@»crs@Ëo³rÓî&y&v@ìr®mdc@ëiM md[15€ Ma[12Ž ![b[® "mì#Lras $ c‰%Swe&\cs_ø'nke@(hx)gpio42_40[42:4GE*(*¶38@+Ê] ,¬26@-Ê5@.Õ 2_13[22:13B /¬8_5[8:5U0Ê@1É@2³R3L½4c5m 6d7gV 8afetx0@9Šrj:Ê];mfe_sƒ<ítb@=Ìji>(ou ?O on_don @¬Š A¸„BPregenCdvDEssHEpllT@Fªs^GR•Hªss@Iÿ!f d (JD * MJÁ&X P+‘," Ï`I ! ' w\)Qp ÁPf¡V¡8?Ðã@(  û.3V=v9Â1†'9?a\`a'3abæ ƒ+q +;)>ƒª¨)5+‚ `;ªiâce¡o>ƒ=,>†X=ƒ f;Â_°¡i-;b)>/f;>ƒ;bY/:+‚f;¹³¡ô' EU+½7> =; k< ˆ9?U.9?a>‰\ ``é©) /Â$ c[ S½  [ =?pG= 9¨ 7?C7=¡?m 7?< E !p pU%=*/.áþ+,'(/7] ™C äX”VH/)9ñ <  - y -1,% mAþb÷#) 172â 17)?v=  ³>7? 2' l 2'÷ â2' l ã'ú{ û}=5J¸ æ ¡>7 '<  0 l'b|¾)bm¿æÅ4b‚/_('cá[îá`V¶+—–O+­,+Í+íT+ÛL+; int38 ”&,? 02z+.%{." P,Y {**4m+bn}Ϫ&,+G:*?¼Va'2*+2b)së  Pf;Nf¤Í¬gëaS'#/Â/+Âj71¡0¢á `+PëP¥ r0eêõb ?i+4/>/Kðfì«£áW?Lû}¥'g H’¥¡ þå+ ­q( hµO &5a« ÕRw o=)-b¤Q*a7AµO¡ '5–f `+]'p+:€ù!•§³+( >/()Uy, *v¡¼'Âv!—°'$%ï/]N+)1WT+ÿTa‹¿ömG+Fhó¼#—g!' /]'§X):(I¼'3,E+:+K+)#*4+¼'ÂÆ)W $8™¡R,'4d',/,4'›2%(›0.+(.? @¢¶'7¡ %ž!wµ''/?(/?(<|6"¼4"üá*"y§¥*kg+ > ,+ (.¾ '0'Â&' d'| Œ> G" $) ¨$#Å4"ü*mi64&ü2&¢K &* -"°4ç(}''% 1?i¥¨ÆÄäIôt ­Èm-c !Í+_s *f",Ï+D+Q SÒ!!å!«å & ³P$ âD a&#¶'wWjŽe'Jâpo' jÝy'Až‹Ú³JœSi+P²(™L/- Tt 0)+AF–k Ð|bž]1'* |#‹¡eélùS¬£_cúAyöí VØm¡Ãö¶R¢4#–Z'cû ](yÊ'M?jkzªHÉj!~• b¿',JCjpC>BµªpS*&–#3'Ä £J3  %5 D%'g%«j)  aÎ- vr3':Ï   4 U¯jj :<> v&14 +ðXU'qgVjör'@4!+¢ƒ`sA³£`“Hisºg+( ž_ ,$'7.¬(Qp)0.3m_ ) p -[W82.*2s-6.Q))X(L(d(48 !P k)kw:Ï« C ˜'¤ ©(Lº(L×( è€kþª]Ë$\ckmow~[C&Û'¤&ì(Lý' '''K$k5(LK(ð\Wk„'¸'•(L¦(p·(LÈ(LÙ(Lö'Œ((Ìkk((:jJÃ2_ËA ök& o w;{cL(L](Ìn wkŠw‹›Ò¬VwDþccE W2ÃF!k1ËG£sG3'4GDZQJ{ N’hOKQþ'¤R'R V0ÃS'”S((L9(LJ(Ì[ k kl w k}(dŽ(LŸ(L°(pÁ(LÒ(äãkkô' TksTKKk"(L.(L:(LF(LR( ^!ðJ ! !• ¶¹o÷ %1=IUamy…‘©µÁÍÙåñý !-9EQ]iu™¥±½ÉÕáíù)5AMYeq}‰•¡­¹ÅÑÝéõ %1=IUaINTERFACES/FSDB/FSDBVERILOG/exp1.vcd.fsdb000064400001440000012000000143571103104161000201020ustar00jcosleystaff00000400000023HÙ>EmͲ/10psSep 20, 2000 16:57:02Leapfrog,U„@¨8ÿÿÿÿÿÿÿÿ/ü®ÿ°Wed Nov 29 10:13:06 2006unknownsun4uSunOS5.7 Generic_106541-02FSDB_ENV_SYNC_CONTROL=NULL, FSDB_ENV_DUMP_SEQ_NUM=NULL, FSDB_ENV_MAX_GLITCH_NUM=NULL, FSDB_ENV_WRITER_MEM_LIMIT=NULL, FSDB_ENV_NOVAS_LOCK=NULL, FSDB_ENV_LOCK_FILE_LOC=NULLident_ffw_SOL2_DEB_6.1_4.1_SUNOS5.8_/opt/SUNWspro42/SC4.2/bin/cc_10172006þmembistv_chip`ȃpad_toÏ Xý‘rightÓiýýýÿ!¿hclkinharbQs_P hhold¨ahblastM…hwrY e_n[3] Í2M Í1M Í0] \aitg D offhrdyrhd[3u‹Sw29K‹8W‹7K‹6W—5K‹4W—q‹o—mƒwo1w‹w—wƒw‹w —w!ƒi  "g  #‹e  $—w %cn &nm'jt(uk)`j*kq+jº ,u· -j´ .uq /srck00d1PfsH2st™3Hy4G™5“16d7Dfs8J™9Hy:P™;‡2<d=“H>“Q?sY@“BA›3BdCLfsD“YEHyF‡HGgpioå Hͧ IÍa JÛs KÍ­ LÛg M­± Nº³ O¬jP¹· Q¬fR¹eS¬½ T¹·U¬¡ V¹c WpjTXHdoYGrstZQms[Gdi\lª]Hj^Gª_Qj`yJaej_Zlbkd˜cVtagÒdͳeÍt fscan_enlgteI¬hjtselilx_bisteU jtm_dspkih lrsZmGYndPelÖ oî¸ pîº qý©rì¾ sûktpllk]u‹oev•bw‰p'x‰A ouT'yË)z–n¶{&¬ |&n}v_rati@ gpad_*_Tj~'Saó¦+瀺w+ú­wr낾a+òƒÃˆ+ô„¦‰+ó…º×_/†+z‡žsck²Ÿˆ³fs(T‰,(² еxЉ‹©&>©Œµ&¤µ&*º޵&,­,,¦µ&,¹‘«&.¬’¡&,¢“·&,¿”,.®•£&«–¹&¿—¯&.µ˜¥&.º"™,.«š±&0«›‡|!ÖË(œ.½4.i ž.c Ÿ.p%  .}= ¡-¹6¢-±*£- ¤-¹ ¥-¾¦-­§-¦ ¨-«©-°ª-a-«ÿ•D*¬°T,Æ­‘[+&R®£Y!°#&ÿ!Á(E&, ¡VÜ, = a­„ Xï°°e `' 7" >…¨8ÃÿÂj "-8CNYdoz…›¦±¼ÇÒÝèóþ *5@KValw‚˜£®¹ÄÏÚåðû'3?KWco{‡“Ÿ«·ÃÏÛçóÿ #/;GS_kwƒ›§³¿Ë×ãñ!1=IUamy…‘©µÁÍÙåñý !-9EQ]iuŸ«·ÃÏÛçóÿ #/;GS_kwƒ›§³¿Ë×ãïû+7CO[gs‹—£¯»ÇÓßë÷INTERFACES/FSDB/FSDBSTIL/000075500001440000012000000000001103104161000152445ustar00jcosleystaff00000400000023INTERFACES/FSDB/FSDBSTIL/exp1.vcd000064400001440000012000004261431103104161000166310ustar00jcosleystaff00000400000023$date Dec 3, 2001 16:19:45 $end $version VERILOG-XL 2.7.s032 $end $timescale 10ps $end $scope module pcibridge_tb $end $var wire 1 ! TCK $end $var wire 1 " TMS $end $var wire 1 # TDI $end $var wire 1 $ TDO $end $var wire 1 % TRST_L $end $var wire 1 & BPCCE $end $var wire 1 ' CFG66 $end $var wire 1 ( S_CFN_L $end $var wire 1 ) P_SERR_L $end $var wire 1 * S_M66EN $end $var wire 1 + GPIO [3] $end $var wire 1 , GPIO [2] $end $var wire 1 - GPIO [1] $end $var wire 1 . GPIO [0] $end $var wire 1 / MSK_IN $end $var wire 1 0 P_AD [31] $end $var wire 1 1 P_AD [30] $end $var wire 1 2 P_AD [29] $end $var wire 1 3 P_AD [28] $end $var wire 1 4 P_AD [27] $end $var wire 1 5 P_AD [26] $end $var wire 1 6 P_AD [25] $end $var wire 1 7 P_AD [24] $end $var wire 1 8 P_AD [23] $end $var wire 1 9 P_AD [22] $end $var wire 1 : P_AD [21] $end $var wire 1 ; P_AD [20] $end $var wire 1 < P_AD [19] $end $var wire 1 = P_AD [18] $end $var wire 1 > P_AD [17] $end $var wire 1 ? P_AD [16] $end $var wire 1 @ P_AD [15] $end $var wire 1 A P_AD [14] $end $var wire 1 B P_AD [13] $end $var wire 1 C P_AD [12] $end $var wire 1 D P_AD [11] $end $var wire 1 E P_AD [10] $end $var wire 1 F P_AD [9] $end $var wire 1 G P_AD [8] $end $var wire 1 H P_AD [7] $end $var wire 1 I P_AD [6] $end $var wire 1 J P_AD [5] $end $var wire 1 K P_AD [4] $end $var wire 1 L P_AD [3] $end $var wire 1 M P_AD [2] $end $var wire 1 N P_AD [1] $end $var wire 1 O P_AD [0] $end $var wire 1 P P_CBE [3] $end $var wire 1 Q P_CBE [2] $end $var wire 1 R P_CBE [1] $end $var wire 1 S P_CBE [0] $end $var wire 1 T P_DEVSEL_L $end $var wire 1 U P_FRAME_L $end $var wire 1 V P_GNT_L $end $var wire 1 W P_IDSEL $end $var wire 1 X P_IRDY_L $end $var wire 1 Y P_LOCK_L $end $var wire 1 Z P_M66EN $end $var wire 1 [ P_PAR $end $var wire 1 \ P_PERR_L $end $var wire 1 ] P_REQ_L $end $var wire 1 ^ P_STOP_L $end $var wire 1 _ P_TRDY_L $end $var wire 1 ` S_AD [31] $end $var wire 1 a S_AD [30] $end $var wire 1 b S_AD [29] $end $var wire 1 c S_AD [28] $end $var wire 1 d S_AD [27] $end $var wire 1 e S_AD [26] $end $var wire 1 f S_AD [25] $end $var wire 1 g S_AD [24] $end $var wire 1 h S_AD [23] $end $var wire 1 i S_AD [22] $end $var wire 1 j S_AD [21] $end $var wire 1 k S_AD [20] $end $var wire 1 l S_AD [19] $end $var wire 1 m S_AD [18] $end $var wire 1 n S_AD [17] $end $var wire 1 o S_AD [16] $end $var wire 1 p S_AD [15] $end $var wire 1 q S_AD [14] $end $var wire 1 r S_AD [13] $end $var wire 1 s S_AD [12] $end $var wire 1 t S_AD [11] $end $var wire 1 u S_AD [10] $end $var wire 1 v S_AD [9] $end $var wire 1 w S_AD [8] $end $var wire 1 x S_AD [7] $end $var wire 1 y S_AD [6] $end $var wire 1 z S_AD [5] $end $var wire 1 { S_AD [4] $end $var wire 1 | S_AD [3] $end $var wire 1 } S_AD [2] $end $var wire 1 ~ S_AD [1] $end $var wire 1 !! S_AD [0] $end $var wire 1 "! S_CLKOUT [9] $end $var wire 1 #! S_CLKOUT [8] $end $var wire 1 $! S_CLKOUT [7] $end $var wire 1 %! S_CLKOUT [6] $end $var wire 1 &! S_CLKOUT [5] $end $var wire 1 '! S_CLKOUT [4] $end $var wire 1 (! S_CLKOUT [3] $end $var wire 1 )! S_CLKOUT [2] $end $var wire 1 *! S_CLKOUT [1] $end $var wire 1 +! S_CLKOUT [0] $end $var wire 1 ,! S_CBE [3] $end $var wire 1 -! S_CBE [2] $end $var wire 1 .! S_CBE [1] $end $var wire 1 /! S_CBE [0] $end $var wire 1 0! S_DEVSEL_L $end $var wire 1 1! S_FRAME_L $end $var wire 1 2! S_GNT_L [8] $end $var wire 1 3! S_GNT_L [7] $end $var wire 1 4! S_GNT_L [6] $end $var wire 1 5! S_GNT_L [5] $end $var wire 1 6! S_GNT_L [4] $end $var wire 1 7! S_GNT_L [3] $end $var wire 1 8! S_GNT_L [2] $end $var wire 1 9! S_GNT_L [1] $end $var wire 1 :! S_GNT_L [0] $end $var wire 1 ;! S_IRDY_L $end $var wire 1 ! S_RESET_L $end $var wire 1 ?! S_PERR_L $end $var wire 1 @! S_REQ_L [8] $end $var wire 1 A! S_REQ_L [7] $end $var wire 1 B! S_REQ_L [6] $end $var wire 1 C! S_REQ_L [5] $end $var wire 1 D! S_REQ_L [4] $end $var wire 1 E! S_REQ_L [3] $end $var wire 1 F! S_REQ_L [2] $end $var wire 1 G! S_REQ_L [1] $end $var wire 1 H! S_REQ_L [0] $end $var wire 1 I! S_SERR_L $end $var wire 1 J! S_STOP_L $end $var wire 1 K! S_TRDY_L $end $var wire 1 L! P_CLK $end $var wire 1 M! P_RESET_L $end $var wire 1 N! S_CLKIN $end $var wire 1 O! LOO $end $var wire 1 P! P_VIO $end $var wire 1 Q! S_VIO $end $var wire 1 R! ENUM_L $end $var wire 1 S! MS0 $end $var wire 1 T! MS1 $end $scope task print_bit_string $end $upscope $end $scope task async_tap_reset $end $upscope $end $scope task sync_tap_reset $end $upscope $end $scope task shift_instr_register_with_pause $end $scope begin insert_overshifted_pattern $end $upscope $end $scope begin check_TDO_for_shifted_pattern $end $upscope $end $upscope $end $scope task shift_boundary_register_with_pause $end $scope begin insert_overshifted_pattern $end $upscope $end $scope begin check_TDO_for_shifted_pattern $end $upscope $end $upscope $end $scope task run_all_tap_states $end $upscope $end $scope task set_instruction $end $upscope $end $scope task insert_serial_data_TDI $end $upscope $end $scope task create_out_bscells_pattern_1 $end $upscope $end $scope task create_out_bscells_pattern_0 $end $upscope $end $scope task create_out_bscells_pattern_01 $end $upscope $end $scope task create_out_bscells_pattern_10 $end $upscope $end $scope task create_out_bscells_pattern_z $end $upscope $end $scope task create_out_bscells_pattern_inverted $end $upscope $end $scope task initialize_input_bscells $end $upscope $end $scope task set_input_bscells_0 $end $upscope $end $scope task set_input_bscells_1 $end $upscope $end $scope task set_input_bscells_01 $end $upscope $end $scope task set_input_bscells_10 $end $upscope $end $scope task set_input_bscells_01_sample $end $upscope $end $scope task set_input_bscells_10_sample $end $upscope $end $scope task set_bidi_pads_Z $end $upscope $end $scope task check_output_bscells_0 $end $upscope $end $scope task check_output_bscells_1 $end $upscope $end $scope task check_output_bscells_01 $end $upscope $end $scope task check_output_bscells_10 $end $upscope $end $scope task check_output_bscells_Z $end $upscope $end $scope task check_output_bscells_highz_Z $end $upscope $end $scope task check_output_bscells_extest $end $upscope $end $scope task check_output_bscells_sample $end $upscope $end $scope task check_default_instruction $end $upscope $end $scope task check_TDO_for_capture_pattern $end $upscope $end $scope task check_bypass_reg $end $upscope $end $scope task check_boundary_reg_with_patterns_01 $end $upscope $end $scope task check_boundary_reg_with_patterns_10 $end $upscope $end $scope task check_boundary_reg_with_patterns_01_sample $end $upscope $end $scope task check_boundary_reg_with_patterns_10_sample $end $upscope $end $scope task check_boundary_reg_with_patterns_0 $end $upscope $end $scope task check_boundary_reg_with_patterns_1 $end $upscope $end $scope task check_TDO_Z $end $upscope $end $scope task sample_TDO $end $upscope $end $scope module chip $end $scope module pad_i1 $end $scope module xp_serr $end $var wire 1 U! gmux_out $end $upscope $end $scope module xs_m66en $end $var wire 1 V! xs_m66en_gmux_out $end $upscope $end $scope module x_gpio_0 $end $var wire 1 W! x_gpio_0_gmux_out $end $upscope $end $scope module x_gpio_1 $end $var wire 1 X! x_gpio_1_gmux_out $end $upscope $end $scope module x_gpio_2 $end $var wire 1 Y! x_gpio_2_gmux_out $end $upscope $end $scope module x_gpio_3 $end $var wire 1 Z! x_gpio_3_gmux_out $end $upscope $end $scope module xp_ad0 $end $var wire 1 [! xp_ad0_gmux_out $end $upscope $end $scope module xp_ad1 $end $var wire 1 \! xp_ad1_gmux_out $end $upscope $end $scope module xp_ad2 $end $var wire 1 ]! xp_ad2_gmux_out $end $upscope $end $scope module xp_ad3 $end $var wire 1 ^! xp_ad3_gmux_out $end $upscope $end $scope module xp_ad4 $end $var wire 1 _! xp_ad4_gmux_out $end $upscope $end $scope module xp_ad5 $end $var wire 1 `! xp_ad5_gmux_out $end $upscope $end $scope module xp_ad6 $end $var wire 1 a! xp_ad6_gmux_out $end $upscope $end $scope module xp_ad7 $end $var wire 1 b! xp_ad7_gmux_out $end $upscope $end $scope module xp_ad8 $end $var wire 1 c! xp_ad8_gmux_out $end $upscope $end $scope module xp_ad9 $end $var wire 1 d! xp_ad9_gmux_out $end $upscope $end $scope module xp_ad10 $end $var wire 1 e! xp_ad10_gmux_out $end $upscope $end $scope module xp_ad11 $end $var wire 1 f! xp_ad11_gmux_out $end $upscope $end $scope module xp_ad12 $end $var wire 1 g! xp_ad12_gmux_out $end $upscope $end $scope module xp_ad13 $end $var wire 1 h! xp_ad13_gmux_out $end $upscope $end $scope module xp_ad14 $end $var wire 1 i! xp_ad14_gmux_out $end $upscope $end $scope module xp_ad15 $end $var wire 1 j! xp_ad15_gmux_out $end $upscope $end $scope module xp_ad16 $end $var wire 1 k! xp_ad16_gmux_out $end $upscope $end $scope module xp_ad17 $end $var wire 1 l! xp_ad17_gmux_out $end $upscope $end $scope module xp_ad18 $end $var wire 1 m! xp_ad18_gmux_out $end $upscope $end $scope module xp_ad19 $end $var wire 1 n! xp_ad19_gmux_out $end $upscope $end $scope module xp_ad20 $end $var wire 1 o! xp_ad20_gmux_out $end $upscope $end $scope module xp_ad21 $end $var wire 1 p! xp_ad21_gmux_out $end $upscope $end $scope module xp_ad22 $end $var wire 1 q! xp_ad22_gmux_out $end $upscope $end $scope module xp_ad23 $end $var wire 1 r! xp_ad23_gmux_out $end $upscope $end $scope module xp_ad24 $end $var wire 1 s! xp_ad24_gmux_out $end $upscope $end $scope module xp_ad25 $end $var wire 1 t! xp_ad25_gmux_out $end $upscope $end $scope module xp_ad26 $end $var wire 1 u! xp_ad26_gmux_out $end $upscope $end $scope module xp_ad27 $end $var wire 1 v! xp_ad27_gmux_out $end $upscope $end $scope module xp_ad28 $end $var wire 1 w! xp_ad28_gmux_out $end $upscope $end $scope module xp_ad29 $end $var wire 1 x! xp_ad29_gmux_out $end $upscope $end $scope module xp_ad30 $end $var wire 1 y! xp_ad30_gmux_out $end $upscope $end $scope module xp_ad31 $end $var wire 1 z! xp_ad31_gmux_out $end $upscope $end $scope module xp_cbe0 $end $var wire 1 {! xp_cbe0_gmux_out $end $upscope $end $scope module xp_cbe1 $end $var wire 1 |! xp_cbe1_gmux_out $end $upscope $end $scope module xp_cbe2 $end $var wire 1 }! xp_cbe2_gmux_out $end $upscope $end $scope module xp_cbe3 $end $var wire 1 ~! xp_cbe3_gmux_out $end $upscope $end $scope module xp_devsel $end $var wire 1 !" xp_devsel_gmux_out $end $upscope $end $scope module xp_frame $end $var wire 1 "" xp_frame_gmux_out $end $upscope $end $scope module xp_irdy $end $var wire 1 #" xp_irdy_gmux_out $end $upscope $end $scope module xp_par $end $var wire 1 $" xp_par_gmux_out $end $upscope $end $scope module xp_perr $end $var wire 1 %" xp_perr_gmux_out $end $upscope $end $scope module xp_req $end $var wire 1 &" gmux_out $end $upscope $end $scope module xp_stop $end $var wire 1 '" xp_stop_gmux_out $end $upscope $end $scope module xp_trdy $end $var wire 1 (" xp_trdy_gmux_out $end $upscope $end $scope module xs_ad0 $end $var wire 1 )" xs_ad0_gmux_out $end $upscope $end $scope module xs_ad1 $end $var wire 1 *" xs_ad1_gmux_out $end $upscope $end $scope module xs_ad2 $end $var wire 1 +" xs_ad2_gmux_out $end $upscope $end $scope module xs_ad3 $end $var wire 1 ," xs_ad3_gmux_out $end $upscope $end $scope module xs_ad4 $end $var wire 1 -" xs_ad4_gmux_out $end $upscope $end $scope module xs_ad5 $end $var wire 1 ." xs_ad5_gmux_out $end $upscope $end $scope module xs_ad6 $end $var wire 1 /" xs_ad6_gmux_out $end $upscope $end $scope module xs_ad7 $end $var wire 1 0" xs_ad7_gmux_out $end $upscope $end $scope module xs_ad8 $end $var wire 1 1" xs_ad8_gmux_out $end $upscope $end $scope module xs_ad9 $end $var wire 1 2" xs_ad9_gmux_out $end $upscope $end $scope module xs_ad10 $end $var wire 1 3" xs_ad10_gmux_out $end $upscope $end $scope module xs_ad11 $end $var wire 1 4" xs_ad11_gmux_out $end $upscope $end $scope module xs_ad12 $end $var wire 1 5" xs_ad12_gmux_out $end $upscope $end $scope module xs_ad13 $end $var wire 1 6" xs_ad13_gmux_out $end $upscope $end $scope module xs_ad14 $end $var wire 1 7" xs_ad14_gmux_out $end $upscope $end $scope module xs_ad15 $end $var wire 1 8" xs_ad15_gmux_out $end $upscope $end $scope module xs_ad16 $end $var wire 1 9" xs_ad16_gmux_out $end $upscope $end $scope module xs_ad17 $end $var wire 1 :" xs_ad17_gmux_out $end $upscope $end $scope module xs_ad18 $end $var wire 1 ;" xs_ad18_gmux_out $end $upscope $end $scope module xs_ad19 $end $var wire 1 <" xs_ad19_gmux_out $end $upscope $end $scope module xs_ad20 $end $var wire 1 =" xs_ad20_gmux_out $end $upscope $end $scope module xs_ad21 $end $var wire 1 >" xs_ad21_gmux_out $end $upscope $end $scope module xs_ad22 $end $var wire 1 ?" xs_ad22_gmux_out $end $upscope $end $scope module xs_ad23 $end $var wire 1 @" xs_ad23_gmux_out $end $upscope $end $scope module xs_ad24 $end $var wire 1 A" xs_ad24_gmux_out $end $upscope $end $scope module xs_ad25 $end $var wire 1 B" xs_ad25_gmux_out $end $upscope $end $scope module xs_ad26 $end $var wire 1 C" xs_ad26_gmux_out $end $upscope $end $scope module xs_ad27 $end $var wire 1 D" xs_ad27_gmux_out $end $upscope $end $scope module xs_ad28 $end $var wire 1 E" xs_ad28_gmux_out $end $upscope $end $scope module xs_ad29 $end $var wire 1 F" xs_ad29_gmux_out $end $upscope $end $scope module xs_ad30 $end $var wire 1 G" xs_ad30_gmux_out $end $upscope $end $scope module xs_ad31 $end $var wire 1 H" xs_ad31_gmux_out $end $upscope $end $scope module xs_cbe0 $end $var wire 1 I" xs_cbe0_gmux_out $end $upscope $end $scope module xs_cbe1 $end $var wire 1 J" xs_cbe1_gmux_out $end $upscope $end $scope module xs_cbe2 $end $var wire 1 K" xs_cbe2_gmux_out $end $upscope $end $scope module xs_cbe3 $end $var wire 1 L" xs_cbe3_gmux_out $end $upscope $end $scope module xs_devsel $end $var wire 1 M" xs_devsel_gmux_out $end $upscope $end $scope module xs_frame $end $var wire 1 N" xs_frame_gmux_out $end $upscope $end $scope module xs_gnt1 $end $var wire 1 O" gmux_out $end $upscope $end $scope module xs_gnt2 $end $var wire 1 P" gmux_out $end $upscope $end $scope module xs_gnt3 $end $var wire 1 Q" gmux_out $end $upscope $end $scope module xs_gnt4 $end $var wire 1 R" gmux_out $end $upscope $end $scope module xs_gnt5 $end $var wire 1 S" gmux_out $end $upscope $end $scope module xs_gnt6 $end $var wire 1 T" gmux_out $end $upscope $end $scope module xs_gnt7 $end $var wire 1 U" gmux_out $end $upscope $end $scope module xs_gnt8 $end $var wire 1 V" gmux_out $end $upscope $end $scope module xs_irdy $end $var wire 1 W" xs_irdy_gmux_out $end $upscope $end $scope module xs_lock $end $var wire 1 X" xs_lock_gmux_out $end $upscope $end $scope module xs_par $end $var wire 1 Y" xs_par_gmux_out $end $upscope $end $scope module xs_perr $end $var wire 1 Z" xs_perr_gmux_out $end $upscope $end $scope module xs_stop $end $var wire 1 [" xs_stop_gmux_out $end $upscope $end $scope module xs_trdy $end $var wire 1 \" xs_trdy_gmux_out $end $upscope $end $scope module xs_gnt0 $end $var wire 1 ]" gmux_out $end $upscope $end $upscope $end $upscope $end $scope begin TDO_check $end $upscope $end $scope begin bsda_tb $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 1! x" x# x$ x% x& x' x( x) x* x+ x, x- x. x/ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x: x; x< x= x> x? x@ xA xB xC xD xE xF xG xH xI xJ xK xL xM xN xO xP xQ xR xS xT xU xV xW xX xY xZ x[ x\ x] x^ x_ x` xa xb xc xd xe xf xg xh xi xj xk xl xm xn xo xp xq xr xs xt xu xv xw xx xy xz x{ x| x} x~ x!! x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x,! x-! x.! x/! x0! x1! x2! x3! x4! x5! x6! x7! x8! x9! x:! x;! x! x?! x@! xA! xB! xC! xD! xE! xF! xG! xH! xI! xJ! xK! xL! xM! xN! xO! zP! zQ! xR! zS! zT! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" $end #10000 0! #15000 0% 0" x) x* z$ #20000 1! #30000 0! #35000 1% #40000 1! #50000 0! #60000 1! #70000 0! #80000 1! #90000 0! #95000 1I! 1H! 1G! 1F! 1E! 1D! 1C! 1B! 1A! 1@! 1N! 1( 1M! 1& 1L! 1V 1W 1Y 1Z 1' 1/ #100000 1! #110000 0! #115000 1" #120000 1! #130000 0! #135000 0" #140000 1! #150000 0! #160000 1! #170000 0! 0$ #175000 1" #180000 1! #190000 0! x$ z$ #200000 1! #210000 0! #215000 0" #220000 1! #230000 0! #235000 1" #240000 1! #250000 0! #260000 1! #270000 0! #275000 0" #280000 1! #290000 0! #300000 1! #310000 0! 1$ #315000 1# #320000 1! #330000 0! 0$ #340000 1! #350000 0! #360000 1! #370000 0! #380000 1! #390000 0! #395000 1" #400000 1! #410000 0! 1$ z$ #415000 0# #420000 1! #430000 0! #435000 0" #440000 1! #450000 0! #455000 1" #460000 1! #470000 0! #480000 1! #490000 0! #500000 1! #510000 0! #520000 1! #530000 0! #540000 1! #550000 0! #560000 1! #570000 0! #575000 0" #580000 1! #590000 0! #600000 1! #610000 0! #615000 1" #620000 1! #630000 0! #640000 1! #650000 0! #655000 0" #660000 1! #670000 0! #680000 1! #690000 0! 1$ #695000 1# #700000 1! #710000 0! 0$ #720000 1! #730000 0! #740000 1! #750000 0! #755000 0# #760000 1! #770000 0! #780000 1! #790000 0! 1$ #795000 1# #800000 1! #810000 0! #815000 0# 1" #820000 1! #830000 0! z$ #835000 0" #840000 1! #850000 0! #860000 1! #870000 0! #880000 1! #890000 0! #900000 1! #910000 0! #920000 1! #930000 0! #940000 1! #950000 0! #955000 1" #960000 1! #970000 0! #975000 0" #980000 1! #990000 0! 1$ #995000 1# #1000000 1! #1010000 0! 0$ #1015000 0# #1020000 1! #1030000 0! #1040000 1! #1050000 0! 1$ #1060000 1! #1070000 0! 0$ #1080000 1! #1090000 0! 1$ #1100000 1! #1110000 0! 0$ #1115000 1" #1120000 1! #1130000 0! z$ #1140000 1! #1150000 0! 0U! 0V! 0W! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0f! 0g! 0h! 0i! 0j! 0k! 0l! 0m! 0n! 0o! 0p! 0q! 0r! 0s! 0t! 0u! 0v! 0w! 0x! 0y! 0z! 0{! 0|! 0}! 0~! 0!" 0"" 0#" 0$" 0%" 0&" 0'" 0(" 0)" 0*" 0+" 0," 0-" 0." 0/" 00" 01" 02" 03" 04" 05" 06" 07" 08" 09" 0:" 0;" 0<" 0=" 0>" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" x]" x\" x[" xZ" xY" xX" xW" xV" xU" xT" xS" xR" xQ" xP" xO" xN" xM" xL" xK" xJ" xI" xH" xG" xF" xE" xD" xC" xB" xA" x@" x?" x>" x=" x<" x;" x:" x9" x8" x7" x6" x5" x4" x3" x2" x1" x0" x/" x." x-" x," x+" x*" x)" x(" x'" x&" x%" x$" x#" x"" x!" x~! x}! x|! x{! xz! xy! xx! xw! xv! xu! xt! xs! xr! xq! xp! xo! xn! xm! xl! xk! xj! xi! xh! xg! xf! xe! xd! xc! xb! xa! x`! x_! x^! x]! x\! x[! xZ! xY! xX! xW! xV! xU! x) x* #1160000 1! #1170000 0! #1180000 1! #1190000 0! #1195000 0" #1200000 1! #1210000 0! #1215000 1" #1220000 1! #1230000 0! #1235000 0" #1240000 1! #1250000 0! #1260000 1! #1270000 0! #1275000 1" #1280000 1! #1290000 0! #1295000 0" #1300000 1! #1310000 0! 1$ #1320000 1! #1330000 0! 0$ #1340000 1! #1350000 0! #1360000 1! #1370000 0! #1380000 1! #1390000 0! #1395000 1" #1400000 1! #1410000 0! z$ #1415000 0" #1420000 1! #1430000 0! #1435000 1" #1440000 1! #1450000 0! #1460000 1! #1470000 0! #1475000 0" #1480000 1! #1490000 0! #1500000 1! #1510000 0! #1515000 1" #1520000 1! #1530000 0! #1535000 0" #1540000 1! #1550000 0! #1560000 1! #1570000 0! x$ #1575000 1# #1580000 1! #1590000 0! #1600000 1! #1610000 0! #1620000 1! #1630000 0! #1635000 0# #1640000 1! #1650000 0! #1660000 1! #1670000 0! #1675000 1# #1680000 1! #1690000 0! #1695000 0# #1700000 1! #1710000 0! #1715000 1# #1720000 1! #1730000 0! #1735000 0# #1740000 1! #1750000 0! #1760000 1! #1770000 0! #1780000 1! #1790000 0! 0$ #1800000 1! #1810000 0! x$ #1820000 1! #1830000 0! #1840000 1! #1850000 0! #1860000 1! #1870000 0! #1880000 1! #1890000 0! #1900000 1! #1910000 0! #1920000 1! #1930000 0! #1940000 1! #1950000 0! #1960000 1! #1970000 0! #1980000 1! #1990000 0! 1$ #2000000 1! #2010000 0! x$ #2020000 1! #2030000 0! #2040000 1! #2050000 0! #2060000 1! #2070000 0! #2080000 1! #2090000 0! #2100000 1! #2110000 0! #2120000 1! #2130000 0! #2140000 1! #2150000 0! #2160000 1! #2170000 0! #2180000 1! #2190000 0! #2200000 1! #2210000 0! #2220000 1! #2230000 0! #2240000 1! #2250000 0! #2260000 1! #2270000 0! #2280000 1! #2290000 0! #2300000 1! #2310000 0! #2320000 1! #2330000 0! #2340000 1! #2350000 0! #2360000 1! #2370000 0! #2380000 1! #2390000 0! #2400000 1! #2410000 0! #2420000 1! #2430000 0! #2440000 1! #2450000 0! #2460000 1! #2470000 0! #2480000 1! #2490000 0! #2500000 1! #2510000 0! #2520000 1! #2530000 0! #2540000 1! #2550000 0! 1$ #2560000 1! #2570000 0! #2580000 1! #2590000 0! #2600000 1! #2610000 0! #2620000 1! #2630000 0! #2640000 1! #2650000 0! #2660000 1! #2670000 0! #2680000 1! #2690000 0! #2700000 1! #2710000 0! #2720000 1! #2730000 0! x$ #2740000 1! #2750000 0! #2760000 1! #2770000 0! #2780000 1! #2790000 0! #2800000 1! #2810000 0! #2820000 1! #2830000 0! #2840000 1! #2850000 0! #2860000 1! #2870000 0! #2880000 1! #2890000 0! #2900000 1! #2910000 0! #2920000 1! #2930000 0! 1$ #2940000 1! #2950000 0! x$ #2960000 1! #2970000 0! 1$ #2980000 1! #2990000 0! x$ #3000000 1! #3010000 0! #3020000 1! #3030000 0! #3040000 1! #3050000 0! #3060000 1! #3070000 0! #3080000 1! #3090000 0! #3100000 1! #3110000 0! #3120000 1! #3130000 0! #3140000 1! #3150000 0! #3160000 1! #3170000 0! #3180000 1! #3190000 0! #3200000 1! #3210000 0! #3220000 1! #3230000 0! #3240000 1! #3250000 0! #3260000 1! #3270000 0! #3280000 1! #3290000 0! 1$ #3300000 1! #3310000 0! #3320000 1! #3330000 0! #3340000 1! #3350000 0! #3360000 1! #3370000 0! x$ #3380000 1! #3390000 0! #3400000 1! #3410000 0! #3420000 1! #3430000 0! #3440000 1! #3450000 0! #3460000 1! #3470000 0! #3480000 1! #3490000 0! #3500000 1! #3510000 0! #3520000 1! #3530000 0! #3540000 1! #3550000 0! #3560000 1! #3570000 0! #3580000 1! #3590000 0! 1$ #3600000 1! #3610000 0! x$ #3620000 1! #3630000 0! #3640000 1! #3650000 0! #3660000 1! #3670000 0! #3680000 1! #3690000 0! #3700000 1! #3710000 0! #3720000 1! #3730000 0! #3740000 1! #3750000 0! #3760000 1! #3770000 0! #3780000 1! #3790000 0! #3800000 1! #3810000 0! #3820000 1! #3830000 0! #3840000 1! #3850000 0! #3860000 1! #3870000 0! #3880000 1! #3890000 0! #3900000 1! #3910000 0! #3920000 1! #3930000 0! 1$ #3940000 1! #3950000 0! x$ #3960000 1! #3970000 0! 0$ #3980000 1! #3990000 0! x$ #4000000 1! #4010000 0! #4020000 1! #4030000 0! #4040000 1! #4050000 0! #4060000 1! #4070000 0! #4080000 1! #4090000 0! #4100000 1! #4110000 0! #4120000 1! #4130000 0! #4140000 1! #4150000 0! 1$ #4160000 1! #4170000 0! x$ #4180000 1! #4190000 0! #4200000 1! #4210000 0! #4220000 1! #4230000 0! #4240000 1! #4250000 0! #4260000 1! #4270000 0! #4280000 1! #4290000 0! #4300000 1! #4310000 0! #4320000 1! #4330000 0! #4340000 1! #4350000 0! #4360000 1! #4370000 0! #4380000 1! #4390000 0! #4400000 1! #4410000 0! 1$ #4420000 1! #4430000 0! #4440000 1! #4450000 0! #4460000 1! #4470000 0! #4475000 1" #4480000 1! #4490000 0! z$ #4495000 0" #4500000 1! #4510000 0! #4520000 1! #4530000 0! #4540000 1! #4550000 0! #4560000 1! #4570000 0! #4580000 1! #4590000 0! #4600000 1! #4610000 0! #4615000 1" #4620000 1! #4630000 0! #4635000 0" #4640000 1! #4650000 0! 1$ #4660000 1! #4670000 0! 0$ #4680000 1! #4690000 0! #4700000 1! #4710000 0! 1$ #4720000 1! #4730000 0! 0$ #4740000 1! #4750000 0! 1$ #4760000 1! #4770000 0! 0$ #4775000 1" #4780000 1! #4790000 0! z$ #4800000 1! #4810000 0! 0&" 0(" 0'" 0%" 0#" 0"" 0!" 0U! 0Z! 0Y! 0X! 0W! 0V" 0]" 0U" 0T" 0S" 0R" 0Q" 0P" 0O" 0\" 0[" 0Z" 0X" 0W" 0N" 0M" 0]! 0\! 0[! 0{! 0d! 0c! 0b! 0a! 0`! 0_! 0^! 0$" 0|! 0j! 0i! 0h! 0g! 0f! 0e! 0}! 0k! 0~! 0r! 0q! 0p! 0o! 0n! 0m! 0l! 0z! 0y! 0x! 0w! 0v! 0u! 0t! 0s! 0H" 0G" 0L" 0F" 0E" 0D" 0C" 0B" 0A" 0@" 0K" 0?" 0>" 0=" 0<" 0;" 0:" 09" 0Y" 0J" 08" 07" 0I" 06" 05" 04" 03" 02" 01" 0V! 00" 0/" 0." 0-" 0," 0+" 0*" 0)" 0) 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 0* 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* x) xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" x]" x\" x[" xZ" xY" xX" xW" xV" xU" xT" xS" xR" xQ" xP" xO" xN" xM" xL" xK" xJ" xI" xH" xG" xF" xE" xD" xC" xB" xA" x@" x?" x>" x=" x<" x;" x:" x9" x8" x7" x6" x5" x4" x3" x2" x1" x0" x/" x." x-" x," x+" x*" x)" x(" x'" x&" x%" x$" x#" x"" x!" x~! x}! x|! x{! xz! xy! xx! xw! xv! xu! xt! xs! xr! xq! xp! xo! xn! xm! xl! xk! xj! xi! xh! xg! xf! xe! xd! xc! xb! xa! x`! x_! x^! x]! x\! x[! xZ! xY! xX! xW! xV! xU! x) x* #18375000 0" #18380000 1! #18390000 0! #18395000 1" #18400000 1! #18410000 0! #18415000 0" #18420000 1! #18430000 0! #18440000 1! #18450000 0! x$ #18460000 1! #18470000 0! #18480000 1! #18490000 0! #18500000 1! #18510000 0! #18520000 1! #18530000 0! #18540000 1! #18550000 0! #18560000 1! #18570000 0! #18580000 1! #18590000 0! #18600000 1! #18610000 0! #18620000 1! #18630000 0! #18640000 1! #18650000 0! #18660000 1! #18670000 0! 0$ #18680000 1! #18690000 0! x$ #18700000 1! #18710000 0! #18720000 1! #18730000 0! #18740000 1! #18750000 0! #18760000 1! #18770000 0! #18780000 1! #18790000 0! #18800000 1! #18810000 0! #18815000 1# #18820000 1! #18830000 0! #18835000 0# #18840000 1! #18850000 0! #18860000 1! #18870000 0! 1$ #18880000 1! #18890000 0! x$ #18900000 1! #18910000 0! #18920000 1! #18930000 0! #18940000 1! #18950000 0! #18955000 1# #18960000 1! #18970000 0! #18975000 0# #18980000 1! #18990000 0! #19000000 1! #19010000 0! #19020000 1! #19030000 0! #19040000 1! #19050000 0! #19060000 1! #19070000 0! #19080000 1! #19090000 0! #19100000 1! #19110000 0! #19120000 1! #19130000 0! #19140000 1! #19150000 0! #19160000 1! #19170000 0! #19180000 1! #19190000 0! #19200000 1! #19210000 0! #19220000 1! #19230000 0! #19240000 1! #19250000 0! #19260000 1! #19270000 0! #19280000 1! #19290000 0! #19300000 1! #19310000 0! #19320000 1! #19330000 0! #19340000 1! #19350000 0! #19360000 1! #19370000 0! #19380000 1! #19390000 0! #19395000 1# #19400000 1! #19410000 0! #19415000 0# #19420000 1! #19430000 0! 0$ #19440000 1! #19450000 0! 1$ #19460000 1! #19470000 0! 0$ #19480000 1! #19490000 0! 1$ #19500000 1! #19510000 0! 0$ #19520000 1! #19530000 0! 1$ #19540000 1! #19550000 0! 0$ #19560000 1! #19570000 0! 1$ #19580000 1! #19590000 0! 0$ #19600000 1! #19610000 0! x$ #19620000 1! #19630000 0! #19640000 1! #19650000 0! #19655000 1# #19660000 1! #19670000 0! #19675000 0# #19680000 1! #19690000 0! #19700000 1! #19710000 0! #19720000 1! #19730000 0! #19740000 1! #19750000 0! #19760000 1! #19770000 0! #19780000 1! #19790000 0! #19800000 1! #19810000 0! 1$ #19820000 1! #19830000 0! x$ #19840000 1! #19850000 0! 0$ #19860000 1! #19870000 0! x$ #19880000 1! #19890000 0! #19900000 1! #19910000 0! #19920000 1! #19930000 0! #19940000 1! #19950000 0! #19960000 1! #19970000 0! #19980000 1! #19990000 0! #19995000 1# #20000000 1! #20010000 0! #20015000 0# #20020000 1! #20030000 0! #20040000 1! #20050000 0! #20060000 1! #20070000 0! #20080000 1! #20090000 0! #20100000 1! #20110000 0! #20120000 1! #20130000 0! #20140000 1! #20150000 0! #20160000 1! #20170000 0! 1$ #20180000 1! #20190000 0! 0$ #20200000 1! #20210000 0! 1$ #20220000 1! #20230000 0! 0$ #20240000 1! #20250000 0! x$ #20260000 1! #20270000 0! #20275000 1# #20280000 1! #20290000 0! #20295000 0# #20300000 1! #20310000 0! #20320000 1! #20330000 0! #20340000 1! #20350000 0! #20360000 1! #20370000 0! #20380000 1! #20390000 0! #20400000 1! #20410000 0! #20420000 1! #20430000 0! #20440000 1! #20450000 0! #20460000 1! #20470000 0! 1$ #20480000 1! #20490000 0! x$ #20500000 1! #20510000 0! #20520000 1! #20530000 0! #20540000 1! #20550000 0! #20560000 1! #20570000 0! #20580000 1! #20590000 0! #20600000 1! #20610000 0! #20620000 1! #20630000 0! #20640000 1! #20650000 0! #20655000 1# #20660000 1! #20670000 0! #20675000 0# #20680000 1! #20690000 0! #20700000 1! #20710000 0! #20720000 1! #20730000 0! #20740000 1! #20750000 0! #20760000 1! #20770000 0! #20780000 1! #20790000 0! #20795000 1# #20800000 1! #20810000 0! 0$ #20815000 0# #20820000 1! #20830000 0! x$ #20840000 1! #20850000 0! 0$ #20860000 1! #20870000 0! x$ #20880000 1! #20890000 0! #20900000 1! #20910000 0! #20920000 1! #20930000 0! #20940000 1! #20950000 0! #20960000 1! #20970000 0! #20980000 1! #20990000 0! #21000000 1! #21010000 0! #21020000 1! #21030000 0! 1$ #21040000 1! #21050000 0! x$ #21060000 1! #21070000 0! #21080000 1! #21090000 0! #21100000 1! #21110000 0! #21120000 1! #21130000 0! #21140000 1! #21150000 0! #21160000 1! #21170000 0! #21180000 1! #21190000 0! #21200000 1! #21210000 0! #21220000 1! #21230000 0! #21240000 1! #21250000 0! #21260000 1! #21270000 0! #21275000 1# #21280000 1! #21290000 0! 0$ #21295000 0# #21300000 1! #21310000 0! 1$ #21315000 1" #21320000 1! #21330000 0! 0$ z$ #21340000 1! #21350000 0! 1&" 1\" 1[" 1Z" 1X" 1W" 1N" 1M" 1V" 1]" 1U" 1T" 1S" 1R" 1Q" 1P" 1O" 1Z! 1Y! 1X! 1W! 1(" 1'" 1%" 1#" 1"" 1!" 1U! 1Y" 1J" 18" 17" 1I" 16" 15" 14" 13" 12" 11" 1V! 10" 1/" 1." 1-" 1," 1+" 1*" 1)" 1H" 1G" 1L" 1F" 1E" 1D" 1C" 1B" 1A" 1@" 1K" 1?" 1>" 1=" 1<" 1;" 1:" 19" 1}! 1k! 1~! 1r! 1q! 1p! 1o! 1n! 1m! 1l! 1z! 1y! 1x! 1w! 1v! 1u! 1t! 1s! 1]! 1\! 1[! 1{! 1d! 1c! 1b! 1a! 1`! 1_! 1^! 1$" 1|! 1j! 1i! 1h! 1g! 1f! 1e! z* z:! z9! z8! z7! z6! z5! z4! z3! z2! z>! 0+! 0*! 0)! 0(! 0'! 0&! 0%! 0$! 0#! 0"! z] z) z!! z~ z} z| z{ zz zy zx z/! zw zv zu zt zs zr zq zp z.! z=! z?! z z? zQ zU zX z_ zT z^ z\ z[ zR z@ zA zB zC zD zE zF zG zS zH zI zJ zK zL zM zN zO #21355000 0" #21360000 1! #21370000 0! #21375000 0!! 1~ 0} 1| 0{ 1z 0y 1x 0/! 1w 0v 1u 0t 1s 0r 1q 0p 1.! 0=! 0?! 1 1? 0Q 1U 0X 1_ 0T 1^ 1\ 0[ 1R 0@ 1A 0B 1C 0D 1E 0Z 1F 0G 1S 0H 1I 0J 1K 0L 1M 0N 1O 1" #21380000 1! #21390000 0! #21395000 0" #21400000 1! #21410000 0! #21420000 1! #21430000 0! 0$ #21435000 x# #21440000 1! #21450000 0! 1$ #21460000 1! #21470000 0! 0$ #21480000 1! #21490000 0! 1$ #21500000 1! #21510000 0! 0$ #21520000 1! #21530000 0! 1$ #21540000 1! #21550000 0! 0$ #21560000 1! #21570000 0! 1$ #21580000 1! #21590000 0! 0$ #21600000 1! #21610000 0! 1$ #21620000 1! #21630000 0! 0$ #21640000 1! #21650000 0! #21660000 1! #21670000 0! 1$ #21680000 1! #21690000 0! 0$ #21700000 1! #21710000 0! 1$ #21720000 1! #21730000 0! 0$ #21740000 1! #21750000 0! 1$ #21760000 1! #21770000 0! 0$ #21780000 1! #21790000 0! 1$ #21800000 1! #21810000 0! #21820000 1! #21830000 0! 0$ #21840000 1! #21850000 0! 1$ #21860000 1! #21870000 0! 0$ #21880000 1! #21890000 0! 1$ #21900000 1! #21910000 0! 0$ #21920000 1! #21930000 0! 1$ #21940000 1! #21950000 0! #21960000 1! #21970000 0! 0$ #21980000 1! #21990000 0! 1$ #22000000 1! #22010000 0! 0$ #22020000 1! #22030000 0! 1$ #22040000 1! #22050000 0! 0$ #22060000 1! #22070000 0! 1$ #22080000 1! #22090000 0! 0$ #22100000 1! #22110000 0! 1$ #22120000 1! #22130000 0! 0$ #22140000 1! #22150000 0! 1$ #22160000 1! #22170000 0! 0$ #22180000 1! #22190000 0! 1$ #22200000 1! #22210000 0! 0$ #22220000 1! #22230000 0! 1$ #22240000 1! #22250000 0! 0$ #22260000 1! #22270000 0! 1$ #22280000 1! #22290000 0! 0$ #22300000 1! #22310000 0! 1$ #22320000 1! #22330000 0! 0$ #22340000 1! #22350000 0! 1$ #22360000 1! #22370000 0! #22380000 1! #22390000 0! 0$ #22400000 1! #22410000 0! 1$ #22420000 1! #22430000 0! 0$ #22440000 1! #22450000 0! 1$ #22460000 1! #22470000 0! 0$ #22480000 1! #22490000 0! 1$ #22500000 1! #22510000 0! 0$ #22520000 1! #22530000 0! 1$ #22540000 1! #22550000 0! 0$ #22560000 1! #22570000 0! 1$ #22580000 1! #22590000 0! x$ #22600000 1! #22610000 0! #22620000 1! #22630000 0! #22640000 1! #22650000 0! #22660000 1! #22670000 0! #22680000 1! #22690000 0! #22700000 1! #22710000 0! #22720000 1! #22730000 0! #22740000 1! #22750000 0! #22760000 1! #22770000 0! #22780000 1! #22790000 0! 0$ #22800000 1! #22810000 0! x$ #22820000 1! #22830000 0! 1$ #22840000 1! #22850000 0! 0$ #22860000 1! #22870000 0! 1$ #22880000 1! #22890000 0! 0$ #22900000 1! #22910000 0! 1$ #22920000 1! #22930000 0! x$ #22940000 1! #22950000 0! #22960000 1! #22970000 0! 1$ #22980000 1! #22990000 0! x$ #23000000 1! #23010000 0! #23020000 1! #23030000 0! #23040000 1! #23050000 0! #23060000 1! #23070000 0! #23080000 1! #23090000 0! #23100000 1! #23110000 0! #23120000 1! #23130000 0! #23140000 1! #23150000 0! 0$ #23160000 1! #23170000 0! 1$ #23180000 1! #23190000 0! 0$ #23200000 1! #23210000 0! 1$ #23220000 1! #23230000 0! x$ #23240000 1! #23250000 0! #23260000 1! #23270000 0! 0$ #23280000 1! #23290000 0! 1$ #23300000 1! #23310000 0! 0$ #23320000 1! #23330000 0! 1$ #23340000 1! #23350000 0! 0$ #23360000 1! #23370000 0! 1$ #23380000 1! #23390000 0! 0$ #23400000 1! #23410000 0! 1$ #23420000 1! #23430000 0! 0$ #23440000 1! #23450000 0! 1$ #23460000 1! #23470000 0! 0$ #23480000 1! #23490000 0! 1$ #23500000 1! #23510000 0! 0$ #23520000 1! #23530000 0! 1$ #23540000 1! #23550000 0! 0$ #23560000 1! #23570000 0! 1$ #23580000 1! #23590000 0! 0$ #23600000 1! #23610000 0! 1$ #23620000 1! #23630000 0! #23640000 1! #23650000 0! 0$ #23660000 1! #23670000 0! 1$ #23680000 1! #23690000 0! 0$ #23700000 1! #23710000 0! 1$ #23720000 1! #23730000 0! 0$ #23740000 1! #23750000 0! 1$ #23760000 1! #23770000 0! #23780000 1! #23790000 0! 0$ #23800000 1! #23810000 0! 1$ #23820000 1! #23830000 0! 0$ #23840000 1! #23850000 0! #23860000 1! #23870000 0! 1$ #23880000 1! #23890000 0! 0$ #23900000 1! #23910000 0! 1$ #23920000 1! #23930000 0! 0$ #23940000 1! #23950000 0! 1$ #23960000 1! #23970000 0! 0$ #23980000 1! #23990000 0! 1$ #24000000 1! #24010000 0! 0$ #24020000 1! #24030000 0! 1$ #24040000 1! #24050000 0! 0$ #24060000 1! #24070000 0! 1$ #24080000 1! #24090000 0! 0$ #24100000 1! #24110000 0! 1$ #24120000 1! #24130000 0! 0$ #24140000 1! #24150000 0! 1$ #24160000 1! #24170000 0! 0$ #24180000 1! #24190000 0! 1$ #24200000 1! #24210000 0! 0$ #24220000 1! #24230000 0! 1$ #24240000 1! #24250000 0! #24260000 1! #24270000 0! 0$ #24280000 1! #24290000 0! 1$ #24295000 1" #24300000 1! #24310000 0! x$ z$ #24320000 1! #24330000 0! x&" x(" x'" x%" x#" x"" x!" xU! xZ! xY! xX! xW! xV" x]" xU" xT" xS" xR" xQ" xP" xO" x\" x[" xZ" xX" xW" xN" xM" x]! x\! x[! x{! xd! xc! xb! xa! x`! x_! x^! x$" x|! xj! xi! xh! xg! xf! xe! x}! xk! x~! xr! xq! xp! xo! xn! xm! xl! xz! xy! xx! xw! xv! xu! xt! xs! xH" xG" xL" xF" xE" xD" xC" xB" xA" x@" xK" x?" x>" x=" x<" x;" x:" x9" xY" xJ" x8" x7" xI" x6" x5" x4" x3" x2" x1" xV! x0" x/" x." x-" x," x+" x*" x)" x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x* x9! x8! x7! x6! x5! x4! x3! x:! x2! x>! x) x] x!! x~ x} x| x{ xz xy xx xw xv xu xt xs xr x/! xq xp x.! x=! xo xn xm xl xk xj xi x-! xh xg xf xe xd xc xb x,! xa x` x7 x6 x5 x4 x3 x2 x1 x0 x> x= x< x; x: x9 x8 xP x? xQ xE xD xC xB xA x@ xR x[ xL xK xJ xI xH xG xF xS xO xN xM x0! x1! x;! x" 1=" 1<" 1;" 1:" 19" 1}! 1k! 1~! 1r! 1q! 1p! 1o! 1n! 1m! 1l! 1z! 1y! 1x! 1w! 1v! 1u! 1t! 1s! 1]! 1\! 1[! 1{! 1d! 1c! 1b! 1a! 1`! 1_! 1^! 1$" 1|! 1j! 1i! 1h! 1g! 1f! 1e! z* z:! z9! z8! z7! z6! z5! z4! z3! z2! z>! 0+! 0*! 0)! 0(! 0'! 0&! 0%! 0$! 0#! 0"! z] z) z!! z~ z} z| z{ zz zy zx z/! zw zv zu zt zs zr zq zp z.! z=! z?! z z? zQ zU zX z_ zT z^ z\ z[ zR z@ zA zB zC zD zE zF zG zS zH zI zJ zK zL zM zN zO #27535000 0" #27540000 1! #27550000 0! #27555000 1!! 0~ 1} 0| 1{ 0z 1y 0x 1/! 0w 1v 0u 1t 0s 1r 0q 1p 0.! 1=! 0I! 1?! 0 0? 1Q 0U 1X 0_ 1T 0^ 1Y 0\ 1[ 0R 1@ 0A 1B 0C 1D 0E 1Z 0F 1G 0S 1H 0I 1J 0K 1L 0M 1N 0O 1' 0/ 1" #27560000 1! #27570000 0! #27575000 0" #27580000 1! #27590000 0! #27600000 1! #27610000 0! 1$ #27615000 x# #27620000 1! #27630000 0! 0$ #27640000 1! #27650000 0! 1$ #27660000 1! #27670000 0! 0$ #27680000 1! #27690000 0! 1$ #27700000 1! #27710000 0! 0$ #27720000 1! #27730000 0! 1$ #27740000 1! #27750000 0! 0$ #27760000 1! #27770000 0! 1$ #27780000 1! #27790000 0! 0$ #27800000 1! #27810000 0! 1$ #27820000 1! #27830000 0! 0$ #27840000 1! #27850000 0! #27860000 1! #27870000 0! 1$ #27880000 1! #27890000 0! 0$ #27900000 1! #27910000 0! 1$ #27920000 1! #27930000 0! 0$ #27940000 1! #27950000 0! 1$ #27960000 1! #27970000 0! #27980000 1! #27990000 0! 0$ #28000000 1! #28010000 0! 1$ #28020000 1! #28030000 0! 0$ #28040000 1! #28050000 0! 1$ #28060000 1! #28070000 0! 0$ #28080000 1! #28090000 0! 1$ #28100000 1! #28110000 0! #28120000 1! #28130000 0! 0$ #28140000 1! #28150000 0! 1$ #28160000 1! #28170000 0! 0$ #28180000 1! #28190000 0! 1$ #28200000 1! #28210000 0! 0$ #28220000 1! #28230000 0! 1$ #28240000 1! #28250000 0! 0$ #28260000 1! #28270000 0! 1$ #28280000 1! #28290000 0! 0$ #28300000 1! #28310000 0! 1$ #28320000 1! #28330000 0! 0$ #28340000 1! #28350000 0! 1$ #28360000 1! #28370000 0! 0$ #28380000 1! #28390000 0! 1$ #28400000 1! #28410000 0! 0$ #28420000 1! #28430000 0! 1$ #28440000 1! #28450000 0! 0$ #28460000 1! #28470000 0! 1$ #28480000 1! #28490000 0! 0$ #28500000 1! #28510000 0! 1$ #28520000 1! #28530000 0! 0$ #28540000 1! #28550000 0! 1$ #28560000 1! #28570000 0! #28580000 1! #28590000 0! 0$ #28600000 1! #28610000 0! 1$ #28620000 1! #28630000 0! 0$ #28640000 1! #28650000 0! 1$ #28660000 1! #28670000 0! 0$ #28680000 1! #28690000 0! 1$ #28700000 1! #28710000 0! 0$ #28720000 1! #28730000 0! 1$ #28740000 1! #28750000 0! 0$ #28760000 1! #28770000 0! x$ #28780000 1! #28790000 0! #28800000 1! #28810000 0! #28820000 1! #28830000 0! #28840000 1! #28850000 0! #28860000 1! #28870000 0! #28880000 1! #28890000 0! #28900000 1! #28910000 0! #28920000 1! #28930000 0! #28940000 1! #28950000 0! #28960000 1! #28970000 0! 1$ #28980000 1! #28990000 0! x$ #29000000 1! #29010000 0! 0$ #29020000 1! #29030000 0! 1$ #29040000 1! #29050000 0! 0$ #29060000 1! #29070000 0! 1$ #29080000 1! #29090000 0! 0$ #29100000 1! #29110000 0! x$ #29120000 1! #29130000 0! #29140000 1! #29150000 0! 1$ #29160000 1! #29170000 0! x$ #29180000 1! #29190000 0! #29200000 1! #29210000 0! #29220000 1! #29230000 0! #29240000 1! #29250000 0! #29260000 1! #29270000 0! #29280000 1! #29290000 0! #29300000 1! #29310000 0! #29320000 1! #29330000 0! 1$ #29340000 1! #29350000 0! 0$ #29360000 1! #29370000 0! 1$ #29380000 1! #29390000 0! 0$ #29400000 1! #29410000 0! x$ #29420000 1! #29430000 0! #29440000 1! #29450000 0! 1$ #29460000 1! #29470000 0! 0$ #29480000 1! #29490000 0! 1$ #29500000 1! #29510000 0! 0$ #29520000 1! #29530000 0! 1$ #29540000 1! #29550000 0! 0$ #29560000 1! #29570000 0! 1$ #29580000 1! #29590000 0! 0$ #29600000 1! #29610000 0! 1$ #29620000 1! #29630000 0! 0$ #29640000 1! #29650000 0! 1$ #29660000 1! #29670000 0! 0$ #29680000 1! #29690000 0! 1$ #29700000 1! #29710000 0! 0$ #29720000 1! #29730000 0! 1$ #29740000 1! #29750000 0! 0$ #29760000 1! #29770000 0! 1$ #29780000 1! #29790000 0! 0$ #29800000 1! #29810000 0! 1$ #29820000 1! #29830000 0! #29840000 1! #29850000 0! 0$ #29860000 1! #29870000 0! 1$ #29880000 1! #29890000 0! 0$ #29900000 1! #29910000 0! 1$ #29920000 1! #29930000 0! 0$ #29940000 1! #29950000 0! 1$ #29960000 1! #29970000 0! #29980000 1! #29990000 0! 0$ #30000000 1! #30010000 0! #30020000 1! #30030000 0! 1$ #30040000 1! #30050000 0! 0$ #30060000 1! #30070000 0! 1$ #30080000 1! #30090000 0! 0$ #30100000 1! #30110000 0! 1$ #30120000 1! #30130000 0! 0$ #30140000 1! #30150000 0! 1$ #30160000 1! #30170000 0! 0$ #30180000 1! #30190000 0! 1$ #30200000 1! #30210000 0! 0$ #30220000 1! #30230000 0! 1$ #30240000 1! #30250000 0! 0$ #30260000 1! #30270000 0! 1$ #30280000 1! #30290000 0! 0$ #30300000 1! #30310000 0! 1$ #30320000 1! #30330000 0! 0$ #30340000 1! #30350000 0! 1$ #30360000 1! #30370000 0! 0$ #30380000 1! #30390000 0! 1$ #30400000 1! #30410000 0! 0$ #30420000 1! #30430000 0! 1$ #30440000 1! #30450000 0! #30460000 1! #30470000 0! 0$ #30475000 1" #30480000 1! #30490000 0! x$ z$ #30500000 1! #30510000 0! x&" x(" x'" x%" x#" x"" x!" xU! xZ! xY! xX! xW! xV" x]" xU" xT" xS" xR" xQ" xP" xO" x\" x[" xZ" xX" xW" xN" xM" x]! x\! x[! x{! xd! xc! xb! xa! x`! x_! x^! x$" x|! xj! xi! xh! xg! xf! xe! x}! xk! x~! xr! xq! xp! xo! xn! xm! xl! xz! xy! xx! xw! xv! xu! xt! xs! xH" xG" xL" xF" xE" xD" xC" xB" xA" x@" xK" x?" x>" x=" x<" x;" x:" x9" xY" xJ" x8" x7" xI" x6" x5" x4" x3" x2" x1" xV! x0" x/" x." x-" x," x+" x*" x)" x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x* x9! x8! x7! x6! x5! x4! x3! x:! x2! x>! x) x] x!! x~ x} x| x{ xz xy xx xw xv xu xt xs xr x/! xq xp x.! x=! xo xn xm xl xk xj xi x-! xh xg xf xe xd xc xb x,! xa x` x7 x6 x5 x4 x3 x2 x1 x0 x> x= x< x; x: x9 x8 xP x? xQ xE xD xC xB xA x@ xR x[ xL xK xJ xI xH xG xF xS xO xN xM x0! x1! x;! x" 1?" 1@" 1A" 1B" 1C" 1D" 1E" 1F" 1G" 1H" 1I" 1J" 1K" 1L" 1M" 1N" 1O" 1P" 1Q" 1R" 1S" 1T" 1U" 1V" 1W" 1X" 1Y" 1Z" 1[" 1\" 1]" z#! z$! z%! z&! z'! z(! z)! z*! z+! z) z* z:! z>! z2! z3! z4! z5! z6! z7! z8! z9! z"! z] zK! zJ! z?! z=! z z? z@ zA zB zC zD zE zF zG zH zI zJ zK zL zM zN zO z+ z, z- z. #30955000 0" #30960000 1! #30970000 0! #30975000 1" #30980000 1! #30990000 0! #30995000 0" #31000000 1! #31010000 0! #31020000 1! #31030000 0! 0$ #31035000 1# #31040000 1! #31050000 0! 1$ #31060000 1! #31070000 0! #31080000 1! #31090000 0! #31100000 1! #31110000 0! #31120000 1! #31130000 0! #31135000 0# #31140000 1! #31150000 0! 0$ #31160000 1! #31170000 0! #31175000 1# #31180000 1! #31190000 0! 1$ #31200000 1! #31210000 0! #31220000 1! #31230000 0! #31240000 1! #31250000 0! #31255000 0# 1" #31260000 1! #31270000 0! 0$ z$ #31280000 1! #31290000 0! #31295000 0" #31300000 1! #31310000 0! #31315000 1" #31320000 1! #31330000 0! #31340000 1! #31350000 0! #31355000 0" #31360000 1! #31370000 0! #31380000 1! #31390000 0! 1$ #31395000 1# #31400000 1! #31410000 0! 0$ #31415000 0# #31420000 1! #31430000 0! #31440000 1! #31450000 0! #31460000 1! #31470000 0! #31475000 1" #31480000 1! #31490000 0! 1$ z$ #31500000 1! #31510000 0! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x#! x$! x%! x&! x'! x(! x)! x*! x+! x:! x>! x2! x3! x4! x5! x6! x7! x8! x9! x"! x] x* x) xK! xJ! x?! x=! x x? x@ xA xB xC xD xE xF xG xH xI xJ xK xL xM xN xO x+ x, x- x. #31515000 0" #31520000 1! #31530000 0! #31535000 1" #31540000 1! #31550000 0! #31555000 0" #31560000 1! #31570000 0! #31580000 1! #31590000 0! x$ #31600000 1! #31610000 0! #31620000 1! #31630000 0! #31640000 1! #31650000 0! #31660000 1! #31670000 0! #31680000 1! #31690000 0! #31700000 1! #31710000 0! #31720000 1! #31730000 0! #31740000 1! #31750000 0! #31760000 1! #31770000 0! #31780000 1! #31790000 0! #31800000 1! #31810000 0! 0$ #31820000 1! #31830000 0! x$ #31840000 1! #31850000 0! #31860000 1! #31870000 0! #31880000 1! #31890000 0! #31900000 1! #31910000 0! #31920000 1! #31930000 0! #31940000 1! #31950000 0! #31960000 1! #31970000 0! #31980000 1! #31990000 0! #32000000 1! #32010000 0! 0$ #32015000 1# #32020000 1! #32030000 0! x$ #32035000 0# #32040000 1! #32050000 0! #32060000 1! #32070000 0! #32080000 1! #32090000 0! #32100000 1! #32110000 0! #32120000 1! #32130000 0! #32140000 1! #32150000 0! #32160000 1! #32170000 0! #32180000 1! #32190000 0! #32200000 1! #32210000 0! #32220000 1! #32230000 0! #32240000 1! #32250000 0! #32260000 1! #32270000 0! #32280000 1! #32290000 0! #32300000 1! #32310000 0! #32320000 1! #32330000 0! #32340000 1! #32350000 0! #32360000 1! #32370000 0! #32380000 1! #32390000 0! #32400000 1! #32410000 0! #32420000 1! #32430000 0! #32440000 1! #32450000 0! #32460000 1! #32470000 0! #32480000 1! #32490000 0! #32500000 1! #32510000 0! #32520000 1! #32530000 0! #32540000 1! #32550000 0! #32560000 1! #32570000 0! 0$ #32575000 1# #32580000 1! #32590000 0! 1$ #32600000 1! #32610000 0! 0$ #32620000 1! #32630000 0! 1$ #32640000 1! #32650000 0! 0$ #32660000 1! #32670000 0! 1$ #32680000 1! #32690000 0! 0$ #32700000 1! #32710000 0! 1$ #32720000 1! #32730000 0! 0$ #32740000 1! #32750000 0! x$ #32755000 0# #32760000 1! #32770000 0! #32780000 1! #32790000 0! #32800000 1! #32810000 0! #32820000 1! #32830000 0! #32840000 1! #32850000 0! #32860000 1! #32870000 0! #32880000 1! #32890000 0! #32900000 1! #32910000 0! #32920000 1! #32930000 0! #32940000 1! #32950000 0! 1$ #32955000 1# #32960000 1! #32970000 0! x$ #32975000 0# #32980000 1! #32990000 0! 0$ #32995000 1# #33000000 1! #33010000 0! x$ #33015000 0# #33020000 1! #33030000 0! #33040000 1! #33050000 0! #33060000 1! #33070000 0! #33080000 1! #33090000 0! #33100000 1! #33110000 0! #33120000 1! #33130000 0! #33140000 1! #33150000 0! #33160000 1! #33170000 0! #33180000 1! #33190000 0! #33200000 1! #33210000 0! #33220000 1! #33230000 0! #33240000 1! #33250000 0! #33260000 1! #33270000 0! #33280000 1! #33290000 0! #33300000 1! #33310000 0! 1$ #33315000 1# #33320000 1! #33330000 0! 0$ #33340000 1! #33350000 0! 1$ #33360000 1! #33370000 0! 0$ #33380000 1! #33390000 0! x$ #33395000 0# #33400000 1! #33410000 0! #33420000 1! #33430000 0! #33440000 1! #33450000 0! #33460000 1! #33470000 0! #33480000 1! #33490000 0! #33500000 1! #33510000 0! #33520000 1! #33530000 0! #33540000 1! #33550000 0! #33560000 1! #33570000 0! #33580000 1! #33590000 0! #33600000 1! #33610000 0! 0$ #33615000 1# #33620000 1! #33630000 0! x$ #33635000 0# #33640000 1! #33650000 0! #33660000 1! #33670000 0! #33680000 1! #33690000 0! #33700000 1! #33710000 0! #33720000 1! #33730000 0! #33740000 1! #33750000 0! #33760000 1! #33770000 0! #33780000 1! #33790000 0! #33800000 1! #33810000 0! #33820000 1! #33830000 0! #33840000 1! #33850000 0! #33860000 1! #33870000 0! #33880000 1! #33890000 0! #33900000 1! #33910000 0! #33920000 1! #33930000 0! #33940000 1! #33950000 0! 1$ #33955000 1# #33960000 1! #33970000 0! x$ #33975000 0# #33980000 1! #33990000 0! 0$ #34000000 1! #34010000 0! x$ #34020000 1! #34030000 0! #34040000 1! #34050000 0! #34060000 1! #34070000 0! #34080000 1! #34090000 0! #34100000 1! #34110000 0! #34120000 1! #34130000 0! #34140000 1! #34150000 0! #34160000 1! #34170000 0! 1$ #34175000 1# #34180000 1! #34190000 0! x$ #34195000 0# #34200000 1! #34210000 0! #34220000 1! #34230000 0! #34240000 1! #34250000 0! #34260000 1! #34270000 0! #34280000 1! #34290000 0! #34300000 1! #34310000 0! #34320000 1! #34330000 0! #34340000 1! #34350000 0! #34360000 1! #34370000 0! #34380000 1! #34390000 0! #34400000 1! #34410000 0! #34420000 1! #34430000 0! 1$ #34435000 1# #34440000 1! #34450000 0! 0$ #34455000 1" #34460000 1! #34470000 0! z$ #34480000 1! #34490000 0! #34495000 0" #34500000 1! #34510000 0! #34515000 1" #34520000 1! #34530000 0! #34540000 1! #34550000 0! #34555000 0" #34560000 1! #34570000 0! #34580000 1! #34590000 0! 1$ #34595000 0# #34600000 1! #34610000 0! 0$ #34620000 1! #34630000 0! #34635000 1# #34640000 1! #34650000 0! #34655000 0# #34660000 1! #34670000 0! #34675000 1" #34680000 1! #34690000 0! z$ #34700000 1! #34710000 0! 0U! 0V! 0W! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0f! 0g! 0h! 0i! 0j! 0k! 0l! 0m! 0n! 0o! 0p! 0q! 0r! 0s! 0t! 0u! 0v! 0w! 0x! 0y! 0z! 0{! 0|! 0}! 0~! 0!" 0"" 0#" 0$" 0%" 0&" 0'" 0(" 0)" 0*" 0+" 0," 0-" 0." 0/" 00" 01" 02" 03" 04" 05" 06" 07" 08" 09" 0:" 0;" 0<" 0=" 0>" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 0* 0) 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* x) xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 0] 0"! 0#! 0$! 0%! 0&! 0'! 0(! 0)! 0*! 0+! 0>! 02! 03! 04! 05! 06! 07! 08! 09! 0:! 1* 0O 0N 0M 0L 0K 0J 0I 0H 0S 0G 0F 0E 0D 0C 0B 0A 0@ 0R 0[ 0\ 0^ 0T 0_ 0X 0U 0Q 0? 0> 0= 0< 0; 0: 09 08 0P 07 06 05 04 03 02 01 00 0. 0- 0, 0+ 0` 0a 0b 0c 0d 0e 0f 0g 0,! 0h 0i 0j 0k 0l 0m 0n 0o 0-! 01! 0;! 0K! 00! 0J! 0" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x) x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 1] 1"! 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1:! 1* 1O 1N 1M 1L 1K 1J 1I 1H 1S 1G 1F 1E 1D 1C 1B 1A 1@ 1R 1[ 1\ 1^ 1T 1_ 1X 1U 1Q 1? 1> 1= 1< 1; 1: 19 18 1P 17 16 15 14 13 12 11 10 1. 1- 1, 1+ 1` 1a 1b 1c 1d 1e 1f 1g 1,! 1h 1i 1j 1k 1l 1m 1n 1o 1-! 11! 1;! 1K! 10! 1J! 1" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" 1U! 1V! 1W! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1d! 1e! 1f! 1g! 1h! 1i! 1j! 1k! 1l! 1m! 1n! 1o! 1p! 1q! 1r! 1s! 1t! 1u! 1v! 1w! 1x! 1y! 1z! 1{! 1|! 1}! 1~! 1!" 1"" 1#" 1$" 1%" 1&" 1'" 1(" 1)" 1*" 1+" 1," 1-" 1." 1/" 10" 11" 12" 13" 14" 15" 16" 17" 18" 19" 1:" 1;" 1<" 1=" 1>" 1?" 1@" 1A" 1B" 1C" 1D" 1E" 1F" 1G" 1H" 1I" 1J" 1K" 1L" 1M" 1N" 1O" 1P" 1Q" 1R" 1S" 1T" 1U" 1V" 1W" 1X" 1Y" 1Z" 1[" 1\" 1]" z) z] z"! z#! z$! z%! z&! z'! z(! z)! z*! z+! z>! z2! z3! z4! z5! z6! z7! z8! z9! z:! z* zO zN zM zL zK zJ zI zH zS zG zF zE zD zC zB zA z@ zR z[ z\ z^ zT z_ zX zU zQ z? z> z= z< z; z: z9 z8 zP z7 z6 z5 z4 z3 z2 z1 z0 z. z- z, z+ z` za zb zc zd ze zf zg z,! zh zi zj zk zl zm zn zo z-! z1! z;! zK! z0! zJ! z" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1:! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1"! 1] 1* 1) 1K! 1J! 1?! 1=! 1 1? 1@ 1A 1B 1C 1D 1E 1F 1G 1H 1I 1J 1K 1L 1M 1N 1O 1+ 1, 1- 1. #66735000 0" #66740000 1! #66750000 0! #66760000 1! #66770000 0! #66775000 1" #66780000 1! #66790000 0! #66800000 1! #66810000 0! #66815000 0" #66820000 1! #66830000 0! #66840000 1! #66850000 0! 1$ #66860000 1! #66870000 0! 0$ #66880000 1! #66890000 0! #66895000 1# #66900000 1! #66910000 0! #66915000 0# #66920000 1! #66930000 0! #66935000 1" #66940000 1! #66950000 0! z$ #66960000 1! #66970000 0! #66975000 0" #66980000 1! #66990000 0! #66995000 1" #67000000 1! #67010000 0! #67015000 0" #67020000 1! #67030000 0! #67040000 1! #67050000 0! 0$ #67060000 1! #67070000 0! #67080000 1! #67090000 0! #67100000 1! #67110000 0! #67120000 1! #67130000 0! #67140000 1! #67150000 0! #67160000 1! #67170000 0! #67180000 1! #67190000 0! #67200000 1! #67210000 0! #67220000 1! #67230000 0! #67240000 1! #67250000 0! #67260000 1! #67270000 0! #67280000 1! #67290000 0! #67300000 1! #67310000 0! #67320000 1! #67330000 0! #67340000 1! #67350000 0! #67360000 1! #67370000 0! #67380000 1! #67390000 0! #67400000 1! #67410000 0! #67420000 1! #67430000 0! #67440000 1! #67450000 0! #67460000 1! #67470000 0! #67480000 1! #67490000 0! #67500000 1! #67510000 0! #67520000 1! #67530000 0! #67540000 1! #67550000 0! #67560000 1! #67570000 0! #67580000 1! #67590000 0! #67600000 1! #67610000 0! #67620000 1! #67630000 0! #67640000 1! #67650000 0! #67660000 1! #67670000 0! #67680000 1! #67690000 0! #67700000 1! #67710000 0! #67720000 1! #67730000 0! #67740000 1! #67750000 0! #67760000 1! #67770000 0! #67780000 1! #67790000 0! #67800000 1! #67810000 0! #67820000 1! #67830000 0! #67840000 1! #67850000 0! #67860000 1! #67870000 0! #67880000 1! #67890000 0! #67900000 1! #67910000 0! #67920000 1! #67930000 0! #67940000 1! #67950000 0! #67960000 1! #67970000 0! #67980000 1! #67990000 0! #68000000 1! #68010000 0! #68020000 1! #68030000 0! #68040000 1! #68050000 0! #68060000 1! #68070000 0! #68080000 1! #68090000 0! #68100000 1! #68110000 0! #68120000 1! #68130000 0! #68140000 1! #68150000 0! #68160000 1! #68170000 0! #68180000 1! #68190000 0! #68200000 1! #68210000 0! #68220000 1! #68230000 0! #68240000 1! #68250000 0! #68260000 1! #68270000 0! #68280000 1! #68290000 0! #68300000 1! #68310000 0! #68320000 1! #68330000 0! #68340000 1! #68350000 0! #68360000 1! #68370000 0! #68380000 1! #68390000 0! #68400000 1! #68410000 0! #68420000 1! #68430000 0! #68440000 1! #68450000 0! #68460000 1! #68470000 0! #68480000 1! #68490000 0! #68500000 1! #68510000 0! #68520000 1! #68530000 0! #68540000 1! #68550000 0! #68560000 1! #68570000 0! #68580000 1! #68590000 0! #68600000 1! #68610000 0! #68620000 1! #68630000 0! #68640000 1! #68650000 0! #68660000 1! #68670000 0! #68680000 1! #68690000 0! #68700000 1! #68710000 0! #68720000 1! #68730000 0! #68740000 1! #68750000 0! #68760000 1! #68770000 0! #68780000 1! #68790000 0! #68800000 1! #68810000 0! #68820000 1! #68830000 0! #68840000 1! #68850000 0! #68860000 1! #68870000 0! #68880000 1! #68890000 0! #68900000 1! #68910000 0! #68920000 1! #68930000 0! #68940000 1! #68950000 0! #68960000 1! #68970000 0! #68980000 1! #68990000 0! #69000000 1! #69010000 0! #69020000 1! #69030000 0! #69040000 1! #69050000 0! #69060000 1! #69070000 0! #69080000 1! #69090000 0! #69100000 1! #69110000 0! #69120000 1! #69130000 0! #69140000 1! #69150000 0! #69160000 1! #69170000 0! #69180000 1! #69190000 0! #69200000 1! #69210000 0! #69220000 1! #69230000 0! #69240000 1! #69250000 0! #69260000 1! #69270000 0! #69280000 1! #69290000 0! #69300000 1! #69310000 0! #69320000 1! #69330000 0! #69340000 1! #69350000 0! #69360000 1! #69370000 0! #69380000 1! #69390000 0! #69400000 1! #69410000 0! #69420000 1! #69430000 0! #69440000 1! #69450000 0! #69460000 1! #69470000 0! #69480000 1! #69490000 0! #69500000 1! #69510000 0! #69520000 1! #69530000 0! #69540000 1! #69550000 0! #69560000 1! #69570000 0! #69580000 1! #69590000 0! #69600000 1! #69610000 0! #69620000 1! #69630000 0! #69640000 1! #69650000 0! #69660000 1! #69670000 0! #69680000 1! #69690000 0! #69700000 1! #69710000 0! #69720000 1! #69730000 0! #69740000 1! #69750000 0! #69760000 1! #69770000 0! #69780000 1! #69790000 0! #69800000 1! #69810000 0! #69820000 1! #69830000 0! #69840000 1! #69850000 0! #69860000 1! #69870000 0! #69880000 1! #69890000 0! #69900000 1! #69910000 0! #69915000 1" #69920000 1! #69930000 0! z$ #69940000 1! #69950000 0! #69955000 0" #69960000 1! #69970000 0! #69975000 1" #69980000 1! #69990000 0! #70000000 1! #70010000 0! #70015000 0" #70020000 1! #70030000 0! #70040000 1! #70050000 0! 1$ #70060000 1! #70070000 0! 0$ #70080000 1! #70090000 0! #70095000 1# #70100000 1! #70110000 0! #70115000 0# #70120000 1! #70130000 0! #70135000 1" #70140000 1! #70150000 0! z$ #70160000 1! #70170000 0! #70175000 0" #70180000 1! #70190000 0! #70200000 1! #70210000 0! #70215000 1" #70220000 1! #70230000 0! #70240000 1! #70250000 0! #70255000 0" #70260000 1! #70270000 0! #70280000 1! #70290000 0! 1$ #70295000 1# #70300000 1! #70310000 0! 0$ #70320000 1! #70330000 0! #70335000 0# #70340000 1! #70350000 0! #70360000 1! #70370000 0! #70375000 1" #70380000 1! #70390000 0! 1$ z$ #70400000 1! #70410000 0! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" x," x-" x." x/" x0" x1" x2" x3" x4" x5" x6" x7" x8" x9" x:" x;" x<" x=" x>" x?" x@" xA" xB" xC" xD" xE" xF" xG" xH" xI" xJ" xK" xL" xM" xN" xO" xP" xQ" xR" xS" xT" xU" xV" xW" xX" xY" xZ" x[" x\" x]" x) x] x"! x#! x$! x%! x&! x'! x(! x)! x*! x+! x>! x2! x3! x4! x5! x6! x7! x8! x9! x:! x* xO xN xM xL xK xJ xI xH xS xG xF xE xD xC xB xA x@ xR x[ x\ x^ xT x_ xX xU xQ x? x> x= x< x; x: x9 x8 xP x7 x6 x5 x4 x3 x2 x1 x0 x. x- x, x+ x` xa xb xc xd xe xf xg x,! xh xi xj xk xl xm xn xo x-! x1! x;! xK! x0! xJ! x" 0?" 0@" 0A" 0B" 0C" 0D" 0E" 0F" 0G" 0H" 0I" 0J" 0K" 0L" 0M" 0N" 0O" 0P" 0Q" 0R" 0S" 0T" 0U" 0V" 0W" 0X" 0Y" 0Z" 0[" 0\" 0]" 1) 1] 1"! 1#! 1$! 1%! 1&! 1'! 1(! 1)! 1*! 1+! 1>! 12! 13! 14! 15! 16! 17! 18! 19! 1:! 1* 1O 1N 1M 1L 1K 1J 1I 1H 1S 1G 1F 1E 1D 1C 1B 1A 1@ 1R 1[ 1\ 1^ 1T 1_ 1X 1U 1Q 1? 1> 1= 1< 1; 1: 19 18 1P 17 16 15 14 13 12 11 10 1. 1- 1, 1+ 1` 1a 1b 1c 1d 1e 1f 1g 1,! 1h 1i 1j 1k 1l 1m 1n 1o 1-! 11! 1;! 1K! 10! 1J! 1 STIL # # Original File: "exp1.vcd.fsdb" # # Target File: "exp1.stil " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.vcd.fsdb"; {#### INPUT VECTOR FILE ####} tabular_format novas_fsdb; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} inputs BPCCE, CFG66, S_CFN_L, MSK_IN, P_GNT_L, P_IDSEL, P_LOCK_L, P_M66EN, S_SERR_L, P_CLK, P_RESET_L, S_CLKIN, TDI, TMS, TCK, TRST_L, P_VIO, S_VIO, MS0, MS1; inputs S_REQ_L[8:0]; outputs P_SERR_L, P_REQ_L, S_RESET_L, TDO, ENUM_L, LOO; outputs S_GNT_L[8:0]; outputs S_CLKOUT[9:0]; bidirects S_M66EN, P_DEVSEL_L, P_FRAME_L, P_IRDY_L, P_PAR, P_PERR_L, P_STOP_L, P_TRDY_L, S_DEVSEL_L, S_FRAME_L, S_IRDY_L, S_LOCK_L, S_PAR, S_PERR_L, S_STOP_L, S_TRDY_L; bidirects GPIO[3:0]; bidirects P_AD[31:0]; bidirects P_CBE[3:0]; bidirects S_AD[31:0]; bidirects S_CBE[3:0]; outputs { #### These are actually bidirect control signals #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into STIL format # #======================================================================# } proc_block begin { #### state character translations for 'VCD'->'STIL'#### } STATE_TRANS 'x'->'N', 'X'->'N', 'z'->'Z' ; STATE_TRANS outputs '0'->'L', '1'->'H', 'Z'->'T', 'z'->'T'; { #### tell vtran how to determine bidirect signal direction #### } bidirect_control S_M66EN = output when xs_m66en_gmux_out = 0; bidirect_control P_DEVSEL_L = output when xp_devsel_gmux_out = 0; bidirect_control P_FRAME_L = output when xp_frame_gmux_out = 0; bidirect_control P_IRDY_L = output when xp_irdy_gmux_out = 0; bidirect_control P_PAR = output when xp_par_gmux_out = 0; bidirect_control P_PERR_L = output when xp_perr_gmux_out = 0; bidirect_control P_STOP_L = output when xp_stop_gmux_out = 0; bidirect_control P_TRDY_L = output when xp_trdy_gmux_out = 0; bidirect_control S_DEVSEL_L = output when xs_devsel_gmux_out = 0; bidirect_control S_FRAME_L = output when xs_frame_gmux_out = 0; bidirect_control S_IRDY_L = output when xs_irdy_gmux_out = 0; bidirect_control S_LOCK_L = output when xs_lock_gmux_out = 0; bidirect_control S_PAR = output when xs_par_gmux_out = 0; bidirect_control S_PERR_L = output when xs_perr_gmux_out = 0; bidirect_control S_STOP_L = output when xs_stop_gmux_out = 0; bidirect_control S_TRDY_L = output when xs_trdy_gmux_out = 0; bidirect_control GPIO[3] = output when x_gpio_3_gmux_out = 0; bidirect_control GPIO[2] = output when x_gpio_2_gmux_out = 0; bidirect_control GPIO[1] = output when x_gpio_1_gmux_out = 0; bidirect_control GPIO[0] = output when x_gpio_0_gmux_out = 0; bidirect_control P_AD[31] = output when xp_ad31_gmux_out = 0; bidirect_control P_AD[30] = output when xp_ad30_gmux_out = 0; bidirect_control P_AD[29] = output when xp_ad29_gmux_out = 0; bidirect_control P_AD[28] = output when xp_ad28_gmux_out = 0; bidirect_control P_AD[27] = output when xp_ad27_gmux_out = 0; bidirect_control P_AD[26] = output when xp_ad26_gmux_out = 0; bidirect_control P_AD[25] = output when xp_ad25_gmux_out = 0; bidirect_control P_AD[24] = output when xp_ad24_gmux_out = 0; bidirect_control P_AD[23] = output when xp_ad23_gmux_out = 0; bidirect_control P_AD[22] = output when xp_ad22_gmux_out = 0; bidirect_control P_AD[21] = output when xp_ad21_gmux_out = 0; bidirect_control P_AD[20] = output when xp_ad20_gmux_out = 0; bidirect_control P_AD[19] = output when xp_ad19_gmux_out = 0; bidirect_control P_AD[18] = output when xp_ad18_gmux_out = 0; bidirect_control P_AD[17] = output when xp_ad17_gmux_out = 0; bidirect_control P_AD[16] = output when xp_ad16_gmux_out = 0; bidirect_control P_AD[15] = output when xp_ad15_gmux_out = 0; bidirect_control P_AD[14] = output when xp_ad14_gmux_out = 0; bidirect_control P_AD[13] = output when xp_ad13_gmux_out = 0; bidirect_control P_AD[12] = output when xp_ad12_gmux_out = 0; bidirect_control P_AD[11] = output when xp_ad11_gmux_out = 0; bidirect_control P_AD[10] = output when xp_ad10_gmux_out = 0; bidirect_control P_AD[9] = output when xp_ad9_gmux_out = 0; bidirect_control P_AD[8] = output when xp_ad8_gmux_out = 0; bidirect_control P_AD[7] = output when xp_ad7_gmux_out = 0; bidirect_control P_AD[6] = output when xp_ad6_gmux_out = 0; bidirect_control P_AD[5] = output when xp_ad5_gmux_out = 0; bidirect_control P_AD[4] = output when xp_ad4_gmux_out = 0; bidirect_control P_AD[3] = output when xp_ad3_gmux_out = 0; bidirect_control P_AD[2] = output when xp_ad2_gmux_out = 0; bidirect_control P_AD[1] = output when xp_ad1_gmux_out = 0; bidirect_control P_AD[0] = output when xp_ad0_gmux_out = 0; bidirect_control P_CBE[3] = output when xp_cbe3_gmux_out = 0; bidirect_control P_CBE[2] = output when xp_cbe2_gmux_out = 0; bidirect_control P_CBE[1] = output when xp_cbe1_gmux_out = 0; bidirect_control P_CBE[0] = output when xp_cbe0_gmux_out = 0; bidirect_control S_AD[31] = output when xs_ad31_gmux_out = 0; bidirect_control S_AD[30] = output when xs_ad30_gmux_out = 0; bidirect_control S_AD[29] = output when xs_ad29_gmux_out = 0; bidirect_control S_AD[28] = output when xs_ad28_gmux_out = 0; bidirect_control S_AD[27] = output when xs_ad27_gmux_out = 0; bidirect_control S_AD[26] = output when xs_ad26_gmux_out = 0; bidirect_control S_AD[25] = output when xs_ad25_gmux_out = 0; bidirect_control S_AD[24] = output when xs_ad24_gmux_out = 0; bidirect_control S_AD[23] = output when xs_ad23_gmux_out = 0; bidirect_control S_AD[22] = output when xs_ad22_gmux_out = 0; bidirect_control S_AD[21] = output when xs_ad21_gmux_out = 0; bidirect_control S_AD[20] = output when xs_ad20_gmux_out = 0; bidirect_control S_AD[19] = output when xs_ad19_gmux_out = 0; bidirect_control S_AD[18] = output when xs_ad18_gmux_out = 0; bidirect_control S_AD[17] = output when xs_ad17_gmux_out = 0; bidirect_control S_AD[16] = output when xs_ad16_gmux_out = 0; bidirect_control S_AD[15] = output when xs_ad15_gmux_out = 0; bidirect_control S_AD[14] = output when xs_ad14_gmux_out = 0; bidirect_control S_AD[13] = output when xs_ad13_gmux_out = 0; bidirect_control S_AD[12] = output when xs_ad12_gmux_out = 0; bidirect_control S_AD[11] = output when xs_ad11_gmux_out = 0; bidirect_control S_AD[10] = output when xs_ad10_gmux_out = 0; bidirect_control S_AD[9] = output when xs_ad9_gmux_out = 0; bidirect_control S_AD[8] = output when xs_ad8_gmux_out = 0; bidirect_control S_AD[7] = output when xs_ad7_gmux_out = 0; bidirect_control S_AD[6] = output when xs_ad6_gmux_out = 0; bidirect_control S_AD[5] = output when xs_ad5_gmux_out = 0; bidirect_control S_AD[4] = output when xs_ad4_gmux_out = 0; bidirect_control S_AD[3] = output when xs_ad3_gmux_out = 0; bidirect_control S_AD[2] = output when xs_ad2_gmux_out = 0; bidirect_control S_AD[1] = output when xs_ad1_gmux_out = 0; bidirect_control S_AD[0] = output when xs_ad0_gmux_out = 0; bidirect_control S_CBE[3] = output when xs_cbe3_gmux_out = 0; bidirect_control S_CBE[2] = output when xs_cbe2_gmux_out = 0; bidirect_control S_CBE[1] = output when xs_cbe1_gmux_out = 0; bidirect_control S_CBE[0] = output when xs_cbe0_gmux_out = 0; bidirect_control S_CLKOUT[9] = output when 0; { #### collapse to cycle-based data, strobe all pins at 49 in cycle #### } {################################################################## The vector data in the VCD file is in a print-on-change format. The vector data for the STIL file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, sampling all input signals at 5 and all output signals at 98 nS into the 100 nS cycle, but sampling the two clock signals at 40 nS into the cycle ######################################################################} CYCLE = 100; ALIGN_TO_CYCLE 100 ALL_INPUTS @ 5, ALL_OUTPUTS @ 98, P_CLK @ 40 S_CLKIN @ 40; { ####now define some timing for the STIL file ####} { #### since VCD file does not contain this info separately ####} PINTYPE NRZ * @ 0, 0; { #### drive all inputs at 0 #### } PINTYPE STB * @ 98; { #### strobe all outputs at 15 #### } PINTYPE RZ P_CLK @ 0, 50; { #### clock waveform #### } PINTYPE RZ S_CLKIN @ 10, 60; { #### clock waveform #### } end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin TESTER_FORMAT STIL {#### OUTPUT FORMAT ####} -quote_names, INPUT_GROUP = "S_AD", { #### make separate group to reduce file size #### } INPUT_GROUP = "P_AD", { #### make separate group to reduce file size #### } ; DELETE_PINS { #### don't want these controls in STIL file #### } xs_m66en_gmux_out, xp_devsel_gmux_out, xp_frame_gmux_out, xp_irdy_gmux_out, xp_par_gmux_out, xp_perr_gmux_out, xp_stop_gmux_out, xp_trdy_gmux_out, xs_devsel_gmux_out, xs_frame_gmux_out, xs_irdy_gmux_out, xs_lock_gmux_out, xs_par_gmux_out, xs_perr_gmux_out, xs_stop_gmux_out, xs_trdy_gmux_out, x_gpio_3_gmux_out, x_gpio_2_gmux_out, x_gpio_1_gmux_out, x_gpio_0_gmux_out, xp_ad31_gmux_out, xp_ad30_gmux_out, xp_ad29_gmux_out, xp_ad28_gmux_out, xp_ad27_gmux_out, xp_ad26_gmux_out, xp_ad25_gmux_out, xp_ad24_gmux_out, xp_ad23_gmux_out, xp_ad22_gmux_out, xp_ad21_gmux_out, xp_ad20_gmux_out, xp_ad19_gmux_out, xp_ad18_gmux_out, xp_ad17_gmux_out, xp_ad16_gmux_out, xp_ad15_gmux_out, xp_ad14_gmux_out, xp_ad13_gmux_out, xp_ad12_gmux_out, xp_ad11_gmux_out, xp_ad10_gmux_out, xp_ad9_gmux_out, xp_ad8_gmux_out, xp_ad7_gmux_out, xp_ad6_gmux_out, xp_ad5_gmux_out, xp_ad4_gmux_out, xp_ad3_gmux_out, xp_ad2_gmux_out, xp_ad1_gmux_out, xp_ad0_gmux_out, xp_cbe3_gmux_out, xp_cbe2_gmux_out, xp_cbe1_gmux_out, xp_cbe0_gmux_out, xs_ad31_gmux_out, xs_ad30_gmux_out, xs_ad29_gmux_out, xs_ad28_gmux_out, xs_ad27_gmux_out, xs_ad26_gmux_out, xs_ad25_gmux_out, xs_ad24_gmux_out, xs_ad23_gmux_out, xs_ad22_gmux_out, xs_ad21_gmux_out, xs_ad20_gmux_out, xs_ad19_gmux_out, xs_ad18_gmux_out, xs_ad17_gmux_out, xs_ad16_gmux_out, xs_ad15_gmux_out, xs_ad14_gmux_out, xs_ad13_gmux_out, xs_ad12_gmux_out, xs_ad11_gmux_out, xs_ad10_gmux_out, xs_ad9_gmux_out, xs_ad8_gmux_out, xs_ad7_gmux_out, xs_ad6_gmux_out, xs_ad5_gmux_out, xs_ad4_gmux_out, xs_ad3_gmux_out, xs_ad2_gmux_out, xs_ad1_gmux_out, xs_ad0_gmux_out, xs_cbe3_gmux_out, xs_cbe2_gmux_out, xs_cbe1_gmux_out, xs_cbe0_gmux_out; target_file "exp1.stil"; {#### OUTPUT VECTOR FILE ####} end; rect_control P_AD[13] = output when xp_ad13_gmux_out = 0; bidirect_control P_AD[12] = output when xp_ad12_gmux_out = 0; bidirect_control P_AD[11] = output when xp_ad11_gmux_out = 0; bidirect_control P_AD[10] = output when xp_ad10_gmux_out = 0; bidirect_control P_AD[9] = output when xp_ad9_gmux_out = 0; bidirect_control P_AD[8] = output when xp_ad8_gmux_out = 0; bidirect_controINTERFACES/FSDB/FSDBSTIL/exp1.vcd.fsdb000064400001440000012000000244771103104161000175520ustar00jcosleystaff00000400000023HÙ>EZx¹/10psDec 3, 2001 16:19:45VERILOG-XL 2.7.s032$$.$]@cÏPÿÿÿÿÿÿÿÿ/×ùÿ™ù6X*Tue Nov 14 18:17:29 2006unknownsun4uSunOS5.7 Generic_106541-02FSDB_ENV_SYNC_CONTROL=NULL, FSDB_ENV_DUMP_SEQ_NUM=NULL, FSDB_ENV_MAX_GLITCH_NUM=NULL, FSDB_ENV_WRITER_MEM_LIMIT=NULL, FSDB_ENV_NOVAS_LOCK=NULL, FSDB_ENV_LOCK_FILE_LOC=NULLident_ffw_SOL2_DEB_6.1_4.1_SUNOS5.8_/opt/SUNWspro42/SC4.2/bin/cc_10172006þpcibridge_tbc print_bit_st gXýasync_tap_resetÕ3hift_in_Wgister_with_pausez]ert_overŽedtn~ýcheck_TDO_for_2$&+boundary >.run_allstates¬[¯uctioÐÃDial_dataI¿cre@_ou^scellsî_1?c0 # G1 Hz?ŽinX P ÉinitQizep'0Ȭ (&/ê/&/&/01_sampl–2¢10/"bidiLds_ZìK);&1&1',1'&1:highz;£exGú2"*£defaulÄ*5 +8capture+Ãbypasss*) çœ.'8*,38*->1-!>1  +b ø °r¬chipwU_i–xT$errIH.‡Exs_m66ev r”r_gpio“rª'{ rÀ'S2ÒÖ'S3Òìkp_adi$PðÇáÅ*òÃ>ã4ÐRô5Áfå6Òzö7ÃŽç8Ô¢ø9Ŷé“qÊ&ëß&ìô&Í &Î &Ï 3&Ð H&Ñ ]&Ò r&Ó œ q2Ó œ&Ó ±&$À  Æ&6óÛ&óð&à  &Ä  &Å  /&Æ  D&Ç  Yñ3Ç  n&Ç  ƒ£cbeã˜&ã­&$Ø Â&6Ù ׫devselÓÑframzR ²irdyѤpaÆ .Ð&¹ B±reqÐW°storqd¢t'Xyts'O —pÖ —aÎ —rÎ –cÎ ÞðÎ òáÎ òÎ š pÎ ŸaÎ žrî V&  k&$Û €&6Ü •&Ý ‹"‘Þ ¿&ðÔ&$ñé&6òþ& ãî (&Ö =&Ï# "‘Ð# g&Ñ# |&$Ò# ‘&6Ó# ¦&Ô# »&Õ# Ð&,óåýî ú&Ó¡' $&ã9&×N&×c©) x½( °gntü¥&ü²&$üÄQÔ Ì&Ô Ù&$Ô æ&6Ô ó&Ô h6Q'Ÿ ±lockÑ"£&±7Ð&ªK±' `±' u&É Šq^Y_ac•G¹Nbsda®hýýÿ!¿TCKTMSTDIFOTRST_LBPCCECFG66S_CFN|P_SERRh VM66EN GPIO[3] ¬2L ¹1L ¬ 0]MSK_IRAD[3bÍC»29MÍ8[Í7MÍ6[Û5MÍ4[ÛlÍmÛnÉk·1kÍkÛkÉkÍk Ûk!Éx  "×y  #Íz  $Ûk %©v &¶u'¬h(¹s)¦r*³q+¬½ ,¹½ -¬½ .¹} /DCBEÒ0ͱ1Û´2És3ZDEVSELg4MFRAMEt5ZGNŸ6EIDD7jRDYv8\LOCKb9HÙ:BPAR;hÙTÎ?S'v @ÍiA­ÕB͵C͵DÛµEɵF×µG͵HÛµIÉkJ×µK¥ÕL͵MÍkNÛµOÍnAÛµQÉk R×}  SÅw TÓa U­j VºiW§hX´iY¬fZ¹g[¦³!\³¡]  ^­_JCLKOUTÃ`'§a'«b'¯c'³d'·e'»f'¡g'£h'gin&^ jͽk͸lÍumK'^ nY&^ oFÆp&¥q&´ r&£s& ¢t&0¢u&¢v&¦w& hxMõyYõzKŠ{TRESEŽ2|uÑ1}˜WÎ ~&­ &§€& §&0ª ‚&ª ƒ&ª$„& §…&0p †]ë6‡kÆ!ˆWæ!‰R!YŠ’"Ó‹YO}5ŒLO9GVIŽTˆENUMmJ70‘Q71’ÿgmux_out“ÿxs_m66en_'V”U_gpio_0(V•&V1(V–&l2(V—&B3(V˜Mp_ad)V™Ó)TšÓ)R›Ó)PœÓ4(TÇ5(TžÛ6(TŸÏ7(T Ã8(T¡×9(T¢ó)I£è)J¤ô)K¥ô)L¦ô)M§é)N¨þ)O©ó)Pªô)Q«é)R¬Þ2)R­ô)R®ô)R¯ô)R°é)R±þ)R²ó)R³ô)R´é)Rµþ)R¶Ó3)R·ô)R¸”cbe)j¹ô)jºô)|»ô)|¼‰devsel(W½€frame(V¾–irdy(U¿‹par(TÀ³er)UÁ)PÂstop(bÖt+`Ä s,LÅÓ)tÆÓ)sÇÓ)rÈÓ)mÉÇ)lÊÛ)kËÏ)jÌÓ)iÍÇ)hÎÛ*LÏô)JÐô)KÑé)LÒþ)MÓó)NÔô)OÕé)PÖþ)Q×ó)RØÔ*LÙô)RÚô)RÛô)RÜô)RÝé)RÞþ)Rßó)Ràô)Ráé)RâÞ*Lãô)Rä”,Låô)jæô)|çô)|è”.Lé‹-Lê)N ë)Mì)Mí)Mî)Mï)Mð)Mñ)Mò‰,tóžlock(Uô”+Iõ³+Iö,|÷’,|ø) ùÿ! '' }Á:˜"† N œ@œ@N ESÔÀ­!j»"qI½g"à_8€u¡¯‰ó,Ü`-úê`+¸,@·Y¿wu³g÷ 1*›c19*+++*+ *+i / 8++* s9> œ5, 6™)&[ J*‡."ÎxJ-† IEÀz)@‚-¿º‹€&®-"a ÀÓD_P/8€W@-c=+¹hl1@ ©€‡â²0p g~@*©g#O"-ÆtL¿Y¬" ˜§ñ b!tSKyá ’[~5÷ ¶71® '¡U !… @Qù“°9W‘Q뇗 Yqø9 ?,sq« Ö<('°0oõÙšAÍþ@W‡÷ OÛ¨>IU‡q™(C/8ÝG'£ ,E} Ë0 ‘ÿ0 _°4 Ç0¹'%-Yê`2ÔJ1å T-¯êÆK/ ©é/ ©7 ‡"&*/ ¿*40&8 EöP1 i .yäV2 ¿Y4 ¿7 Q /¹S4 i0•!ne¥œW!z%ýC»M"àµF‡HC8€÷T÷gyD ŸRÙS"/éf`»ƒ0…¡ÿï­OÔw „4:˜L]x'|$o'Lœ( ¨“¹“\+fU#Ù‡K'V,Ë'QEŸK'#ªñK'GN¿qm•5Òªf,‹ '00.Wˆ[øïù ›‡»/•_–º(–° tgœ@Ë (9Yq 1E *Œ5‰ \O´ ,‡)s!r&+1?† ¸0- * … ŠI,&‡¼íI&8¾ŽB( \‰L©tu- * [ü&0(< '½!«¥/ :<±Ž'…q€ü#&;6/6&2 -25  35—,‡&5—56&,2& &/ 7»Ž,.QZ›Ü*(,, /W ¥É,(5* ù ù) îœ1Gµï%¢2ã'  }, [=*  ? 3" h2ƒ$+ò*V’m'/ 8$áÍIÄŸs!ã Ia¨X‰^L .™¿ô/*-!Ie#gn$ËÛQ -x $fnɶÀ#aš!³I"{#e "Iå $q ˜o#8'KI LÚa¨Røœ& / •  '@'- ' '@'- ' '@'-  ̲9­!&& ,9',E' 9, ' %, ' [ > ' 4  > ' Ö$ > ' 4 1 > ' 4 ' % 6&B W29), E' Jš…17C /, ' 4$ Æ]6H  >: > ' 4> ' 4>' 4>#' µ > ' 4.' µ ' 4 > '  ' 4  > ' 4' 4 ' °@!&+|Å”ù O >$ƒ"' 4$ > ' ô 8K °'= ô  80 /:)c;&e*c) d ¡7íÎ >. > .15 ÞÁ&/'X"&9°$°‰9R!q"+µÝQ‡ Þ!P 'ÆcÏPdVT,Ü`¦pF˜P\a À›Ab\8d9b¡+ò—päðoöN ˆ¸$pã ¤to'P.) 9pGIå ~3o¡,Pûo&q[,P»+r)r{¿ô '°r”) Oô+sT,P´+t,Pt,PÔ+u4,,@u,@v,@v,@w,@w,@w,€x4,,@x,@y,@y,@z,@z,@z,€{4,,@{,@|,@|,@},@},@},€~4,,@~,@,@,@€,@€*€Ô) Oí+€ +°fo' z²9ÏO˜)0_ø+‚Xo'° ‚²+ ƒ,Pr,PÒ+„2,P’,Pò+…R,,@†,@†,@†,@‡,@‡,@‡,€ˆR,,@‰,@‰,@‰,@Š,@Š,@Š,€‹R,,@Œ,@Œ,@Œ,@,@,@,€ŽR,,@,@Ÿ'°Ì+&,P€,PÚ+‘4,PŽ,Pè+’B,Pœ,Pö'°“V,P¶+”,Pv,PÖ+•6o'°•,Pê+–D,Pž,'P— (P¬+P˜Ÿ(P`o' ˜À+™ ,,P™ ÿš:+€šS)Oq,`Š,`¨,`Á,`ß,`ø+ ›+ ›/+€›H)0O¨)œ+œ&,PD([Cœb @%œg(LlëCq(Xv(L{Ëw*O*è *( O*( _*è ž*( O*( _‡'ŸP,Pª+ ,P^,P¸+P¡—(Pl,PÆ+P¢‡(Pz,—F'£.,Pˆ,Pâ+¤<,P–,Pð+¥J,P¤,Pþ+P¦*O‡8'§ ,Pf,—'¨,‡O(PÎ+©(,P‚,PÜ+Pª*O*_*È«*O*_ø+P¬*O*È­*O‡$(Pº+P®—W(Pn,PÈ+¯",P|,—,'°0,PŠ,Pä+±>,‡I(‡E'²L,P¦+³,PZ,‡P'´,Ph,PÂ+µ,Pv,PÐ+¶*,P„,PÞ+·8,—M(Pì+¸F,P ,Pú+P¹—h(P®+º,Pb,P¼+P»—=(Pp,PÊ+¼$,P~,PØ+½2,PŒ,Pæ+¾@,Pš,‡q'¿N,‡6'À,P\(!ðú qq"cÏP“ñ 1BN^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÎÞîþ.>N^n~Žž®¾ÊÖâîú   & 6 F V f v † – ¦ ¶ Æ Ö æ ö   & 6 F V f v † – ¦ ¶ Æ Ö æ ö   & 6 F V f v † – ¦ ¶ Æ Ö æ ö   & 6 F V f v † – ¦ ¶ Æ Ö æ ö   & 6 F V f v † – ¦ ¶ Æ Ö æ ö&6FVfv†–¦¶ÆÖæö&6FVfINTERFACES/FSDB/FSDBAGILENT93K/000075500001440000012000000000001103104161000160435ustar00jcosleystaff00000400000023INTERFACES/FSDB/FSDBAGILENT93K/exp1.vcd000064400001440000012000002132761103104161000174310ustar00jcosleystaff00000400000023$date Apr 21, 1997 11:46:29 $end $version VERILOG-XL 2.3.3 $end $timescale 10ps $end $scope module test $end $scope module top $end $var wire 1 ! E2_CPURST $end $var wire 1 " E2_INTREQ2 $end $var wire 1 # E2_INTREQ1 $end $var wire 1 $ E2_INTREQ0 $end $var wire 1 % C2_LBUSRDY $end $var wire 1 & C1_RSFTEN $end $var wire 1 ' C2_CPUACKN $end $var wire 1 ( S2_EVTSET2 $end $var wire 1 ) S2_EVTSET1 $end $var wire 1 * S2_EVTSET0 $end $var wire 1 + S2_BCMD5 $end $var wire 1 , S2_BCMD4 $end $var wire 1 - S2_BCMD3 $end $var wire 1 . S2_BCMD2 $end $var wire 1 / S2_BCMD1 $end $var wire 1 0 S2_BCMD0 $end $var wire 1 1 S2_SRDSP $end $var wire 1 2 S2_SRMD $end $var wire 1 3 S2_ITLB $end $var wire 1 4 TC2_TLBREAD $end $var wire 1 5 S1_CEXEC6 $end $var wire 1 6 S1_CEXEC5 $end $var wire 1 7 S1_CEXEC4 $end $var wire 1 8 S1_CEXEC3 $end $var wire 1 9 S1_CEXEC2 $end $var wire 1 : S1_CEXEC1 $end $var wire 1 ; S1_CEXEC0 $end $var wire 1 < S2_CDI15 $end $var wire 1 = S2_CDI14 $end $var wire 1 > S2_CDI13 $end $var wire 1 ? S2_CDI12 $end $var wire 1 @ S2_CDI11 $end $var wire 1 A S2_CDI10 $end $var wire 1 B S2_CDI9 $end $var wire 1 C S2_CDI8 $end $var wire 1 D S2_CDI7 $end $var wire 1 E S2_CDI6 $end $var wire 1 F S2_CDI5 $end $var wire 1 G S2_CDI4 $end $var wire 1 H S2_CDI3 $end $var wire 1 I S2_CDI2 $end $var wire 1 J S2_CDI1 $end $var wire 1 K S2_CDI0 $end $var wire 1 L S2_CDIE $end $var wire 1 M S1_CNOEXEC $end $var wire 1 N S2_CSLSRS $end $var wire 3 O L2_LDB31 [2:0] $end $var wire 1 P L2_LDB30 $end $var wire 1 Q L2_LDB29 $end $var wire 1 R L2_LDB28 $end $var wire 1 S L2_LDB27 $end $var wire 1 T L2_LDB26 $end $var wire 1 U L2_LDB25 $end $var wire 1 V L2_LDB24 $end $var wire 1 W L2_LDB23 $end $var wire 1 X L2_LDB22 $end $var wire 1 Y L2_LDB21 $end $var wire 1 Z L2_LDB20 $end $var wire 1 [ L2_LDB19 $end $var wire 1 \ L2_LDB18 $end $var wire 1 ] L2_LDB17 $end $var wire 1 ^ L2_LDB16 $end $var wire 1 _ L2_LDB15 $end $var wire 1 ` L2_LDB14 $end $var wire 1 a L2_LDB13 $end $var wire 1 b L2_LDB12 $end $var wire 1 c L2_LDB11 $end $var wire 1 d L2_LDB10 $end $var wire 1 e L2_LDB9 $end $var wire 1 f L2_LDB8 $end $var wire 1 g L2_LDB7 $end $var wire 1 h L2_LDB6 $end $var wire 1 i L2_LDB5 $end $var wire 1 j L2_LDB4 $end $var wire 1 k L2_LDB3 $end $var wire 1 l L2_LDB2 $end $var wire 1 m L2_LDB1 $end $var wire 1 n L2_LDB0 $end $var wire 1 o T2_TLBMIS $end $var wire 1 p T2_TLBERR $end $var wire 1 q Y1_CMCPU $end $var wire 1 r YA_ASM $end $var wire 1 s YA_TM2 $end $var wire 1 t U2_ASRTBMK $end $var wire 1 u Y1_STPCPU $end $var wire 1 v YA_HSTBY $end $var wire 1 w E2_RSTAJ $end $var wire 1 x S1_SSLEP $end $var wire 1 y S1_INTACK $end $var wire 1 z S2_IVECRDN $end $var wire 1 { S1_IVECWRN $end $var wire 1 | S2_SRBL $end $var wire 1 } S2_SRIMASK3 $end $var wire 1 ~ S2_SRIMASK2 $end $var wire 1 !! S2_SRIMASK1 $end $var wire 1 "! S2_SRIMASK0 $end $var wire 1 #! S1_ASLIRW $end $var wire 1 $! S1_ASLIRL $end $var wire 1 %! S2_ASPID2 $end $var wire 1 &! S2_ASPID1 $end $var wire 1 '! S2_ASPID0 $end $var wire 1 (! S2_CPUST15 $end $var wire 1 )! S2_CPUST14 $end $var wire 1 *! S2_CPUST13 $end $var wire 1 +! S2_CPUST12 $end $var wire 1 ,! S2_CPUST11 $end $var wire 1 -! S2_CPUST10 $end $var wire 1 .! S2_CPUST9 $end $var wire 1 /! S2_CPUST8 $end $var wire 1 0! S2_CPUST7 $end $var wire 1 1! S2_CPUST6 $end $var wire 1 2! S2_CPUST5 $end $var wire 1 3! S2_CPUST4 $end $var wire 1 4! S2_CPUST3 $end $var wire 1 5! S2_CPUST2 $end $var wire 1 6! S2_CPUST1 $end $var wire 1 7! S2_CPUST0 $end $var wire 1 8! SA_CPUDMY17 $end $var wire 1 9! SA_CPUDMY16 $end $var wire 1 :! SA_CPUDMY15 $end $var wire 1 ;! SA_CPUDMY14 $end $var wire 1 ! SA_CPUDMY11 $end $var wire 1 ?! SA_CPUDMY10 $end $var wire 1 @! SA_CPUDMY9 $end $var wire 1 A! SA_CPUDMY8 $end $var wire 1 B! SA_CPUDMY7 $end $var wire 1 C! SA_CPUDMY6 $end $var wire 1 D! SA_CPUDMY5 $end $var wire 1 E! SA_CPUDMY4 $end $var wire 1 F! SA_CPUDMY3 $end $var wire 1 G! SA_CPUDMY2 $end $var wire 1 H! SA_CPUDMY1 $end $var wire 1 I! SA_CPUDMY0 $end $var wire 1 J! U2_BRKTYP0 $end $var wire 1 K! U2_BRKTYP1 $end $var wire 1 L! S2_LAB31 $end $var wire 1 M! S2_LAB30 $end $var wire 1 N! S2_LAB29 $end $var wire 1 O! S2_LAB28 $end $var wire 1 P! S2_LAB27 $end $var wire 1 Q! S2_LAB26 $end $var wire 1 R! S2_LAB25 $end $var wire 1 S! S2_LAB24 $end $var wire 1 T! S2_LAB23 $end $var wire 1 U! S2_LAB22 $end $var wire 1 V! S2_LAB21 $end $var wire 1 W! S2_LAB20 $end $var wire 1 X! S2_LAB19 $end $var wire 1 Y! S2_LAB18 $end $var wire 1 Z! S2_LAB17 $end $var wire 1 [! S2_LAB16 $end $var wire 1 \! S2_LAB15 $end $var wire 1 ]! S2_LAB14 $end $var wire 1 ^! S2_LAB13 $end $var wire 1 _! S2_LAB12 $end $var wire 1 `! S2_LAB11 $end $var wire 1 a! S2_LAB10 $end $var wire 1 b! S2_LAB9 $end $var wire 1 c! S2_LAB8 $end $var wire 1 d! S2_LAB7 $end $var wire 1 e! S2_LAB6 $end $var wire 1 f! S2_LAB5 $end $var wire 1 g! S2_LAB4 $end $var wire 1 h! S2_LAB3 $end $var wire 1 i! S2_LAB2 $end $var wire 1 j! S2_LAB1 $end $var wire 1 k! S2_LAB0 $end $var wire 1 l! S2_XAB15 $end $var wire 1 m! S2_XAB14 $end $var wire 1 n! S2_XAB13 $end $var wire 1 o! S2_XAB12 $end $var wire 1 p! S2_XAB11 $end $var wire 1 q! S2_XAB10 $end $var wire 1 r! S2_XAB9 $end $var wire 1 s! S2_XAB8 $end $var wire 1 t! S2_XAB7 $end $var wire 1 u! S2_XAB6 $end $var wire 1 v! S2_XAB5 $end $var wire 1 w! S2_XAB4 $end $var wire 1 x! S2_XAB3 $end $var wire 1 y! S2_XAB2 $end $var wire 1 z! S2_XAB1 $end $var wire 1 {! S2_YAB15 $end $var wire 1 |! S2_YAB14 $end $var wire 1 }! S2_YAB13 $end $var wire 1 ~! S2_YAB12 $end $var wire 1 !" S2_YAB11 $end $var wire 1 "" S2_YAB10 $end $var wire 1 #" S2_YAB9 $end $var wire 1 $" S2_YAB8 $end $var wire 1 %" S2_YAB7 $end $var wire 1 &" S2_YAB6 $end $var wire 1 '" S2_YAB5 $end $var wire 1 (" S2_YAB4 $end $var wire 1 )" S2_YAB3 $end $var wire 1 *" S2_YAB2 $end $var wire 1 +" S2_YAB1 $end $var wire 1 ," TC1_TLBREAD1 $end $var wire 1 -" TC1_TLBREAD0 $end $var wire 1 2" HECS_CLK $end $scope module CPU $end $scope module CEX $end $scope module shcdp_i0 $end $var wire 1 ." EMWBLP $end $var wire 1 /" EMWBHP $end $var wire 1 0" EMWLHP $end $var wire 1 1" EMWHHP $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 12" 1! x" x# x$ 1% 0& 0' x( x) x* x+ x, x- x. x/ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x: x; x< x= x> x? x@ xA xB xC xD xE xF xG xH xI xJ xK xL xM xN bxxx O xP xQ xR xS xT xU xV xW xX xY xZ x[ x\ x] x^ x_ x` xa xb xc xd xe xf xg xh xi xj xk xl xm xn 0o 0p 1q 0r 0s 0t 0u 0v xw xx xy xz x{ x| x} x~ x!! x"! x#! x$! x%! x&! x'! z(! z)! z*! z+! z,! z-! z.! z/! z0! z1! z2! z3! z4! z5! z6! z7! 08! x9! 0:! 1;! 0! 0?! 1@! 0A! zB! zC! zD! zE! zF! zG! zH! zI! xJ! xK! xL! xM! xN! xO! xP! xQ! xR! xS! xT! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! xn! xo! xp! xq! xr! xs! xt! xu! xv! xw! xx! xy! xz! x{! x|! x}! x~! x!" x"" x#" x$" x%" x&" x'" x(" x)" x*" x+" 0," 1-" x." x/" x0" x1" $end #100 1>! 19! #200 01" 00" 0/" 0." zL! zM! zN! zO! zP! zQ! zR! zS! zT! zU! zV! zW! zX! zY! zZ! z[! zk! zj! z\! z]! z^! z_! z`! za! zb! zc! zd! ze! zf! zg! zh! zi! #220 x& #600 0x #800 0y #900 07 05 1{ #1000 0M 06 09 #1100 0$! 0#! 0: #1200 08 0; #1300 0* 0) 0( #5000 0q #5300 0J! 0K! 0w x0 x/ x. x- x, x+ 1$ 1# 0" #5500 0L 03 04 #5900 0%! 1z #6000 0'! 0&! #10000 1q #15000 0q #15300 xn xm xl xk xj xi xh xg xf xe xd xc xb xa x` x_ x^ x] x\ x[ xZ xY xX xW xV xU xT xS xR xQ xP bxxx O #20000 1q #25000 0q #30000 1q #35000 0q #40000 1q #45000 0q #50000 1q #55000 0q #60000 1q #65000 0q #70000 1q #75000 0q #75300 0$ #80000 1q 0# #85000 0q #90000 1q #95000 0q #100000 1q #105000 0q #105300 0! #110000 1q #115000 0q #115300 xL! xM! xN! xO! xP! xQ! xR! xS! xT! xU! xV! xW! xX! xY! xZ! x[! xk! xj! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! #115600 0, 0+ 0- 0. 0/ 00 #116200 0N #116500 1( #116600 0( #120000 1q #125000 0q #130000 1q #135000 0q #135500 1~ 1"! 1} 01 1!! #140000 1q #145000 0q #145500 12 1| #150000 1q #155000 0q #160000 1q #165000 0q #165300 0M! 0O! 0P! 0Q! 0R! 0S! 0T! 0U! 0V! 0W! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0f! 0g! 0h! 0i! 0j! 0k! 1L! 1N! #165500 13 14 #165600 1+ 1, #170000 1q #170220 1& #175000 0q #175300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 0^ 1] 1\ 0[ 1Z 1Y 0X 0W 1V 1U 1T 1S 1R 0Q 1P b111 O #175500 03 04 #175600 0+ #175800 1'! #175900 1%! 0'! #176100 0%! #180000 1q #180520 x$! x#! #180720 0$! #180820 1#! #185000 0q #185300 1h! 0i! 0n 1m 1l 0k 1j 1i 1e 1c 1b 0a 1` 1^ 0] 0\ 1[ 0Z 0Y 0V 0U 0T 0S 0R 0P b000 O #185800 1'! #190000 1q #190720 1: 1; 18 x9 #190820 0: 0; 08 09 #190920 1; #191020 0; #195000 0q #195300 1d! 1e! 1g! 1i! 0j 0i 1f 1d 0b 1a 0` 0_ 0^ 1] 0[ 1Y 1W 1Q 1P #195500 14 #195600 10 1. 1/ #195700 1&! #195800 1%! 0'! #195900 0&! #196000 0%! #196100 1&! #196400 1( #196700 0( #200000 1q #200520 0#! #200820 17 15 #200920 07 05 #205000 0q #205300 0d! 0e! 0i! 0m 0l 0f 0e 0d 0c 0a 0] 1Z 1X 0W 1T 1S 0Q 0P #205500 13 #205600 00 1+ 0. 0/ #210000 1q #210520 1#! #215000 0q #215300 1i! 1l 1j 1i 1f 1b 1` 1_ 1^ 1] 0X 0T 0S 1R 1P b111 O #215500 03 04 #215600 0+ #215700 0&! #215800 1'! #215900 0'! #216000 1&! #216100 0&! #216200 1( #216300 0( #216500 1( #216600 1) #216700 1* 0( 0) #216800 0* #220000 1q #225000 0q #225300 1f! 0g! 0h! 0i! 1m 0l 0i 0f 0b 1a 0` 0_ 0^ 0] 0Z 0Y 1U 0R 1Q #226100 1'! #230000 1q #230720 1: 1; 18 #230820 0: 0; 08 #230920 1; #231020 0; #235000 0q #235300 1d! 1e! 1h! 1n 1i 1e 1c 1b 0a 1` 1_ 1] 1Y 1V 0U 0P b000 O #235500 14 #235600 10 1. 1/ #235700 1&! #235900 0'! #240000 1q #245000 0q #245300 1i! 0n 0m 0j 1h 1g 1f 1d 1a 1^ 1\ 1[ 0Y 0V 1T 1S b111 O #245800 1%! #245900 1'! #246000 0%! #246100 0&! #250000 1q #250520 0#! #255000 0q #255300 0d! 0e! 0h! 0i 0g 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 1Z 1Y 1X 0Q b000 O #255500 04 #255600 00 0. 0/ #260000 1q #260520 1#! #260820 17 15 #260920 07 05 #265000 0q #265300 1m 1i 0h 1c 1] 1\ 1[ 0Z 0X 1U 0T 1P #265600 0, #265700 0'! #265800 1%! #266000 1&! #266100 0%! #270000 1q #275000 0q #275300 1P! 1Q! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1d! 1e! 0i! 0n 1m 0l 0k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 0_ 0^ 1] 1\ 1[ 0Z 1Y 0X 0W 0V 1U 0T 1S 0R 0Q 1P b000 O #275500 14 #275600 10 1/ #275700 1'! #275900 0&! #280000 1q #280520 0#! #285000 0q #285300 1." 10" 11" 1h! 0P! 0Q! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0e! 0^ 0] 0\ 0[ 1Z 1Y 1X 0W 0V 0U 1T 1S 0R 0Q 0P b000 O 1f 1e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 1h 0g #285500 04 #285600 00 0/ 1, #290000 1q #290520 1#! #295000 0q #295300 0." 00" 01" 1P! 1Q! 1U! 1V! 1W! 1b! 1c! 1e! 0f! 0h! 0L! 0N! 1V 1Q 1P b111 O 1c 1b 1a 1i 1g 0Z 0Y 0X 0S 0h #295500 14 #295600 10 1/ 0, #295700 1&! #295800 0'! 1%! #295900 0%! 1'! #296000 0'! #296100 1( #296200 0( #296400 1( #296500 0( #300000 1q #305000 0q #305300 1." 10" 11" 0W! 0V! 0U! 0Q! 0P! 1N! 1L! 1g! 1f! 1d! 0c! 0b! 0V 0Q 0P b000 O 0c 0b 0a 0i 0g 0T 0e 0f #305600 1. 1, #305700 0&! #305800 1'! #310000 1q #310520 0#! #315000 0q #315300 0." 00" 01" 1h! 1i! 0d! 0e! 0g! 1Y 1T 1S b111 O #315500 04 #315600 00 0. 0/ #320000 1q #320520 1#! #320820 17 15 #320920 07 05 #321020 1: #321120 0: #325000 0q #325300 1n 1j 1i 1b 1` 1_ 1^ 1Z 0Y 1X 1V 1U 0T #325600 0, #325700 0'! 1&! #325900 0&! #326000 1%! #326100 0%! #326200 1&! #330000 1q #335000 0q #335300 1g! 0h! 0i! 1n 0m 0l 0k 1j 1i 0h 0g 0f 0e 0d 0c 1b 0a 1` 1_ 1^ 0] 0\ 0[ 1Z 0Y 1X 0W 1V 1U 0T 1S 0R 0Q 0P b111 O #335600 1, #335800 1'! #336000 0&! #340000 1q #345000 0q #345300 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 1^ 0] 0\ 0[ 1Z 1Y 0X 0W 1V 0U 0T 0S 1R 0Q 1P b111 O #345600 0, #345700 1&! #345800 1%! 0'! #345900 0&! #346000 0%! #346100 1&! #350000 1q #355000 0q #355300 1i! 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 1^ 0] 0\ 0[ 1Z 1Y 0X 0W 1V 0U 0T 0S 1R 0Q 1P b111 O #355600 1, #355700 0&! #355800 1'! #360000 1q #365000 0q #365300 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 1Q 1P b000 O #365600 0, #365700 0'! 1&! #365900 0&! #366000 1&! #366100 1%! #366200 0%! #370000 1q #370720 1: 1; 18 19 #370820 0: 0; 08 09 #370920 1; #371020 0; #375000 0q #375300 1d! 1e! 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 1Q 1P b000 O #375500 14 #375600 10 1. 1/ 1, #375800 1'! #375900 0&! #376000 1%! #376100 0%! #380000 1q #380520 0#! #385000 0q #385300 1h! 0d! 0e! 0i! 0n 0m 0l 0k 1j 1i 0h 0g 1f 1e 1d 1c 1b 1a 1` 1_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 1T 0S 0R 1Q 0P b111 O #385500 04 #385600 00 0. 0/ #390000 1q #390520 1#! #395000 0q #395300 1d! 1e! 1m 0i 0f 0e 0d 0c 0b 0` 0_ 0T 1R 1P b000 O #395500 14 #395600 10 1. 1/ #395800 1&! #395900 0'! #400000 1q #400520 0#! #405000 0q #405300 0d! 0e! 0m 0j 0a 0\ 1V 0R 0Q 0P #405500 04 #405600 00 0. 0/ 0, #410000 1q #410520 1#! #415000 0q #415300 1Q! 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 0h! 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 0T 0S 0R 0Q 0P b000 O #415500 14 #415600 10 1/ #415700 0&! #415900 1'! #420000 1q #420520 0#! #425000 0q #425300 1." 10" 11" 1h! 1i! 0Q! 0Y! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 0h 0g #425500 04 #425600 00 0/ 1, #430000 1q #430520 1#! #435000 0q #435300 0." 00" 01" 1\ 1R 1Q 1P 1a 1m 1j 0V #435600 0, #435700 1&! #435900 0'! #440000 1q #445000 0q #445300 1Q! 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 0h! 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 1Q 1P b000 O #445500 14 #445600 10 1/ #445800 1%! #445900 1'! #446000 0%! #446100 0&! #450000 1q #450520 0#! #455000 0q #455300 1." 10" 11" 1e! 0Q! 0Y! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0f! 0g! 0i! 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 0h 0g 1V #455500 04 #455600 00 0/ 1, #460000 1q #460520 1#! #465000 0q #465300 0." 00" 01" 1] 1\ 1[ 1Y 1R 1P b111 O 1a 1m 1j 0V #465600 0, #465700 0'! #465800 1%! #466000 1&! #466100 0%! #470000 1q #475000 0q #475300 1Q! 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1f! 1g! 1h! 0e! 0n 1m 0l 0k 1j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 0_ 0^ 1] 1\ 1[ 0Z 1Y 0X 0W 0V 0U 0T 0S 1R 0Q 1P b111 O #475500 14 #475600 10 1/ #475700 1'! #475900 0&! #480000 1q #480520 0#! #485000 0q #485300 1." 10" 11" 1e! 1i! 0Q! 0Y! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0f! 0g! 0h! 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 0h 0g 1V #485500 04 #485600 00 0/ 1, #490000 1q #490520 1#! #495000 0q #495300 0." 00" 01" 1U 1S 1Q 1P b111 O 1e 1c 1` 1m 1l 1k 1j 1i 0V #495600 0, #495700 1&! #495800 0'! 1%! #495900 0%! 1'! #496000 0'! #500000 1q #505000 0q #505300 1Q! 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1f! 1g! 1h! 0e! 0n 1m 1l 1k 1j 1i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 1U 0T 1S 0R 1Q 1P b111 O #505500 14 #505600 10 1/ #505700 0&! #505800 1'! #506100 1( #506200 0( #506400 1( #506500 0( #510000 1q #510520 0#! #515000 0q #515300 1." 10" 11" 1e! 0Q! 0Y! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0f! 0g! 0i! 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 0h 0g 1V #515500 04 #515600 00 0/ 1, #520000 1q #520520 1#! #525000 0q #525300 0." 00" 01" 1d! 1f! 1g! 1i! 1] 1Z 1Y 1U 1S 1f 1d 1a 1` 1_ 1n #525500 14 #525600 10 1. 1/ #525700 0'! 1&! #525900 0&! #526000 1%! #526100 0%! #526200 1&! #530000 1q #530520 0#! #535000 0q #535300 0d! 0f! 0g! 0i! 0n 1j 1g 1e 1c 1b 0] 1\ 0Z 0Y 0V 0U 1T 0S 1Q b111 O #535500 04 #535600 00 0. 0/ 0, #540000 1q #540520 1#! #545000 0q #545300 1Q! 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1c! 1d! 1g! 0e! 0h! 0n 0m 0l 0k 1j 0i 0h 1g 1f 1e 1d 1c 1b 1a 1` 1_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 1T 0S 0R 1Q 0P b111 O #545500 14 #545600 10 1/ #545800 1'! #546000 0&! #550000 1q #550520 0#! #555000 0q #555300 1." 10" 11" 1e! 1h! 1i! 0Q! 0Y! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0c! 0d! 0g! 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0m 0l 0k 0j 0i 0h 0g 1V #555500 04 #555600 00 0/ 1, #560000 1q #560520 1#! #565000 0q #565300 0." 00" 01" 1Y 1W 1U 1S 1R 1Q 1f 1e 1c 1_ 1h #565600 0, #565700 1&! #565800 1%! 0'! #565900 0&! #566000 0%! #566100 1&! #570000 1q #575000 0q #575300 1g! 0h! 0i! 0n 0m 0l 0k 0j 0i 1h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #575600 1, #575700 0&! #575800 1'! #576100 1( #576200 0( #580000 1q #585000 0q #585300 0n 1m 0l 1k 0j 1i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #585600 0, #585700 0'! 1&! #585900 0&! #586000 1&! #586100 1%! #586200 0%! #590000 1q #595000 0q #595300 1i! 0n 1m 0l 1k 0j 1i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #595600 1, #595800 1'! #595900 0&! #596000 1%! #596100 0%! #600000 1q #605000 0q #605300 0n 1m 0l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 1[ 0Z 1Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #605600 0, #605800 1&! #605900 0'! #610000 1q #615000 0q #615300 1h! 0i! 0n 1m 0l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 1[ 0Z 1Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #615600 1, #615700 0&! #615900 1'! #620000 1q #625000 0q #625300 0n 1m 0l 1k 1j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #625600 0, #625700 1&! #625900 0'! #626400 1( #626500 0( #630000 1q #635000 0q #635300 1i! 0n 1m 0l 1k 1j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #635600 1, #635800 1%! #635900 1'! #636000 0%! #636100 0&! #640000 1q #645000 0q #645300 0n 1m 1l 1k 1j 0i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #645600 0, #645700 0'! #645800 1%! #646000 1&! #646100 0%! #650000 1q #655000 0q #655300 1f! 0g! 0h! 0i! 0n 1m 1l 1k 1j 0i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #655600 1, #655700 1'! #655900 0&! #660000 1q #665000 0q #665300 1n 1m 0l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 0[ 1Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #665600 0, #665700 1&! #665800 0'! 1%! #665900 0%! 1'! #666000 0'! #670000 1q #675000 0q #675300 1i! 1n 1m 0l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 0[ 1Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #675600 1, #675700 0&! #675800 1'! #680000 1q #685000 0q #685300 0n 0m 1l 0k 1j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #685600 0, #685700 0'! 1&! #685900 0&! #686000 1%! #686100 0%! #686200 1&! #690000 1q #695000 0q #695300 1h! 0i! 0n 0m 1l 0k 1j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #695600 1, #695800 1'! #696000 0&! #696100 1( #696200 0( #700000 1q #705000 0q #705300 0n 1m 1l 1k 0j 0i 1h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #705600 0, #705700 1&! #705800 1%! 0'! #705900 0&! #706000 0%! #706100 1&! #710000 1q #715000 0q #715300 1i! 0n 1m 1l 1k 0j 0i 1h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #715600 1, #715700 0&! #715800 1'! #720000 1q #725000 0q #725300 0n 0m 1l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 0[ 0Z 0Y 1X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #725600 0, #725700 0'! 1&! #725900 0&! #726000 1&! #726100 1%! #726200 0%! #730000 1q #735000 0q #735300 1g! 0h! 0i! 0n 0m 1l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 0[ 0Z 0Y 1X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #735600 1, #735800 1'! #735900 0&! #736000 1%! #736100 0%! #740000 1q #745000 0q #745300 0n 1m 1l 1k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #745600 0, #745800 1&! #745900 0'! #750000 1q #755000 0q #755300 1i! 0n 1m 1l 1k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #755600 1, #755700 0&! #755900 1'! #760000 1q #765000 0q #765300 0n 1m 0l 1k 1j 0i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #765600 0, #765700 1&! #765900 0'! #770000 1q #775000 0q #775300 1h! 0i! 0n 1m 0l 1k 1j 0i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #775600 1, #775800 1%! #775900 1'! #776000 0%! #776100 0&! #780000 1q #785000 0q #785300 1n 0m 1l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 1[ 1Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #785600 0, #785700 0'! #785800 1%! #786000 1&! #786100 0%! #790000 1q #795000 0q #795300 1i! 1n 0m 1l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 1[ 1Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #795600 1, #795700 1'! #795900 0&! #800000 1q #805000 0q #805300 0n 0m 0l 1k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #805600 0, #805700 1&! #805800 0'! 1%! #805900 0%! 1'! #806000 0'! #806200 1( #806400 0( #810000 1q #810720 16 19 #810820 09 #810920 17 15 #811220 1; #815000 0q #815300 1d! 0e! 0f! 0g! 0h! 0i! 0n 0m 0l 1k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #815600 1- 1. #815700 0&! #815800 1'! #820000 1q #820520 0#! #820820 06 07 05 #821120 0; #825000 0q #825300 1." 10" 11" 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 0n 1m 0l 1k 0j 0i 0h 0g 0V #825600 0- 0. 1, #830000 1q #830520 1#! #830820 17 15 #831120 1; #835000 0q #835300 0." 00" 01" 1\ 1[ 1Z 1X 1U 1S 1R 1Q 1e 1c 1` #835600 1. 0, #835700 0'! 1&! #835900 0&! #836000 1%! #836100 0%! #836200 1&! #840000 1q #840720 0; #840920 07 05 #845000 0q #845300 1i! 0n 1m 0l 1k 0j 0i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 0] 1\ 1[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O xf xe xd xc xb xa x` x_ xn xm xl xk xj xi xh xg x^ x] x\ x[ xZ xY xX xW xV xU xT xS xR xQ xP bxxx O #845400 0f 0e 0d 0c 0b 0a 0` 0_ 0n 1m 0l 1k 0j 0i 0h 0g 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #845600 0. 1, #845800 1'! #846000 0&! #850000 1q #855000 0q #855300 xl xk xf xd xa x` x_ x] x[ xV xU xS 1S 1U 1V 1[ 1] 1l 1_ 1` 1a 1d 1f 0k #855600 0, #855700 1&! #855800 1%! 0'! #855900 0&! #856000 0%! #856100 1&! #860000 1q #865000 0q #865300 1h! 0i! 0n 1m 1l 0k 0j 0i 0h 0g 1f 0e 1d 0c 0b 1a 1` 1_ 0^ 1] 0\ 1[ 0Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b000 O #865600 1, #865700 0&! #865800 1'! #870000 1q #875000 0q #875300 0n 1m 0l 0k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #875600 0, #875700 0'! 1&! #875900 0&! #876000 1&! #876100 1%! #876200 1( 0%! #876400 0( #880000 1q #880720 16 19 #880820 09 #880920 17 15 #885000 0q #885300 1i! 0n 1m 0l 0k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 1W 1V 1U 0T 1S 1R 1Q 0P b000 O #885600 1- 1. #885800 1'! #885900 0&! #886000 1%! #886100 0%! #890000 1q #890520 0#! #890820 06 07 05 #895000 0q #895300 1." 10" 11" 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O 0f 0e 0d 0c 0b 0a 0` 0_ 1n 1l 0j 0i 0h 0g 1m 1k #895600 0- 0. 1, #900000 1q #900520 1#! #900820 17 15 #905000 0q #905300 0." 00" 01" 1^ 1] 1\ 1Q b111 O 0m 0l #905600 1. 0, #905800 1&! #905900 0'! #910000 1q #910920 07 05 #915000 0q #915300 1g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 1] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O 1m 1k 0f 0e 0d 0c 0b 0a 0` 0_ 0n 0l 0j 0i 0h 0g 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #915400 1n 1l #915600 0. 1, #915700 0&! #915900 1'! #920000 1q #925000 0q #925300 xn xm xj xd xc xb x` x_ x^ x] x[ xZ xU xS xR xP bxxx O b111 O 1P 1R 1S 1U 1Z 1[ 1] 1^ 1j 1_ 1` 1b 1c 1d 0m 0n #925600 0, #925700 1&! #925900 0'! #930000 1q #935000 0q #935300 0n 0m 1l 1k 1j 0i 0h 0g 0f 0e 1d 1c 1b 0a 1` 1_ 1^ 1] 0\ 1[ 1Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #935800 1%! #935900 1'! #936000 0%! #936100 0&! #940000 1q #940520 0#! #945000 0q #945300 1h! 1i! 1j! #945500 13 14 #945600 1+ 1, #950000 1q #955000 0q #955300 1f! 0g! 0h! 0i! 0j! 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 1` 1_ 1^ 0] 0\ 1[ 1Z 0Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b111 O #955500 03 04 #955600 0+ #955700 0'! #955900 1'! #956000 1&! #960000 1q #960520 1#! #965000 0q #965300 1i! 1n 1m 1e 0_ 1] 0[ 0Z 0U 0S 1Q 1P b000 O #965700 0&! 0'! 1%! #965900 1'! #966200 0%! 1( #966300 0( #966500 1( #966600 1) #966700 1* 0( 0) #966800 0* #970000 1q #975000 0q #975300 0e 1d 1U #975600 0, #975700 0'! 1&! #975900 0&! #976000 1%! #976100 0%! #976200 1( 1&! #976300 0( #980000 1q #985000 0q #985300 1h! 0i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 0e 1d 0c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 0S 0R 1Q 1P b000 O #985600 1, #985800 1'! #986000 0&! #990000 1q #995000 0q #995300 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 1d 0c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 1T 0S 0R 1Q 1P b000 O #995600 0, #995700 1&! #995800 1%! 0'! #995900 0&! #996000 0%! #996100 1&! #1000000 1q #1005000 0q #1005300 1i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 1d 0c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 1T 0S 0R 1Q 1P b000 O #1005600 1, #1005700 0&! #1005800 1'! #1010000 1q #1015000 0q #1015300 1n 1m 0l 0k 0j 0i 0h 0g 0f 0e 0d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 0S 0R 1Q 1P b000 O #1015600 0, #1015700 0'! 1&! #1015900 0&! #1016000 1&! #1016100 1%! #1016200 0%! #1020000 1q #1025000 0q #1025300 1g! 0h! 0i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 0e 0d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 0S 0R 1Q 1P b000 O #1025600 1, #1025800 1'! #1025900 0&! #1026000 1%! #1026100 0%! #1030000 1q #1035000 0q #1035300 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 0d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 0T 1S 0R 1Q 1P b000 O #1035600 0, #1035800 1&! #1035900 0'! #1040000 1q #1045000 0q #1045300 1i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 0d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 0T 1S 0R 1Q 1P b000 O #1045600 1, #1045700 0&! #1045900 1'! #1050000 1q #1055000 0q #1055300 1n 1m 0l 0k 0j 0i 0h 0g 0f 0e 1d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 1S 0R 1Q 1P b000 O #1055600 0, #1055700 1&! #1055900 0'! #1060000 1q #1065000 0q #1065300 1h! 0i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 0e 1d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 1S 0R 1Q 1P b000 O #1065600 1, #1065800 1%! #1065900 1'! #1066000 0%! #1066100 0&! #1070000 1q #1075000 0q #1075300 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 1d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 1T 1S 0R 1Q 1P b000 O #1075600 0, #1075700 0'! #1075800 1%! #1076000 1&! #1076100 0%! #1080000 1q #1085000 0q #1085300 1i! 1n 1m 0l 0k 0j 0i 0h 0g 0f 1e 1d 1c 0b 1a 1` 0_ 1^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 0U 1T 1S 0R 1Q 1P b000 O #1085600 1, #1085700 1'! #1085900 0&! #1090000 1q #1095000 0q #1095300 0n 1m 1l 1k 1j 0i 0h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 0X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1095600 0, #1095700 1&! #1095800 0'! 1%! #1095900 0%! 1'! #1096000 0'! #1100000 1q #1105000 0q #1105300 1e! 0f! 0g! 0h! 0i! 0n 1m 1l 1k 1j 0i 0h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 0X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1105600 1, #1105700 0&! #1105800 1'! #1110000 1q #1115000 0q #1115300 0n 1m 1l 1k 1j 1i 0h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 1Y 0X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1115600 0, #1115700 0'! 1&! #1115900 0&! #1116000 1%! #1116100 0%! #1116200 1&! #1120000 1q #1125000 0q #1125300 1i! 0n 1m 1l 1k 1j 1i 0h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 1Y 0X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1125600 1, #1125800 1'! #1126000 0&! #1130000 1q #1135000 0q #1135300 0n 1m 1l 1k 1j 0i 1h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 1X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1135600 0, #1135700 1&! #1135800 1%! 0'! #1135900 0&! #1136000 0%! #1136100 1&! #1140000 1q #1145000 0q #1145300 1h! 0i! 0n 1m 1l 1k 1j 0i 1h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 1X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1145600 1, #1145700 0&! #1145800 1'! #1150000 1q #1155000 0q #1155300 0n 1m 1l 1k 1j 1i 1h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 1Y 1X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1155600 0, #1155700 0'! 1&! #1155900 0&! #1156000 1&! #1156100 1%! #1156200 0%! #1160000 1q #1165000 0q #1165300 1i! 0n 1m 1l 1k 1j 1i 1h 1g 0f 0e 0d 0c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 1Y 1X 1W 0V 0U 0T 0S 0R 0Q 1P b000 O #1165600 1, #1165800 1'! #1165900 0&! #1166000 1%! #1166100 0%! #1170000 1q #1175000 0q #1175300 1n 1m 0l 1k 0j 1i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #1175600 0, #1175800 1&! #1175900 0'! #1180000 1q #1185000 0q #1185300 1g! 0h! 0i! 1n 1m 0l 1k 0j 1i 0h 0g 0f 1e 0d 1c 0b 0a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #1185600 1, #1185700 0&! #1185900 1'! #1190000 1q #1195000 0q #1195300 0n 1m 1l 0k 1j 0i 1h 0g 1f 1e 1d 1c 0b 1a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1195600 0, #1195700 1&! #1195900 0'! #1200000 1q #1205000 0q #1205300 1i! 0n 1m 1l 0k 1j 0i 1h 0g 1f 1e 1d 1c 0b 1a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1205600 1, #1205800 1%! #1205900 1'! #1206000 0%! #1206100 1( 0&! #1206300 1) #1206400 0( 0) 1* #1206500 0* #1210000 1q #1210720 1: 1; 18 19 #1210820 0: 0; 08 09 #1210920 1; #1211020 0; #1215000 0q #1215300 1c! 1h! 0d! 0e! 0g! 0i! 1n 0m 1l 1k 0j 0i 0h 0g 0f 1e 0d 1c 1b 0a 1` 1_ 0^ 1] 1\ 0[ 1Z 1Y 0X 1W 1V 1U 1T 1S 0R 1Q 0P b000 O #1215500 14 #1215600 10 1. 1/ #1215700 0'! #1215800 1%! #1216000 1&! #1216100 0%! #1216600 1( #1216700 0( #1220000 1q #1220520 0#! #1225000 0q #1225300 1d! 1e! 1g! 1i! 0c! 0h! 0n 0l 0k 0e 0c 0b 0` 0_ 0] 0\ 0Z 0Y 1X 0W 0V 0U 0Q #1225500 04 #1225600 00 0. 0/ 0, #1230000 1q #1230820 17 15 #1230920 07 05 #1231020 1: #1231120 0: #1235000 0q #1235300 0L! 0N! 1P! 1Q! 1U! 0d! 0e! 0g! 0i! 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 1X 0W 0V 0U 1T 1S 0R 0Q 0P b000 O #1235500 13 14 #1235600 1+ 1, #1236400 1( #1236500 0( #1240000 1q #1240520 1#! #1245000 0q #1245300 1i! 0n 1m 0l 0k 0j 0i 0h 0g 1f 1e 0d 1c 0b 0a 0` 0_ 0^ 1] 0\ 1[ 1Z 0Y 1X 0W 1V 1U 1T 1S 1R 0Q 1P b111 O #1245500 03 04 #1245600 0+ #1245700 1'! 0&! 1%! #1245800 0%! #1245900 1%! #1246000 0'! #1246100 0%! #1246200 1( #1246300 0( #1246500 1( #1246600 1) #1246700 1* 0( 0) #1246800 0* #1250000 1q #1255000 0q #1255300 1h! 0i! 1l 1k 0e 1d 1` 0U #1255800 1'! #1260000 1q #1260720 1: 1; 18 #1260820 0: 0; 08 #1260920 1; #1261020 0; #1265000 0q #1265300 1c! 1e! 1f! 1i! 0l 1j 1h 1b 1_ 1^ 0[ 1Y 0X 1W 0V 1U 0R 1Q b000 O #1265500 14 #1265600 10 1. 1/ #1265700 1&! #1265800 1%! 0'! #1265900 0&! #1266000 0%! #1266100 1&! #1270000 1q #1270820 17 15 #1270920 07 05 #1275000 0q #1275300 0c! 0e! 0f! 0m 0k 0j 0h 0f 0d 0c 0b 0` 0_ 0^ 0] 1X 0W 0U 0Q 0P #1275500 04 #1275600 00 0. 0/ #1275700 0&! #1275800 1'! #1276100 1( #1276300 0( #1280000 1q #1280720 1: 1; 18 #1280820 0: 0; 08 #1280920 1; #1281020 0; #1285000 0q #1285300 1c! 1e! 1f! 1g! 0h! 0i! 1n 1k 1i 1h 1f 1e 1d 1` 1_ 1^ 1[ 0X 1W 1V 1Q #1285500 14 #1285600 10 1. 1/ #1285700 0'! 1&! #1285900 0&! #1286000 1&! #1286100 1%! #1286200 0%! #1290000 1q #1290520 0#! #1295000 0q #1295300 1h! 1i! 0c! 0e! 0f! 0g! 1m 0k 1j 1g 0d 0` 0_ 0^ 0[ 0Z 0Y 0W 0V 0T 0S 1R 1P b111 O #1295500 04 #1295600 00 0. 0/ 0, #1300000 1q #1300820 17 15 #1300920 07 05 #1305000 0q #1305300 1n 1m 0l 0k 1j 1i 1h 1g 1f 1e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 1Q 1P b111 O #1305700 1N #1310000 1q #1315000 0q #1320000 1q #1325000 0q #1330000 1q #1330520 1#! #1335000 0q #1335300 1g! 0h! 0i! #1335600 1, #1335800 1'! #1335900 0&! #1336000 1%! #1336100 0%! #1340000 1q #1345000 0q #1345300 0n 1m 0l 1k 1j 0i 1h 0g 0f 0e 1d 0c 1b 0a 1` 1_ 1^ 0] 0\ 1[ 1Z 0Y 1X 0W 1V 1U 0T 0S 1R 0Q 1P b111 O #1345600 0, #1345800 1&! #1345900 0'! #1346100 1( #1346200 0( #1346300 1( #1346600 0( #1350000 1q #1350720 1: 1; 18 #1350820 0: 0; 08 #1350920 1; #1351020 0; #1355000 0q #1355300 1c! 1e! 1f! 1i! 0n 1m 0l 1k 1j 0i 1h 0g 0f 0e 1d 0c 1b 0a 1` 1_ 1^ 0] 0\ 1[ 1Z 0Y 1X 0W 1V 1U 0T 0S 1R 0Q 1P b111 O #1355500 14 #1355600 10 1. 1/ 1, #1355700 0&! #1355900 1'! #1360000 1q #1360520 0#! #1365000 0q #1365300 0c! 0e! 0f! 1n 1m 1l 1k 1j 1i 1h 1g 1f 1e 1d 1c 1b 1a 1` 1_ 1^ 1] 1\ 1[ 1Z 1Y 1X 1W 1V 1U 1T 1S 1R 0Q 1P b111 O #1365500 04 #1365600 00 0. 0/ #1370000 1q #1370520 1#! #1370820 17 15 #1370920 07 05 #1371020 1: #1371120 18 0: 1; #1371220 08 0; #1375000 0q #1375300 0l 0k 0j 0i 0g 0e 0c 0b 0_ 0^ 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P #1375600 0, #1375700 1&! #1375900 0'! #1376100 1( #1376400 0( #1380000 1q #1385000 0q #1385300 1h! 0i! 1n 1m 0l 0k 0j 0i 1h 0g 1f 0e 1d 0c 0b 1a 1` 0_ 0^ 1] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O #1385600 1, #1385800 1%! #1385900 1'! #1386000 0%! #1386100 0&! #1386300 1( #1386400 0( #1390000 1q #1390720 1: 1; 18 19 #1390820 0: 0; 08 09 #1390920 1; #1391020 0; #1395000 0q #1395300 1c! 1e! 1f! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1395500 14 #1395600 10 1. 1/ #1395700 0'! #1395800 1%! #1396000 1&! #1396100 0%! #1400000 1q #1405000 0q #1405300 1i! 1m 1l 0k 1i 1h 1f 1d 1` 1] 0[ 1Y 1V #1405700 1'! #1405900 0&! #1406400 1( #1406700 0( #1410000 1q #1410520 0#! #1410820 17 15 #1410920 07 05 #1415000 0q #1415300 0c! 0e! 0f! 0m 0l 1j 0i 0h 0d 1b 0` 0] 1Z 0Y 1R #1415500 13 #1415600 00 1+ 0. 0/ #1420000 1q #1420520 1#! #1425000 0q #1425300 1f! 0g! 0h! 0i! 0n 1m 1l 1k 0j 1g 1e 0b 1` 0^ 1\ 1[ 0Z 1X 1U 1Q #1425500 03 04 #1425600 0+ #1425800 1%! #1426000 0'! #1426100 0%! #1430000 1q #1435000 0q #1435300 1i! 1n 0m 0l 0g 0f 0e 0` 1^ 0\ 0X 0V 0U 0R 0Q #1435800 1'! #1440000 1q #1445000 0q #1445600 0, #1445700 1&! #1445800 1%! 0'! #1445900 0&! #1446000 0%! #1446100 1&! #1450000 1q #1455000 0q #1455300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1455600 1, #1455700 0&! #1455800 1'! #1456100 1( #1456300 0( #1460000 1q #1465000 0q #1465300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1465600 0, #1465700 0'! 1&! #1465900 0&! #1466000 1&! #1466100 1%! #1466200 0%! #1470000 1q #1475000 0q #1475300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1475600 1, #1475800 1'! #1475900 0&! #1476000 1%! #1476100 0%! #1480000 1q #1485000 0q #1485300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1485600 0, #1485800 1&! #1485900 0'! #1490000 1q #1495000 0q #1495300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1495600 1, #1495700 0&! #1495900 1'! #1500000 1q #1505000 0q #1505300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1505600 0, #1505700 1&! #1505900 0'! #1510000 1q #1515000 0q #1515300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1515600 1, #1515800 1%! #1515900 1'! #1516000 0%! #1516100 0&! #1520000 1q #1525000 0q #1525300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1525600 0, #1525700 0'! #1525800 1%! #1526000 1&! #1526100 0%! #1526200 1( #1526700 0( #1530000 1q #1530520 0#! #1535000 0q #1535300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1535500 13 14 #1535600 1+ 1, #1540000 1q #1540520 1#! #1545000 0q #1545300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1545500 03 04 #1545600 0+ #1545700 1'! 0&! 1%! #1545800 0%! #1545900 1%! #1546000 0'! #1546100 0%! #1546200 1( #1546300 0( #1546500 1( #1546600 1) #1546700 1* 0( 0) #1546800 0* #1550000 1q #1555000 0q #1555300 1i! #1555800 1'! #1560000 1q #1565000 0q #1565300 0n 1m 1l 1j 1g 1f 1e 1` 0^ 0[ 1Z 1X 1V 1U 1R 1P b111 O #1565600 0, #1565700 1&! #1565800 1%! 0'! #1565900 0&! #1566000 0%! #1566100 1&! #1570000 1q #1575000 0q #1575300 1e! 0f! 0g! 0h! 0i! 0n 1m 1l 1k 1j 0i 0h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 0^ 0] 0\ 0[ 1Z 0Y 1X 0W 1V 1U 0T 0S 1R 0Q 1P b111 O #1575600 1, #1575700 0&! #1575800 1'! #1580000 1q #1585000 0q #1585300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1585600 0, #1585700 0'! 1&! #1585900 0&! #1586000 1&! #1586100 1%! #1586200 0%! #1590000 1q #1595000 0q #1595300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1595600 1, #1595800 1'! #1595900 0&! #1596000 1%! #1596100 0%! #1600000 1q #1600720 1: 1; 18 #1600820 0: 0; 08 #1600920 1; #1601020 0; #1605000 0q #1605300 1c! 1d! 0e! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1605500 14 #1605600 10 1. 1/ #1605800 1&! #1605900 0'! #1610000 1q #1610520 0#! #1615000 0q #1615300 1e! 1i! 0c! 0d! 1l 1i 1g 1e 1d 1c 1b 1` 1_ 1\ 1Y 1W 1U 1T 1S 1R 1P b111 O #1615500 04 #1615600 00 0. 0/ 0, #1620000 1q #1620520 1#! #1620820 17 15 #1620920 07 05 #1621120 18 1; #1621220 08 0; #1625000 0q #1625300 1h! 0i! 1n 0m 1l 1k 0j 1i 0h 1g 0f 1e 1d 1c 1b 0a 1` 1_ 1^ 0] 1\ 1[ 0Z 1Y 0X 1W 0V 1U 1T 1S 1R 0Q 1P b111 O #1625600 1, #1625700 0&! #1625900 1'! #1626100 1( #1626300 0( #1630000 1q #1635000 0q #1635300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1635600 0, #1635700 1&! #1635900 0'! #1640000 1q #1645000 0q #1645300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1645600 1, #1645800 1%! #1645900 1'! #1646000 0%! #1646100 0&! #1650000 1q #1655000 0q #1655300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1655600 0, #1655700 0'! #1655800 1%! #1656000 1&! #1656100 0%! #1660000 1q #1665000 0q #1665300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1665600 1, #1665700 1'! #1665900 0&! #1670000 1q #1675000 0q #1675300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1675600 0, #1675700 1&! #1675800 0'! 1%! #1675900 0%! 1'! #1676000 0'! #1680000 1q #1685000 0q #1685300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1685600 1, #1685700 0&! #1685800 1'! #1690000 1q #1695000 0q #1695300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1695600 0, #1695700 0'! 1&! #1695900 0&! #1696000 1%! #1696100 0%! #1696200 1( 1&! #1696700 0( #1700000 1q #1700520 0#! #1705000 0q #1705300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1705500 13 14 #1705600 1+ 1, #1710000 1q #1710520 1#! #1715000 0q #1715300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1715500 03 04 #1715600 0+ #1715700 0&! #1716200 1( #1716300 0( #1716500 1( #1716600 1) #1716700 1* 0( 0) #1716800 0* #1720000 1q #1725000 0q #1725300 1i! #1725800 1&! #1725900 0&! 1'! #1726000 1%! #1726100 0%! #1730000 1q #1735000 0q #1735300 0n 1m 1l 1i 1g 1f 1e 1` 0^ 0[ 1V 1U 1Q 1P #1735600 0, #1735800 1&! #1735900 0'! #1740000 1q #1745000 0q #1745300 1f! 0g! 0h! 0i! 0n 1m 1l 1k 0j 1i 0h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 0S 0R 1Q 1P b000 O #1745600 1, #1745700 0&! #1745900 1'! #1750000 1q #1755000 0q #1755300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1755600 0, #1755700 1&! #1755900 0'! #1760000 1q #1765000 0q #1765300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1765600 1, #1765800 1%! #1765900 1'! #1766000 0%! #1766100 0&! #1770000 1q #1775000 0q #1775300 1c! 1d! 1g! 0e! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1775500 14 #1775600 10 1. 0, #1775700 0'! #1775800 1%! #1776000 1&! #1776100 0%! #1780000 1q #1780520 0#! #1785000 0q #1785300 1e! 0c! 0d! 0g! 1m 0k 1i 1f 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1785500 04 #1785600 00 0. #1790000 1q #1790520 1#! #1790820 17 15 #1790920 07 05 #1791020 1: #1791120 18 0: #1791220 08 #1795000 0q #1795300 1h! 0i! 1n 1m 0l 0k 0j 1i 0h 0g 1f 0e 0d 0c 0b 0a 0` 0_ #1795600 1, #1795700 1'! #1795900 0&! #1796300 1( #1796500 0( #1800000 1q #1805000 0q #1805300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1805600 0, #1805700 1&! #1805800 0'! 1%! #1805900 0%! 1'! #1806000 0'! #1810000 1q #1815000 0q #1815300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1815600 1, #1815700 0&! #1815800 1'! #1820000 1q #1825000 0q #1825300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1825600 0, #1825700 0'! 1&! #1825900 0&! #1826000 1%! #1826100 0%! #1826200 1&! #1830000 1q #1835000 0q #1835300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1835600 1, #1835800 1'! #1836000 0&! #1840000 1q #1845000 0q #1845300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1845600 0, #1845700 1&! #1845800 1%! 0'! #1845900 0&! #1846000 0%! #1846100 1&! #1850000 1q #1855000 0q #1855300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1855600 1, #1855700 0&! #1855800 1'! #1860000 1q #1865000 0q #1865300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1865600 0, #1865700 0'! 1&! #1865900 0&! #1866000 1&! #1866100 1%! #1866200 1( 0%! #1866700 0( #1870000 1q #1870520 0#! #1875000 0q #1875300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1875500 13 14 #1875600 1+ 1, #1880000 1q #1880520 1#! #1885000 0q #1885300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1885500 03 04 #1885600 0+ #1885700 0&! #1886200 1( #1886300 0( #1886500 1( #1886600 1) #1886700 1* 0( 0) #1886800 0* #1890000 1q #1895000 0q #1895300 1i! #1895700 1&! #1895800 1%! 0&! #1896000 0%! 1'! 1&! #1896100 0&! #1900000 1q #1905000 0q #1905300 0n 1m 1l 1j 1i 1g 1f 1e 1` 0[ 1V 1U 1Q 1P #1905600 0, #1905700 0'! #1905800 1%! #1906000 1&! #1906100 0%! #1910000 1q #1915000 0q #1915300 1d! 0e! 0f! 0g! 0h! 0i! 0n 1m 1l 1k 1j 1i 0h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 1^ 0] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 0S 0R 1Q 1P b000 O #1915600 1, #1915700 1'! #1915900 0&! #1920000 1q #1925000 0q #1925300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1925600 0, #1925700 1&! #1925800 0'! 1%! #1925900 0%! 1'! #1926000 0'! #1930000 1q #1935000 0q #1935300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1935600 1, #1935700 0&! #1935800 1'! #1940000 1q #1945000 0q #1945300 1c! 1f! 1g! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1945500 14 #1945600 1. 1/ 0, #1945700 0'! 1&! #1945900 0&! #1946000 1%! #1946100 0%! #1946200 1&! #1950000 1q #1950520 0#! #1955000 0q #1955300 0c! 0f! 0g! 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O 1m 0k 1i 1f #1955500 04 #1955600 0. 0/ #1960000 1q #1960520 1#! #1960820 17 15 #1960920 07 05 #1961020 1: #1961120 18 0: 1; #1961220 08 0; #1965000 0q #1965300 1h! 0i! 1n 1m 0l 0k 0j 1i 0h 0g 1f 0e 0d 0c 0b 0a 0` 0_ #1965600 1, #1965800 1'! #1966000 0&! #1966100 1( #1966200 0( #1966300 1( #1966500 0( #1970000 1q #1975000 0q #1975300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1975600 0, #1975700 1&! #1975800 1%! 0'! #1975900 0&! #1976000 0%! #1976100 1&! #1980000 1q #1985000 0q #1985300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1985600 1, #1985700 0&! #1985800 1'! #1990000 1q #1995000 0q #1995300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #1995600 0, #1995700 0'! 1&! #1995900 0&! #1996000 1&! #1996100 1%! #1996200 0%! #2000000 1q #2005000 0q #2005300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2005600 1, #2005800 1'! #2005900 0&! #2006000 1%! #2006100 0%! #2010000 1q #2015000 0q #2015300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 1[ 1Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2015600 0, #2015800 1&! #2015900 0'! #2020000 1q #2025000 0q #2025300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 1[ 1Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2025600 1, #2025700 0&! #2025900 1'! #2030000 1q #2035000 0q #2035300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2035600 0, #2035700 1&! #2035900 0'! #2036200 1( #2036700 0( #2040000 1q #2040520 0#! #2045000 0q #2045300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2045500 13 14 #2045600 1+ 1, #2050000 1q #2050520 1#! #2055000 0q #2055300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2055500 03 04 #2055600 0+ #2055800 1%! #2055900 0%! #2056000 0&! #2056300 1( #2056400 0( #2060000 1q #2065000 0q #2065300 1i! #2065800 1%! 1'! #2066200 0%! #2070000 1q #2075000 0q #2075300 0n 1m 1l 1h 1g 1f 1e 1` 1Y 1V 1U #2075600 0, #2075700 0'! 1&! #2075900 0&! #2076000 1%! #2076100 0%! #2076200 1&! #2080000 1q #2085000 0q #2085300 1f! 0g! 0h! 0i! 0n 1m 1l 1k 0j 0i 1h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 1^ 0] 0\ 1[ 0Z 1Y 0X 0W 1V 1U 0T 0S 0R 0Q 0P b000 O #2085600 1, #2085800 1'! #2086000 0&! #2090000 1q #2095000 0q #2095300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2095600 0, #2095700 1&! #2095800 1%! 0'! #2095900 0&! #2096000 0%! #2096100 1&! #2100000 1q #2105000 0q #2105300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2105600 1, #2105700 0&! #2105800 1'! #2110000 1q #2115000 0q #2115300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2115600 0, #2115700 0'! 1&! #2115900 0&! #2116000 1&! #2116100 1%! #2116200 0%! #2120000 1q #2125000 0q #2125300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2125600 1, #2125800 1'! #2125900 0&! #2126000 1%! #2126100 1( 0%! #2126500 0( #2130000 1q #2135000 0q #2135300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2135600 0, #2135800 1&! #2135900 0'! #2140000 1q #2145000 0q #2145300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2145600 1, #2145700 0&! #2145900 1'! #2150000 1q #2155000 0q #2155300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2155600 0, #2155700 1&! #2155900 0'! #2160000 1q #2165000 0q #2165300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2165600 1, #2165800 1%! #2165900 1'! #2166000 0%! #2166100 0&! #2170000 1q #2175000 0q #2175300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2175600 0, #2175700 0'! #2175800 1%! #2176000 1&! #2176100 0%! #2180000 1q #2185000 0q #2185300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2185600 1, #2185700 1'! #2185900 0&! #2190000 1q #2195000 0q #2195300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2195600 0, #2195700 1&! #2195800 0'! 1%! #2195900 0%! 1'! #2196000 0'! #2196200 1( #2196700 0( #2200000 1q #2200520 0#! #2205000 0q #2205300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2205500 13 14 #2205600 1+ 1, #2210000 1q #2210520 1#! #2215000 0q #2215300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2215500 03 04 #2215600 0+ #2215700 0&! #2215900 1%! #2216000 0%! 1&! #2216100 0&! #2216200 1( #2216300 0( #2216500 1( #2216600 1) #2216700 1* 0( 0) #2216800 0* #2220000 1q #2225000 0q #2225300 1i! #2225800 1%! 1'! #2226200 0%! #2230000 1q #2235000 0q #2235300 0^ 1] 0[ 1V 1U #2235600 0, #2235700 0'! 1&! #2235900 0&! #2236000 1&! #2236100 1%! #2236200 0%! #2240000 1q #2245000 0q #2245300 1e! 0f! 0g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 0\ 0[ 0Z 0Y 0X 0W 1V 1U 0T 0S 0R 0Q 0P b000 O #2245600 1, #2245800 1'! #2245900 0&! #2246000 1%! #2246100 0%! #2250000 1q #2255000 0q #2255300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2255600 0, #2255800 1&! #2255900 0'! #2260000 1q #2265000 0q #2265300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2265600 1, #2265700 0&! #2265900 1'! #2266100 1( #2266400 0( #2270000 1q #2275000 0q #2275300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2275600 0, #2275700 1&! #2275900 0'! #2276100 1( #2276300 0( #2280000 1q #2285000 0q #2285300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2285600 1, #2285800 1%! #2285900 1'! #2286000 0%! #2286100 0&! #2290000 1q #2295000 0q #2295300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 1\ 1[ 1Z 0Y 1X 1W 1V 1U 0T 0S 0R 0Q 1P b000 O #2295600 0, #2295700 0'! #2295800 1%! #2296000 1&! #2296100 0%! #2300000 1q #2305000 0q #2305300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 1\ 1[ 1Z 0Y 1X 1W 1V 1U 0T 0S 0R 0Q 1P b000 O #2305600 1, #2305700 1'! #2305900 0&! #2310000 1q #2315000 0q #2315300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2315600 0, #2315700 1&! #2315800 0'! 1%! #2315900 0%! 1'! #2316000 0'! #2320000 1q #2325000 0q #2325300 1g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2325600 1, #2325700 0&! #2325800 1'! #2330000 1q #2335000 0q #2335300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2335600 0, #2335700 0'! 1&! #2335900 0&! #2336000 1%! #2336100 0%! 1( #2336200 1&! #2336500 0( #2340000 1q #2345000 0q #2345300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2345600 1, #2345800 1'! #2346000 0&! #2350000 1q #2355000 0q #2355300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2355600 0, #2355700 1&! #2355800 1%! 0'! #2355900 0&! #2356000 0%! #2356100 1&! #2360000 1q #2365000 0q #2365300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2365600 1, #2365700 0&! #2365800 1'! #2370000 1q #2375000 0q #2375300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O #2375600 0, #2375700 0'! 1&! #2375900 0&! #2376000 1&! #2376100 1%! #2376200 0%! #2380000 1q #2385000 0q #2385300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O #2385600 1, #2385800 1'! #2385900 0&! #2386000 1%! #2386100 0%! #2390000 1q #2395000 0q #2395300 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2395600 0, #2395800 1&! #2395900 0'! #2400000 1q #2405000 0q #2405300 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2405700 0&! #2405900 1'! #2406200 1( #2406700 0( #2410000 1q #2410520 0#! #2415000 0q #2415300 1f! 0g! 0h! 0i! #2415500 13 14 #2415600 1+ 1, #2420000 1q #2420520 1#! #2425000 0q #2425300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2425500 03 04 #2425600 0+ #2425700 0'! 1&! #2425800 1%! #2425900 0&! #2426000 0%! 1&! #2426100 0&! #2426200 1( #2426300 0( #2426500 1( #2426600 1) #2426700 1* 0( 0) #2426800 0* #2430000 1q #2435000 0q #2435300 1h! 0i! #2435600 1%! #2435800 0%! 1'! #2440000 1q #2445000 0q #2445300 0n 1m 1l 1i 1h 1g 1f 1e 1` 1X 1V 1U 1Q #2445600 0, #2445700 1&! #2445800 0'! 1%! #2445900 0%! 1'! #2446000 0'! #2450000 1q #2455000 0q #2455300 1i! 0n 1m 1l 1k 0j 1i 1h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 1^ 0] 0\ 1[ 0Z 0Y 1X 0W 1V 1U 0T 0S 0R 1Q 0P b000 O #2455600 1, #2455700 0&! #2455800 1'! #2460000 1q #2465000 0q #2465300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2465600 0, #2465700 0'! 1&! #2465900 0&! #2466000 1%! #2466100 0%! #2466200 1&! #2470000 1q #2475000 0q #2475300 1g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2475600 1, #2475800 1'! #2476000 0&! #2480000 1q #2485000 0q #2485300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2485600 0, #2485700 1&! #2485800 1%! 0'! #2485900 0&! #2486000 0%! #2486100 1&! #2490000 1q #2495000 0q #2495300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2495600 1, #2495700 0&! #2495800 1'! #2496100 1( #2496500 0( #2500000 1q #2505000 0q #2505300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2505600 0, #2505700 0'! 1&! #2505900 0&! #2506000 1&! #2506100 1%! #2506200 0%! #2510000 1q #2515000 0q #2515300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2515600 1, #2515800 1'! #2515900 0&! #2516000 1%! #2516100 0%! #2520000 1q #2525000 0q #2525300 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2525600 0, #2525800 1&! #2525900 0'! #2530000 1q #2535000 0q #2535300 1i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 1a 0` 1_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2535600 1, #2535700 0&! #2535900 1'! #2540000 1q #2545000 0q #2545300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2545600 0, #2545700 1&! #2545900 0'! #2550000 1q #2555000 0q #2555300 1c! 0d! 0e! 0f! 0g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2555600 1, #2555800 1%! #2555900 1'! #2556000 0%! #2556100 0&! #2560000 1q #2565000 0q #2565300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2565600 0, #2565700 0'! #2565800 1%! #2566000 1&! #2566100 0%! #2566200 1( #2566700 0( #2570000 1q #2570520 0#! #2575000 0q #2575300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2575500 13 14 #2575600 1+ 1, #2580000 1q #2580520 1#! #2585000 0q #2585300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2585500 03 04 #2585600 0+ #2585700 1'! 0&! 1%! #2585800 0%! #2585900 1%! #2586000 0'! #2586100 0%! #2586200 1( #2586300 0( #2586500 1( #2586600 1) #2586700 1* 0( 0) #2586800 0* #2590000 1q #2595000 0q #2595300 1h! 0i! #2595800 1'! #2600000 1q #2605000 0q #2605300 0n 1m 1l 1j 1i 1h 1g 1f 1e 1` 1\ 1X 1V 1U 1Q #2605600 0, #2605700 1&! #2605800 1%! 0'! #2605900 0&! #2606000 0%! #2606100 1&! #2610000 1q #2615000 0q #2615300 1i! 0n 1m 1l 1k 1j 1i 1h 1g 1f 1e 0d 0c 0b 0a 1` 0_ 1^ 0] 1\ 1[ 0Z 0Y 1X 0W 1V 1U 0T 0S 0R 1Q 0P b000 O #2615600 1, #2615700 0&! #2615800 1'! #2620000 1q #2625000 0q #2625300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2625600 0, #2625700 0'! 1&! #2625900 0&! #2626000 1&! #2626100 1%! #2626200 0%! #2630000 1q #2635000 0q #2635300 1g! 0h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2635600 1, #2635800 1'! #2635900 0&! #2636000 1%! #2636100 0%! #2640000 1q #2645000 0q #2645300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2645600 0, #2645800 1&! #2645900 0'! #2650000 1q #2655000 0q #2655300 1i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2655600 1, #2655700 0&! #2655900 1'! #2656100 1( #2656500 0( #2660000 1q #2665000 0q #2665300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2665600 0, #2665700 1&! #2665900 0'! #2670000 1q #2675000 0q #2675300 1h! 0i! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2675600 1, #2675800 1%! #2675900 1'! #2676000 0%! #2676100 0&! #2680000 1q #2685000 0q #2685300 0n 1m 1l 1k 1j 1i 0h 0g 1f 0e 1d 1c 0b 0a 1` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2685600 0, #2685700 0'! #2685800 1%! #2686000 1&! #2686100 0%! #2690000 1q #2695000 0q #2695300 1i! 0n 1m 1l 1k 1j 1i 0h 0g 1f 0e 1d 1c 0b 0a 1` 0_ 1^ 0] 0\ 1[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2695600 1, #2695700 1'! #2695900 0&! #2700000 1q #2705000 0q #2705300 0n 1m 0l 0k 0j 0i 0h 0g 1f 1e 1d 0c 0b 0a 1` 1_ 0^ 1] 1\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 1S 0R 1Q 0P b000 O #2705600 0, #2705700 1&! #2705800 0'! 1%! #2705900 0%! 1'! #2706000 0'! #2710000 1q #2715000 0q #2715300 1f! 0g! 0h! 0i! 0n 1m 0l 0k 0j 0i 0h 0g 1f 1e 1d 0c 0b 0a 1` 1_ 0^ 1] 1\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 1S 0R 1Q 0P b000 O #2715600 1, #2715700 0&! #2715800 1'! #2720000 1q #2725000 0q #2725300 0n 1m 1l 0k 1j 1i 1h 1g 0f 0e 0d 0c 0b 1a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 1X 0W 0V 0U 0T 0S 0R 0Q 1P b000 O #2725600 0, #2725700 0'! 1&! #2725900 0&! #2726000 1%! #2726100 0%! #2726200 1&! #2730000 1q #2735000 0q #2735300 1i! 0n 1m 1l 0k 1j 1i 1h 1g 0f 0e 0d 0c 0b 1a 1` 0_ 0^ 1] 1\ 1[ 0Z 0Y 1X 0W 0V 0U 0T 0S 0R 0Q 1P b000 O #2735600 1, #2735800 1'! #2736000 0&! #2736100 1( #2736200 0( #2740000 1q #2745000 0q #2745300 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1g! 1h! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 1^ 1] 0\ 1[ 0Z 1Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #2745500 14 #2745600 10 1/ 0, #2745700 1&! #2745800 1%! 0'! #2745900 0&! #2746000 0%! 1( #2746100 1&! #2746300 0( #2750000 1q #2755000 0q #2755300 1." 10" 11" 0i! 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0e! 0g! 0^ 0] 0[ 0Y 1X 1T 1S 1f 1j 1i 1g 1l 0k 0n #2755500 04 #2755600 00 0/ 1, #2755700 0&! #2755800 1'! #2760000 1q #2765000 0q #2765300 0." 00" 01" 1] 1\ 1V 1U 1Q 1e 1d 1c 1a 1m 0X 0i 0g #2765600 0, #2765700 0'! 1&! #2765900 0&! #2766000 1&! #2766100 1%! #2766200 0%! #2770000 1q #2770720 19 #2770820 09 #2775000 0q #2775300 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1g! 1i! 0n 1m 1l 0k 1j 0i 0h 0g 1f 1e 1d 1c 0b 1a 0` 0_ 0^ 1] 1\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 1S 0R 1Q 0P b000 O #2775500 14 #2775600 10 1. 1/ #2775800 1'! #2775900 0&! #2776000 1%! #2776100 0%! #2776400 1( #2776500 0( #2780000 1q #2780520 0#! #2780820 17 15 #2780920 07 05 #2781020 1: #2781120 0: #2785000 0q #2785300 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0e! 0g! 0i! 0n 0m 1l 0k 1j 1i 0h 1g 1f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 1X 0W 0V 0U 1T 1S 0R 0Q 0P b000 O #2785500 04 #2785600 00 0. 0/ #2785700 0N #2790000 1q #2795000 0q #2795300 0n 0m 1l 0k 1j 1i 0h 1g 1f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 1X 0W 0V 0U 1T 1S 0R 0Q 0P b000 O #2800000 1q #2805000 0q #2805500 13 14 #2805600 1+ 1, #2810000 1q #2810520 1#! #2815000 0q #2815300 1i! 0n 1m 1l 0k 1j 0i 0h 0g 1f 1e 1d 1c 0b 1a 0` 0_ 0^ 1] 1\ 0[ 0Z 0Y 0X 0W 1V 1U 1T 1S 0R 1Q 0P b000 O #2815500 03 04 #2815600 0+ #2815800 0'! #2816200 1( #2816300 0( #2816600 1( 1) #2816700 1* 0( 0) #2816800 0* #2820000 1q #2825000 0q #2825300 1g! 0h! 0i! 1i 1Y #2825700 1&! #2825800 1%! 0&! #2826000 0%! 1'! 1&! #2826100 1( 0&! #2826300 1) #2826400 1* 0( 0) #2826500 0* #2830000 1q #2835000 0q #2835300 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1h! 1i! 0i 1h 0Y 1X #2835500 14 #2835600 10 1/ 0, #2835700 0'! #2835800 1%! #2836000 1&! #2836100 0%! #2840000 1q #2845000 0q #2845300 1." 10" 11" 0i! 0] 1Z 1Y 0V 1R 0Q 0c 1b 0a 1` 0m 1k 1i 0S 0T 0X 0f 0l #2845700 1'! #2845900 0&! #2850000 1q #2850520 0#! #2855000 0q #2855300 1i! 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0e! 0h! b111 O 1P 1S 1T 1W 0Z 1[ 1^ 1_ 1c 1g 0h 0j 1l 1n #2855500 04 #2855600 00 0/ 1, #2860000 1q #2860520 1#! #2865000 0q #2865300 0." 00" 01" 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1] 1X 1V 1Q 1f 1a 1m 1j 1h 0^ 0[ 0W 0R 0P b000 O 0b 0` 0_ 0n 0k 0g #2865500 14 #2865600 10 1/ 0, #2865700 1&! #2865800 0'! 1%! #2865900 0%! 1'! #2866000 0'! #2870000 1q #2875000 0q #2875300 1." 10" 11" 0i! 0] 0X 0V 0Q 0f 0a 0m 0j 0h 1n 0S 0T 0U 0Y 0\ 0c 0d 0e 0i 0l #2875700 0&! #2875800 1'! #2880000 1q #2880520 0#! #2885000 0q #2885300 1h! 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0e! 1f 1i 1m #2885500 04 #2885600 00 0/ 1, #2890000 1q #2890520 1#! #2895000 0q #2895300 0." 00" 01" 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1i! 0g! 1] 1Z 1U 1S 1R 1P b111 O 1e 1c 1b 1a 0f 0n 0m 0i #2895500 14 #2895600 10 1/ 0, #2895700 0'! 1&! #2895900 0&! #2896000 1%! #2896100 0%! #2896200 1&! #2900000 1q #2905000 0q #2905300 1." 10" 11" 0i! 0] 0Z 0U 0S 0R 0P b000 O 0e 0c 0b 0a 1n #2905800 1'! #2906000 0&! #2910000 1q #2910520 0#! #2915000 0q #2915300 1g! 1i! 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0e! 1P 1Q 1R 1e 1f 1g 1h 1i 1j 1m #2915500 04 #2915600 00 0/ 1, #2920000 1q #2920520 1#! #2925000 0q #2925300 0." 00" 01" 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 0g! 0h! 1] 1Z 1Y 1V 1U 1S b111 O 1c 1b 1` 1_ 0R 0Q 0P 0f 0n 0i 0h 0g #2925500 14 #2925600 10 1/ 0, #2925700 1&! #2925800 1%! 0'! #2925900 0&! #2926000 0%! #2926100 1&! #2930000 1q #2935000 0q #2935300 1." 10" 11" 0i! 0] 0Z 0Y 0V 0U 0S b000 O 0c 0b 0` 0_ 1R 1f 1n 0e 0m #2935700 0&! #2935800 1'! #2936400 1( #2936500 0( #2940000 1q #2940520 0#! #2945000 0q #2945300 0V! 0X! 0Y! 0Z! 0[! 0\! 0]! 0^! 0_! 0`! 0a! 0b! 0d! 0f! 1V 1Z 1^ 1b 0f 0j 0n #2945500 04 #2945600 00 0/ 1, #2950000 1q #2950520 1#! #2955000 0q #2955300 0." 00" 01" 1d! 1i! 0e! 1U 1S 1Q 1f 1e 1c 1_ 1n 1m 1l 1k 1i 0^ 0V 0b #2955500 14 #2955600 10 1. 1/ #2955700 0'! 1&! #2955900 0&! #2956000 1&! #2956100 1%! #2956200 0%! #2960000 1q #2960520 0#! #2965000 0q #2965300 1e! 0d! 0i! 0n 0m 0l 1j 1h 0f 1d 0c 1b 1` 0_ 1\ 1Y 0S 0Q #2965500 04 #2965600 00 0. 0/ 0, #2970000 1q #2970520 1#! #2970820 17 15 #2970920 07 05 #2975000 0q #2975300 1i! 0n 0m 0l 1k 1j 1i 1h 0g 0f 1e 1d 0c 1b 0a 1` 0_ 0^ 0] 1\ 0[ 1Z 1Y 0X 0W 0V 1U 0T 0S 1R 0Q 0P b000 O #2975600 1, #2975800 1'! #2975900 0&! #2976000 1%! #2976100 0%! #2980000 1q #2985000 0q #2985300 0n 0m 0l 0k 0j 1i 0h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 1^ 0] 0\ 0[ 1Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #2985600 0, #2985800 1&! #2985900 0'! #2990000 1q #2990720 1: 1; 18 #2990820 0: 0; 08 #2990920 1; #2991020 0; #2995000 0q #2995300 1d! 1h! 0e! 0i! 0n 0m 0l 0k 0j 1i 0h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 1^ 0] 0\ 0[ 1Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #2995500 14 #2995600 10 1. 1/ 1, #2995700 0&! #2995900 1'! #3000000 1q #3000520 0#! #3005000 0q #3005300 1e! 0d! 1n 0m 1l 1k 0j 1i 0h 1g 0f 1e 1d 1c 1b 0a 1` 1_ 1^ 0] 1\ 1[ 0Z 1Y 0X 1W 0V 1U 1T 1S 1R 0Q 1P b111 O #3005500 04 #3005600 00 0. 0/ #3010000 1q #3010520 1#! #3010820 17 15 #3010920 07 05 #3011120 1; #3011220 0; #3015000 0q #3015300 0l 0k 1j 0i 0g 0d 0^ 0W 1V 0T 0R 0P #3015600 0, #3015700 1&! #3015900 0'! #3020000 1q #3025000 0q #3025300 1i! 1n 0m 0l 0k 1j 0i 0h 0g 0f 1e 0d 1c 1b 0a 1` 1_ 0^ 0] 1\ 1[ 0Z 1Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b111 O #3025600 1, #3025800 1%! #3025900 1'! #3026000 0%! #3026100 0&! #3030000 1q #3030720 1: 1; 18 #3030820 0: 0; 08 #3030920 1; #3031020 0; #3035000 0q #3035300 1d! 0e! 1n 0m 0l 1k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 1Z 1Y 0X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #3035500 14 #3035600 10 1. 1/ #3035700 0'! #3035800 1%! #3036000 1&! #3036100 0%! #3040000 1q #3040520 0#! #3045000 0q #3045300 1e! 0d! 0k 0i 0f 0e 0c 0_ 0Z 0Y 0U 0S 0R 0Q #3045500 04 #3045600 00 0. 0/ 0, #3050000 1q #3050520 1#! #3050820 17 15 #3050920 07 05 #3051020 1: #3051120 0: #3055000 0q #3055300 1g! 0h! 0i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #3055600 1, #3055700 1'! #3055900 0&! #3060000 1q #3065000 0q #3065300 0n 0m 0l 0k 0j 0i 1h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 0^ 0] 0\ 0[ 1Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #3065600 0, #3065700 1&! #3065800 0'! 1%! #3065900 0%! 1'! #3066000 0'! #3070000 1q #3070720 1: 1; 18 #3070820 0: 0; 08 #3070920 1; #3071020 0; #3075000 0q #3075300 1d! 0e! 0n 0m 0l 0k 0j 0i 1h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 0^ 0] 0\ 0[ 1Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #3075500 14 #3075600 10 1. 1/ 1, #3075700 0&! #3075800 1'! #3080000 1q #3080520 0#! #3085000 0q #3085300 1e! 1i! 0d! 1n 1m 0l 0k 0j 1i 0h 0g 1f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #3085500 04 #3085600 00 0. 0/ #3090000 1q #3090520 1#! #3090820 17 15 #3090920 07 05 #3091020 1: #3091120 0: 1; #3091220 0; #3095000 0q #3095300 0n 0m 1j 0i 0f 1e 1c 1b 1` 1_ 1] 1\ 1Y 1V 1U 1S b111 O #3095600 0, #3095700 0'! 1&! #3095900 0&! #3096000 1%! #3096100 0%! #3096200 1&! #3100000 1q #3105000 0q #3105300 1h! 0i! 0n 0m 0l 0k 1j 0i 0h 0g 0f 1e 0d 1c 1b 0a 1` 1_ 0^ 1] 1\ 0[ 0Z 1Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b111 O #3105600 1, #3105800 1'! #3106000 0&! #3110000 1q #3110720 1: 1; 18 #3110820 0: 0; 08 #3110920 1; #3111020 0; #3115000 0q #3115300 1d! 1i! 0e! 0h! 1n 1m 0l 0k 0j 1i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 1Z 0Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #3115500 14 #3115600 10 1. 1/ #3115700 1&! #3115800 1%! 0'! #3115900 0&! #3116000 0%! #3116100 1&! #3120000 1q #3120520 0#! #3125000 0q #3125300 1e! 1h! 0d! 0i! 0m 0i 0f 0e 0c 0_ 0Z 0X 0U 0S 0R 0Q #3125500 04 #3125600 00 0. 0/ 0, #3130000 1q #3130520 1#! #3130820 17 15 #3130920 07 05 #3135000 0q #3135300 1i! 1n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P b000 O #3135600 1, #3135700 0&! #3135800 1'! #3140000 1q #3145000 0q #3145300 0n 0m 0l 0k 0j 1i 1h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 1^ 1] 1\ 1[ 0Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #3145600 0, #3145700 0'! 1&! #3145900 0&! #3146000 1&! #3146100 1%! #3146200 0%! #3150000 1q #3150720 1: 1; 18 #3150820 0: 0; 08 #3150920 1; #3151020 0; #3155000 0q #3155300 1d! 0e! 0i! 0n 0m 0l 0k 0j 1i 1h 0g 0f 1e 0d 1c 1b 1a 0` 0_ 1^ 1] 1\ 1[ 0Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #3155500 14 #3155600 10 1. 1/ 1, #3155800 1'! #3155900 0&! #3156000 1%! #3156100 0%! #3160000 1q #3160520 0#! #3165000 0q #3165300 1e! 1f! 0d! 0g! 0h! 1n 1m 0l 0k 1j 1i 1h 1g 1f 1e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 1Q 1P b000 O #3165500 04 #3165600 00 0. 0/ #3170000 1q #3170520 1#! #3170820 17 15 #3170920 07 05 #3171120 1; #3171220 0; #3175000 0q #3175300 1l 1k 0j 0i 0h 0g 0f 1c 1b 1` 1_ 1Y 1V 1U 1S 0R 0Q 0P b111 O #3175600 0, #3175800 1&! #3175900 0'! #3180000 1q #3185000 0q #3185300 1i! 1n 1m 1l 1k 0j 0i 0h 0g 0f 1e 0d 1c 1b 0a 1` 1_ 0^ 0] 0\ 0[ 0Z 1Y 0X 0W 1V 1U 0T 1S 0R 0Q 0P b111 O #3185600 1, #3185700 0&! #3185900 1'! #3190000 1q #3190720 1: 1; 18 #3190820 0: 0; 08 #3190920 1; #3191020 0; #3195000 0q #3195300 1d! 1g! 1h! 0e! 0f! 1n 0m 1l 1k 1j 0i 0h 0g 1f 1e 0d 1c 0b 0a 0` 1_ 0^ 0] 0\ 0[ 1Z 1Y 1X 0W 0V 1U 0T 1S 1R 1Q 0P b000 O #3195500 14 #3195600 10 1. 1/ #3195700 1&! #3195900 0'! #3200000 1q #3200520 0#! #3205000 0q #3205300 1e! 1f! 0d! 0g! 0h! 0l 0k 0e 0c 0_ 0Z 0Y 0X 0U 0S 0Q #3205500 04 #3205600 00 0. 0/ 0, #3210000 1q #3210520 1#! #3210820 17 15 #3210920 07 05 #3211020 1: #3211120 0: #3215000 0q #3215300 1h! 0i! 1n 0m 0l 0k 1j 0i 0h 0g 1f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 1R 0Q 0P b000 O #3215600 1, #3215800 1%! #3215900 1'! #3216000 0%! #3216100 0&! #3220000 1q #3225000 0q #3225300 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 1\ 1[ 1Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O #3225600 0, #3225700 0'! #3225800 1%! #3226000 1&! #3226100 0%! #3230000 1q #3230720 1: 1; 18 #3230820 0: 0; 08 #3230920 1; #3231020 0; #3235000 0q #3235300 1d! 0e! 0h! 1n 0m 0l 1k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 1] 1\ 1[ 1Z 0Y 0X 0W 0V 0U 0T 0S 0R 1Q 0P b111 O #3235500 14 #3235600 10 1. 1/ 1, #3235700 1'! #3235900 0&! #3240000 1q #3240520 0#! #3245000 0q #3245300 1e! 1h! 1i! 0d! 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 1b 0a 0` 0_ 1^ 0] 0\ 0[ 1Z 0Y 0X 0W 1V 0U 0T 0S 1R 0Q 0P b000 O #3245500 04 #3245600 00 0. 0/ #3250000 1q #3250520 1#! #3250820 17 15 #3250920 07 05 #3251020 1: #3251120 0: 1; #3251220 0; #3255000 0q #3255300 0b 0^ 1Y 1X 0V 1T 1S 0R #3255600 0, #3255700 1&! #3255800 0'! 1%! #3255900 0%! 1'! #3256000 0'! #3260000 1q #3265000 0q #3265300 0n 0m 0l 0k 0j 0i 0h 0g 0f 0e 0d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 1Z 1Y 1X 0W 0V 0U 1T 1S 0R 0Q 0P b000 O #3265700 0&! #3265800 1'! #3270000 1q #3270520 0#! #3275000 0q #3275300 1d! 0e! 0i! #3275500 13 14 #3275600 1+ 1, #3280000 1q #3280520 1#! #3285000 0q #3285300 1i! 0n 1m 0l 0k 0j 1i 0h 1g 0f 1e 0d 1c 0b 1a 0` 0_ 1^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 1U 0T 1S 1R 0Q 1P b111 O #3285500 03 04 #3285600 0+ #3285700 1&! #3285800 0'! #3285900 1%! #3286000 0%! #3286100 0&! #3286200 1( #3286300 0( #3286500 1( #3286600 1) #3286700 1* 0( 0) #3286800 0* #3290000 1q #3295000 0q #3295300 1g! 0h! 0i! 0m 1l 1j 1h 1f 1d 1b 1` 1_ 0^ 1\ 0U 1T 0S 0R 0P b000 O #3295800 1%! 1'! #3296200 0%! #3300000 1q #3300720 1: 1; 18 #3300820 0: 0; 08 #3300920 1; #3301020 0; #3305000 0q #3305300 0l 1k #3305500 14 #3305600 10 1. 1/ #3305700 0'! 1&! #3305900 0&! #3306000 1&! #3306100 1%! #3306200 0%! #3310000 1q #3310520 0#! #3315000 0q #3315500 04 #3315600 00 0. 0/ 0, #3320000 1q #3320520 1#! #3325000 0q #3325300 1Y! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1e! 1h! 0P! 0U! 0n 0m 0l 1k 1j 1i 1h 1g 1f 1e 1d 1c 1b 1a 1` 1_ 0^ 0] 1\ 0[ 0Z 0Y 0X 0W 0V 0U 1T 0S 0R 0Q 0P b000 O #3325500 14 #3325600 10 1/ #3325800 1'! #3325900 0&! #3326000 1%! #3326100 0%! 16600 1( 1) #2816700 1* 0( 0) #2816800 0* #2820000 1q #2825000 0q #2825300 1g! 0h! 0i! 1i 1Y #2825700 1&! #2825800 1%! 0&! #2826000 0%! 1'! 1&! #2826100 1( 0&! #2826300 1) #2826400 1* 0( 0) #2826500 0* #2830000 1q #2835000 0q #2835300 1V! 1X! 1Y! 1Z! 1[! 1\! 1]! 1^! 1_! 1`! 1a! 1b! 1d! 1e! 1h! 1i! 0i 1h 0Y 1X #2835500 14INTERFACES/FSDB/FSDBAGILENT93K/exp1.vtran000064400001440000012000000171641103104161000200050ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: FSDB < to > AGILENT93K # # Original File: "exp1.vcd.fsdb" # # Target File: "exp1.agk " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "exp1.vcd.fsdb"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT novas_fsdb; {#### INPUT FORMAT ####} { ########################################################## The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. ############################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS L2_LDB31[2:0] , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into AGILENT93k format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'AGILENT93k'#### } STATE_TRANS 'x'->'X', 'z'->'Z' ; state_trans outputs '0'->'L', '1'->'H'; { ######################################################### In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. ###########################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { #### collapse to cycle-based data, strobe all pins at 49 in cycle #### } { ############################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the HP83000 file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, sampling all input signals at 20 and all output signals at 99 nS into the 100 nS cycle, but strobing the Y1_CMCPU signal at 40 nS into the cycle #################################################################} CYCLE = 100; ALIGN_TO_CYCLE 100 ALL_INPUTS @ 20, ALL_OUTPUTS @ 95, Y1_CMCPU @ 40 ; { #### now define some timing for HP93000 file #### } { #### since VCD file does not contain this info separately #### } PINTYPE NRZ * @ 5, 0; { #### drive all inputs at 5 #### } PINTYPE STB * @ 95; { #### strobe all outputs at 45 #### } PINTYPE RZ Y1_CMCPU @ 0, 50; { #### clock pin behavior #### } SEPARATE_TIMING; DISABLE_VECTOR_FILTER; { #### necessary for cycle-based formats #####} END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN TESTER_FORMAT hp93000 {#### OUTPUT FORMAT ####} -auto_group, REPEAT_THRESHOLD = "32", MAX_LINE_LENGTH = "120", Use_Timeset = "DefTim", DVC_FILE = "exp1.dvc" ; TARGET_FILE "exp1.agk"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/FSDB/FSDBAGILENT93K/exp1.vcd.fsdb000064400001440000012000000310461103104161000203370ustar00jcosleystaff00000400000023HÙ>E[¿/10psApr 21, 1997 11:46:29VERILOG-XL 2.3.3-Ã-ì.@2À”ÿÿÿÿÿÿÿÿ/ SÎÿÎ/V Wed Nov 15 14:12:15 2006unknownsun4uSunOS5.7 Generic_106541-02FSDB_ENV_SYNC_CONTROL=NULL, FSDB_ENV_DUMP_SEQ_NUM=NULL, FSDB_ENV_MAX_GLITCH_NUM=NULL, FSDB_ENV_WRITER_MEM_LIMIT=NULL, FSDB_ENV_NOVAS_LOCK=NULL, FSDB_ENV_LOCK_FILE_LOC=NULLident_ffw_SOL2_DEB_6.1_4.1_SUNOS5.8_/opt/SUNWspro42/SC4.2/bin/cc_10172006þtest`topƒCPU“CEX›shcdp_i0J@ Ðýýýýýÿ!¿E2_CPURSTl INTREQ2'1'0C2_LBUSRDYC1_RSFTENzQACKM S2_EVTSET'R 'R mBCMD5 ë4 ë3 ÷^ã\ïZkWSP«MDb ITLBTBJREAYS1_CEXEC6& F&G&'H& H &G &'F tCDI1ëS÷SãIïP  ëN !×9"Â8#Í7$ÊA%ÕF &ÊQ'ÕD (ÀY)Ë_*ÊM+ÕE,”NOo-Ž SLSRS.LB DB31[2:0]/ñC0Ý21ëS2ëT3ëW 4ë]5÷W6ã]7ïS 8ëZ9÷]:Ã1;ëK <ëL =ëO>÷W?ãO @ïUAëKB÷WCãUDÏNEÊA FÕA GÀSHËJIÊA JÕFKÀOLËFMÊCNT€MI OÌERRPY MQ QYA_ASMRiTM_SU2SRTBMKTmSTPŽUnHSTBVv S AJWqSSLEX}A!\YhIVECRDZšMWR [{SRBL\ªIMASK](P ^(K_(H`t ASLIRWa& Ub|ASPIk c& Nd& I eyMSTcf'Q g'["h'Qi'Aj'Sk&\l&Om&(Sn&5Go& Fp&Wq&'Dr&4Us& Dt&UuSAlDMY1v(Sw(Mx(Gy(Vz(S{(U|(M }'Z~'K'P$€'Q'^‚'Wƒ'E „'M…'B†'Y‡iBRKTYP ˆ'L ‰f LA[$ŠëS‹Ëu$Œë[÷J*ŽãI ïT ëS‘÷W’ã] “ïW”ëK•×u$–ëW—ëB.˜ëA™÷LšãW›ïX œëU ÷OžãWŸÏV ÊM¡ÕW1¢ÀS£Ë_¤ÊI¥ÕP¦ÀO§Ë^ ¨ÊE©uXUBªëC«÷U¬ëU­ëE ®ëG¯×L °ÂU±ÍM7²ÊI ³ÕU´ÀYµËF ¶ÊE ·ÕT¸`YJM¹ëR º÷Y»ëZ¼ëP½÷J¾ÃW¿Î@ ÀÊX<ÁÕJÂÀRÃËD$ÄÊJÅÕJÆÀNÇME1_XEmE^È)M ÉHECS_CLQ,ÊÿEMWBL -ˉH-ÌsLiÍ}HHPÎÿ!!›TÁ´‡´T#Ì(ÍpÁkÁTÜ"˜Œ¸"ÂdG7¸,L,MÈÈ[6(íA2À(Îà{Ä(G­°¹¨¡^m¯%‹¨i'ØyLô%ä'frWyaSdus<{&¬qN gÀø¥ ô06g2\ðßD0­d*b“Ç*0iOaÈé˜4&S?}d&Hqu”k›q$a à SVaƒ'Iu" qL­ §““|•—¬*ˆ§3ì·pœ¯‚ G%€d)lh =,H ÃÃP'u0EQ#‡EÀ‡W‡{gq3ˆIð‡ @+[`‡àO*6G† u]'N e«±u0Ý,IE)* /)QI« £ê`œe k&8)>/&))*E), *8 *&  *&G 8 &« Gœ@' " ®oêu)Ø8€ÅU±ƒ³_Ô¯·É&&™“a)Á“Qæ¡&Ç ƒq5&( ;& K( Ž)( E “>Œ {C m"ÉO%© /]‡& õ \#æ ¦g <ãL‰U8\“|â I)6PX&¹ Ô óp‡÷ i¯-)(±Eu0í³M_u79O4"') #" ¥ë4º „ Ž@éü&^ z&¬‚:tuëHáf@›ÜetÌCbNM“OüD,ý" ‚¼‡åuÁ ÉèAZøCc'tÕ ‡€°YäPu •G"¤O Ћ ÂuM£ÑO|P¶Y÷³E,žµm ý÷ #Q¾`¾¡¶\‡§LÊPÿ©¥• lÐWdéü-˜œ@K 4P'LÃ( K† ‡A7'((> J (A6'*§«(ǹ( ]' (. W¬Ä'ED9F1ªHQS)œ@Ë&å#ŠJe8@8U!ppiC†k_8EuD÷K† ‡j7gcoA‡Ä:M&/T9O¢M‹åÅD'7Y¢WI[µ[/E¶@SWK/TFT0¬J—rûÐ\‘Z'0,Ck \ïZdüÝÐctRj/½Uyt´Y&1·ËU(Û§MN +ô@12YT 8Zf gKM½Xu0iû›ŸDvm{›&4=¯(4ßK³¥Q—+&™ÃPku³& M÷ FÙQ“NPœ@]U ê`E« & õ ©w"S°e›_jM&&)OzE‚l) _ÑmC,>®ªQ–fê#t#ZUIŒB&›ÔÀÛ /EJ åN- ¸€«”o  'åâÙi¥™X®¯*"µú(Š&;•õ&&, ¥ Qå¨S¢ ·ë¿-ªy°yLD\¸(dE°1z E&­ê`G$"àP¢!A¿ž!e\àþ- ®£U† rc])-.[+~‡­.ß [ @“Ü'¥(7gôgug='. *Y]© á§©-KÃP»C+llvRE—d@ „LÒ  Õp‡ïd—%‡Ù\±«b‡”¬6+ZO Fµ*KE(!½µ_¥K(,"¬+S¥¡ “ªK€Lqo¶À‡ 밆޽³½Hµ½-JJ‚ÓˆNi*ËtR¼®&Œu0ø e@z+Ðn¯dY-‰³'•t+IVzg)S¼:KQúE¥Eê`( ­ ‚k}¿wWO )5¥(;bZT™1ûÐHÔÀk5PV¾((ЧIð*ˆº§g¯[WV`gíP†+ &;KQ‹̶¨ª KI,é€yo¿G\©—¹*ð!MÄ òp4„¶Sª‹:U…±R—à «ÃP+² &A…óôp­+FE¾*¡¥LwBfSGYEQŠ›“I¤&Yºðpƒo+8&M¿E'A&% &8å!œ@#SVÝÓ GQ˜}ŒWÍȽ°·#gNMOÁS§ £ •7­„'N P0U,'*<J¼„F\º Š\¢ §¾+*4^(0½(%Q‚çamù_&€@I`W0‡¢ ¯K­·IW³"…U_(¾¬‰V+%± [B€m,.H°Ê±T ªKI²¼å S…MŽS,&&,¼GCŒU¼±pKˆ¥…(ùÝ«©*R£*úq¹ «+)1 K8€ñF(Ñ &2“($®_E…HË…O¢]&¤ÔÀ9»!qëü2'-´t¤3KÅm@óšt,>2ª­pË0&< EJ ›+-^)%˜Z”óf§1( &*:¼ jSœ`E'4v 2&Z3‘l¶ ¹KK¿,·Z¸I( Y8€( ¾î Mç@  &@Ïg’;±M1 RÑGrµ¡ €o&i@Ã(+¯—up‡„ÎR¯ Z©L¼(¼¬ _›ËIv?¦T¨ã=µU(2ÁêZ/?3Øw( ´ ³'!‹9x¹9B\1 )7D …‡n·´«*#3»ò+-1mSí|,6¡@åC¬ )7(&)ÖY'+/F‚~`'ïÐ,T“{D&  >·&7B £Wó ƒ­°-1³ dA4–+~xfx¯hEJ˜ŸCK£g''3G¢¦¤\A½‰U ‡ <&Q®ŒXè&& (54!\&&< E uõ Α+-Ž+g‡ò¡:&rÞK¸()kºE&2 ‹ËEÂ^1Ó)Ž*:¥A[]«S˜^'U‡ ££»É–-Ó5⇠`’~µ/·__¦W& »«ý«eÙ_‚C_]Yõ³[¼ «^EFÉ^ÈCa#[¹M[& GM¥³ßVG‡{… 0P‡_QÿWq&1’0§)&›H& -9R‹N ì·ô –)($q\'t›!1ž§XZ’Q¾Fß×’ó_>&(® ‡Ið¥¨DYdaZ†@*8GÁ¥S\ ¡%kåAp&[EJ0jéü¢#QP Ða ¶ »K‘[›++18&"))&¹…&>M­,ï# š¶ ˆQtžÄ¨ÈRìXùV ‰À÷²!€&!E˜ ,7-@:ÑRm±{H„°Z A&±¶­MKˆ$P$-¨„FÛˆˆ ª),(ÔÉX§#Ý€ §„ð¡$#¦I'7¦8 L#¼Ü!”ÃLôC¬Q)"WE¨L&)¥&<"›½”ý×O}Eµ·v{YsQF¹‹J]_圇F\ kKg[‘‡)[K´W)$)*¡ µ‹*2&§Ç  ˜’È"˜ÈˆeMX!AÏt"È#=Ƚ#Š–&H"€":˜1,!<–*,Ñ# Ê#'Î$*™K=*³."R›ÈwôÑ/$/ 8# !õ©{E—©}¹8!7Ï0]E)#Ó½"6ª*­ /8!0¢ã*Bw«]ËK¬ r eqU!ÏÛ0*#> 4!yÏÈmQ >:8**"9×5 )") ¿«C, )*³«© é4q*j0e)&“Å^®åÈ!£ÕLp%AA( !*©ZmE°iC]&H$ØO%r!‹„oOM¼i5¼MXÑ/<Y#2´W«M¾'>85<&88<§Q¯%ä‡=652Q ®tÇ,ªÂì}I]&”›x+*W,R3U}1*C ¯¥,ºL,uŒE,U,*5$°7G!!åç,<I2<)ŒOLß;6 &0&&KT4#ák:*)>&Õ ".³E <&4_Ç=*y "£0)4,> [¯ ©& y¬oI·&,)<&8E!)8&‚ O°Ñ&6Q#&€M¼(²—HŧK'ØcEC!KN„—4"'èot$É]K]U¸C20E+½¯'tkÁ…'t'0ý«:02K±C'C U¥])*  K.W.&2CôÃÏ“Y)$/S ,«K Ñ1œuø' ÏECo+$sé v\Ï*,$C8&$)AÆ Œth?$±c. y—>*Ñ28&>Ci:>`]ØÙ/( Õƒ­&,.& U¹& q‰) Ç Ách )ójNÌIª)U4 )/6ÇÈMÞÁœT´œ²]!0Ð*Qä* -OLb­°&DÛ"r!ä´e8(Í`+NLOÓ- D$8Á%;@d¢D¾/+9$1–0>0œU‰"!í ݽÝ) !j°>4KÏ̬Ô2# ! > A Ì#bŠÝ­6 G)!„Mœ™"¿GˆÜ¢ÝEO4…ü '#$š(;²$.˜)°ð¤åÍZ—!„Xo!ÔwæP ! Äuœ"þÑ4½ '  TK(-?€˜"PÎ"! ÝZ4–i…(Ë¡Õ÷¥õ7K‡\@ Iºðù Ã,2¥ )N&/VZß¡«í'1E !ÎR TdÿM¢I@á)²˜i˜—…k¥™!¥E"7ÜI[!(O.!^$‰©2N"!¹'¤ª'-Ó$ŠIPö"þ%= ³QMWœö_['¦_‰Ð”C-E'(‰_² '&­‰P­›Ÿ?±ƒS$¯)F&4V& KH¦K&#&*TK)XM©O,&ºQHEQ«R ±; ­) E&&&%ݨZ !ÛeS­¿¥E‰.+^¤&V¨V& EH¼ £½>U&)Q;,¬¸µC±)&K&W&§)­>)5)&)8&²«2]¶¡&2 ± ¡ Q/­/$" æà0 q%&ŠÄwhÈ1YŒŠ‚\!<;O3zZ$¸Œ:!9Ñ’#r & åå L. =&!  ›T¦ ´L ´ #Ì`8€NpŽ&$,HLY1˜h˜ì>'CVˆK 2&¬$ qL'P&'oë #o"`_aÃð—O7 ®`O ªpoO ƒ :&  ðGo¾ oö¦'ÙLlFoã8\8\oí&€!ü_ cópa >û2À”9@'yJ*9DS^m}­½ÍÝíý -=M]m}©µÁÍÙåñý !-9EQ]iu…•¥µÅÕåõ%5EUeu…•¥µÅÕåõ%5EUeu…‘¬¸ÄÐÜèô $4DTdt„”¥¶ÇÓßë÷'3?KWco{‡“Ÿ«·ÃÏÛçóÿ #/;GS_kw‡—§·Ç×ç÷'7GWgw‡—§·Ç×ç÷   ' 7 G W g w ƒ  › § ³ ¿ Ë × ã ï û    + 7 C O [ g s  ‹ — £ ¯ » Ç Ó ß ë ÷    /þtest`topƒCPU“CEX›shcdp_i0J@ Ðýýýýýÿ!¿E2_CPURSTl INTREQ2'1'0C2_LBUSRDYC1_RSFTENzQACKM S2_EVTSET'R 'R mBCMD5 ë4 ë3 ÷^ã\ïZkWSP«MDb ITLBTBJREAYINTERFACES/FSDB/README000064400001440000012000000013031103104161000147070ustar00jcosleystaff00000400000023The main directory is "FSDB" and the sub-directories are -> FSDBAGILENT93K/ -> FSDBSTIL/ -> FSDBVERILOG/ The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "FSDBSTIL" contains the translation of FSDB file to STIL output format. Sub-directory -> "FSDBVERILOG" contains the translation of FSDB file to Verilog testbench output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The FSDB interface only includes a Reader at this time. Because FSDB is a binary format, each sub-directory includes a VCD file or EVCD file that represents the data in the FSDB IVF file. INTERFACES/FSDB/t000064400001440000012000000000601103104161000142140ustar00jcosleystaff00000400000023FSDBAGILENT93K/ FSDBSTIL/ FSDBVERILOG/ README t INTERFACES/TERADYNE/000075500001440000012000000000001103104161000145275ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/TDSCATAL/000075500001440000012000000000001103104161000157265ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/TDSCATAL/exp1.vtran000064400001440000012000000057211103104161000176640ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: TDS < to > CATALYST # # Original File: "exp1.tds" # # Target File: "exp1.catl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { ###################################################################### Translate a TSSI TDS file to TERADYNE This VTRAN command file translates a TSSI TDS file, using a canned reader, to a TERADYNE-formated file. The TDS file is a print-on-change simulation data file. For each of the statements below, only those which will change for different designs are commented. All others will always be there. #######################################################################} { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.tds"; {#### INPUT VECTOR FILE ####} aux_file "exp1.sdf"; {#### TDS Signal Definition File #### } tabular_format tds; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the TDS # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin cycle 100; { #### The cycle time #### } disable_vector_filter; align_to_step 100, 99; { #### state character translations for 'TDS'->''CATALYST #### } state_trans 'D'->'0', 'U'->'1', 'N'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus_$vec; {##### Flatten Busses ####} tester_format teradyne -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp1.cytl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/TDSCATAL/exp1.tds000064400001440000012000000520161103104161000173230ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.tds" # # Original File: "exp1.tds" # # Target File: "exp1.catl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# .0ns N N N N X N N N N N N N U U # time = 0 15.0ns D D D D X D U U U U U U U U # time = 15 125.0ns U U D D X D D D D D D D D U # time = 125 200.0ns U U D D X U D D D D D D D U # time = 200 250.0ns U U D D X D D D D D D D D U # time = 250 300.0ns U U D D X U D D D D D D D U # this is a comment at time 300 380.0ns U U D D X D D D D D D D D U # comment at time 350 400.0ns U U D D X U D D D D D D D U # comment at time 400 425.0ns U U D D X U Z Z Z Z Z Z Z Z # time = 425 450.0ns U U D D X D Z Z Z Z Z Z Z Z # time = 450 475.0ns U U D D X D L L L L L L L H # time = 475 500.0ns U U D D X U Z Z Z Z Z Z Z Z # time = 500 525.0ns U U D D X U D D D D D D D U 550.0ns U U D D X D D D D D D D D U # comment above time 600 600.0ns U U D D X U D D D D D D D U 650.0ns U U D D X D D D D D D D D U 675.0ns U U D D H D D D D D D D D U 700.0ns U U D D X U D D D D D D D U 725.0ns U U U D X U D D D D D U D U 750.0ns U U U D X D D D D D D U D U 775.0ns U U U D H D D D D D D U D U 800.0ns U U U D X U D D D D D U D U 850.0ns U U U D X D D D D D D U D U 875.0ns U U U D H D D D D D D U D U 900.0ns U U U D X U D D D D D U D U 925.0ns D U U D X U D D D D D U D U 950.0ns D U U D X D D D D D D U D U 975.0ns D U U D L D D D D D D U D U 1000.0ns D U U D X U D D D D D U D U 1050.0ns D U U D X D D D D D D U D U 1075.0ns D U U D L D D D D D D U D U 1100.0ns D U U D X U D D D D D U D U 1150.0ns D U U D X D D D D D D U D U 1200.0ns D U U D X U D D D D D U D U 1225.0ns U U U D X U D D D D D U D U 1250.0ns U U U D X D D D D D D U D U 1300.0ns U U U D X U D D D D D U D U 1325.0ns D U U D X U D D D D D U D U 1350.0ns D U U D X D D D D D D U D U 1400.0ns D U U D X U D D D D D U D U 1425.0ns U U U D X U D D D D D U D U 1450.0ns U U U D X D D D D D D U D U 1500.0ns U U U D X U D D D D D U D U 1550.0ns U U U D X D D D D D D U D U 1575.0ns U U U D L D D D D D D U D U 1600.0ns U U U D X U D D D D D U D U 1625.0ns D U U D X U D D D D D U D U 1650.0ns D U U D X D D D D D D U D U 1675.0ns D U U D L D D D D D D U D U 1700.0ns D U U D X U D D D D D U D U 1725.0ns U U U D X U D D D D D U D U 1750.0ns U U U D X D D D D D D U D U 1775.0ns U U U D L D D D D D D U D U 1800.0ns U U U D X U D D D D D U D U 1850.0ns U U U D X D D D D D D U D U 1875.0ns U U U D L D D D D D D U D U 1900.0ns U U U D X U D D D D D U D U 1925.0ns D U U D X U D D D D D U D U 1950.0ns D U U D X D D D D D D U D U 1975.0ns D U U D L D D D D D D U D U 2000.0ns D U U D X U D D D D D U D U 2050.0ns D U U D X D D D D D D U D U 2075.0ns D U U D L D D D D D D U D U 2100.0ns D U U D X U D D D D D U D U 2125.0ns U U U D X U D D D D D U D U 2150.0ns U U U D X D D D D D D U D U 2175.0ns U U U D L D D D D D D U D U 2200.0ns U U U D X U D D D D D U D U 2225.0ns D D U U X U U U U U U U U D 2250.0ns D D U U X D U U U U U U U D 2275.0ns D D U U L D U U U U U U U D # Comments from Tim #Comments from Tim #45678901234567890123456789012345678901234567890123456789012345678901 2300.0ns D D U U X U U U U U U U U D 2325.0ns U U U D X U U U U D D U U U 2350.0ns U U U D X D U U U D D U U U 2375.0ns U U U D H D U U U D D U U U 2400.0ns U U U D X U U U U D D U U U 2450.0ns U U U D X D U U U D D U U U 2475.0ns U U U D H D U U U D D U U U 2500.0ns U U U D X U U U U D D U U U 2525.0ns D U U D X U U U U D D U U U 2550.0ns D U U D X D U U U D D U U U 2575.0ns D U U D L D U U U D D U U U 2600.0ns D U U D X U U U U D D U U U 2650.0ns D U U D X D U U U D D U U U 2675.0ns D U U D L D U U U D D U U U 2700.0ns D U U D X U U U U D D U U U 2750.0ns D U U D X D U U U D D U U U 2800.0ns D U U D X U U U U D D U U U 2825.0ns U U U D X U U U U D D U U U 2850.0ns U U U D X D U U U D D U U U 2900.0ns U U U D X U U U U D D U U U 2925.0ns D U U D X U U U U D D U U U 2950.0ns D U U D X D U U U D D U U U 3000.0ns D U U D X U U U U D D U U U 3025.0ns U U U D X U U U U D D U U U 3050.0ns U U U D X D U U U D D U U U 3100.0ns U U U D X U U U U D D U U U 3150.0ns U U U D X D U U U D D U U U 3175.0ns U U U D L D U U U D D U U U 3200.0ns U U U D X U U U U D D U U U 3225.0ns D U U D X U U U U D D U U U 3250.0ns D U U D X D U U U D D U U U 3275.0ns D U U D L D U U U D D U U U 3300.0ns D U U D X U U U U D D U U U 3325.0ns U U U D X U U U U D D U U U 3350.0ns U U U D X D U U U D D U U U 3375.0ns U U U D L D U U U D D U U U 3400.0ns U U U D X U U U U D D U U U 3450.0ns U U U D X D U U U D D U U U 3475.0ns U U U D L D U U U D D U U U 3500.0ns U U U D X U U U U D D U U U 3525.0ns D U U D X U U U U D D U U U 3550.0ns D U U D X D U U U D D U U U 3575.0ns D U U D L D U U U D D U U U 3600.0ns D U U D X U U U U D D U U U 3650.0ns D U U D X D U U U D D U U U 3675.0ns D U U D L D U U U D D U U U 3700.0ns D U U D X U U U U D D U U U 3725.0ns U U U D X U U U U D D U U U 3750.0ns U U U D X D U U U D D U U U 3775.0ns U U U D L D U U U D D U U U 3800.0ns U U U D X U U U U D D U U U 3850.0ns U U U D X D U U U D D U U U 3875.0ns U U U D H D U U U D D U U U 3900.0ns U U U D X U U U U D D U U U 3950.0ns U U U D X D U U U D D U U U 3975.0ns U U U D H D U U U D D U U U 4000.0ns U U U D X U U U U D D U U U 4050.0ns U U U D X D U U U D D U U U 4075.0ns U U U D H D U U U D D U U U 4100.0ns U U U D X U U U U D D U U U 4150.0ns U U U D X D U U U D D U U U 4175.0ns U U U D H D U U U D D U U U 4200.0ns U U U D X U U U U D D U U U 4250.0ns U U U D X D U U U D D U U U 4275.0ns U U U D H D U U U D D U U U 4300.0ns U U U D X U U U U D D U U U 4325.0ns D U U D X U U U U D D U U U 4350.0ns D U U D X D U U U D D U U U 4375.0ns D U U D L D U U U D D U U U 4400.0ns D U U D X U U U U D D U U U 4450.0ns D U U D X D U U U D D U U U 4475.0ns D U U D L D U U U D D U U U 4500.0ns D U U D X U U U U D D U U U 4550.0ns D U U D X D U U U D D U U U 4575.0ns D U U D L D U U U D D U U U 4600.0ns D U U D X U U U U D D U U U 4650.0ns D U U D X D U U U D D U U U 4675.0ns D U U D L D U U U D D U U U 4700.0ns D U U D X U U U U D D U U U 4750.0ns D U U D X D U U U D D U U U 4775.0ns D U U D L D U U U D D U U U 4800.0ns D U U D X U U U U D D U U U 4825.0ns D D U U X U U U U D D U U D 4850.0ns D D U U X D U U U D D U U D 4875.0ns D D U U L D U U U D D U U D 4900.0ns D D U U X U U U U D D U U D 4925.0ns D U U D X U U U U U U U D U 4950.0ns D U U D X D U U U U U U D U 4975.0ns D U U D L D U U U U U U D U 5000.0ns D U U D X U U U U U U U D U 5050.0ns D U U D X D U U U U U U D U 5075.0ns D U U D L D U U U U U U D U 5100.0ns D U U D X U U U U U U U D U 5150.0ns D U U D X D U U U U U U D U 5175.0ns D U U D L D U U U U U U D U 5200.0ns D U U D X U U U U U U U D U 5250.0ns D U U D X D U U U U U U D U 5275.0ns D U U D L D U U U U U U D U 5300.0ns D U U D X U U U U U U U D U 5350.0ns D U U D X D U U U U U U D U 5375.0ns D U U D L D U U U U U U D U 5400.0ns D U U D X U U U U U U U D U 5450.0ns D U U D X D U U U U U U D U 5475.0ns D U U D L D U U U U U U D U 5500.0ns D U U D X U U U U U U U D U 5550.0ns D U U D X D U U U U U U D U 5575.0ns D U U D L D U U U U U U D U 5600.0ns D U U D X U U U U U U U D U 5650.0ns D U U D X D U U U U U U D U 5675.0ns D U U D L D U U U U U U D U 5700.0ns D U U D X U U U U U U U D U 5750.0ns D U U D X D U U U U U U D U 5775.0ns D U U D L D U U U U U U D U 5800.0ns D U U D X U U U U U U U D U 5850.0ns D U U D X D U U U U U U D U 5875.0ns D U U D L D U U U U U U D U 5900.0ns D U U D X U U U U U U U D U 5925.0ns U U U D X U U U U U U U D U 5950.0ns U U U D X D U U U U U U D U 5975.0ns U U U D H D U U U U U U D U 6000.0ns U U U D X U U U U U U U D U 6050.0ns U U U D X D U U U U U U D U 6075.0ns U U U D H D U U U U U U D U 6100.0ns U U U D X U U U U U U U D U 6150.0ns U U U D X D U U U U U U D U 6175.0ns U U U D H D U U U U U U D U 6200.0ns U U U D X U U U U U U U D U 6250.0ns U U U D X D U U U U U U D U 6275.0ns U U U D H D U U U U U U D U 6300.0ns U U U D X U U U U U U U D U 6350.0ns U U U D X D U U U U U U D U 6375.0ns U U U D H D U U U U U U D U 6400.0ns U U U D X U U U U U U U D U 6450.0ns U U U D X D U U U U U U D U 6475.0ns U U U D H D U U U U U U D U 6500.0ns U U U D X U U U U U U U D U 6550.0ns U U U D X D U U U U U U D U 6575.0ns U U U D H D U U U U U U D U 6600.0ns U U U D X U U U U U U U D U 6650.0ns U U U D X D U U U U U U D U 6675.0ns U U U D H D U U U U U U D U 6700.0ns U U U D X U U U U U U U D U 6750.0ns U U U D X D U U U U U U D U 6775.0ns U U U D H D U U U U U U D U 6800.0ns U U U D X U U U U U U U D U 6850.0ns U U U D X D U U U U U U D U 6875.0ns U U U D H D U U U U U U D U 6900.0ns U U U D X U U U U U U U D U 6925.0ns D U U D X U U U U U U U D U 6950.0ns D U U D X D U U U U U U D U 6975.0ns D U U D L D U U U U U U D U 7000.0ns D U U D X U U U U U U U D U 7050.0ns D U U D X D U U U U U U D U 7075.0ns D U U D L D U U U U U U D U 7100.0ns D U U D X U U U U U U U D U 7150.0ns D U U D X D U U U U U U D U 7175.0ns D U U D L D U U U U U U D U 7200.0ns D U U D X U U U U U U U D U 7250.0ns D U U D X D U U U U U U D U 7275.0ns D U U D L D U U U U U U D U 7300.0ns D U U D X U U U U U U U D U 7350.0ns D U U D X D U U U U U U D U 7375.0ns D U U D L D U U U U U U D U 7400.0ns D U U D X U U U U U U U D U 7450.0ns D U U D X D U U U U U U D U 7475.0ns D U U D L D U U U U U U D U 7500.0ns D U U D X U U U U U U U D U 7550.0ns D U U D X D U U U U U U D U 7575.0ns D U U D L D U U U U U U D U 7600.0ns D U U D X U U U U U U U D U 7650.0ns D U U D X D U U U U U U D U 7675.0ns D U U D L D U U U U U U D U 7700.0ns D U U D X U U U U U U U D U 7750.0ns D U U D X D U U U U U U D U 7775.0ns D U U D L D U U U U U U D U 7800.0ns D U U D X U U U U U U U D U 7850.0ns D U U D X D U U U U U U D U 7875.0ns D U U D L D U U U U U U D U 7900.0ns D U U D X U U U U U U U D U 7925.0ns U U U D X U U U U U U U D U 7950.0ns U U U D X D U U U U U U D U 7975.0ns U U U D H D U U U U U U D U 8000.0ns U U U D X U U U U U U U D U 8050.0ns U U U D X D U U U U U U D U 8075.0ns U U U D H D U U U U U U D U 8100.0ns U U U D X U U U U U U U D U 8150.0ns U U U D X D U U U U U U D U 8175.0ns U U U D H D U U U U U U D U 8200.0ns U U U D X U U U U U U U D U 8250.0ns U U U D X D U U U U U U D U 8275.0ns U U U D H D U U U U U U D U 8300.0ns U U U D X U U U U U U U D U 8350.0ns U U U D X D U U U U U U D U 8375.0ns U U U D H D U U U U U U D U 8400.0ns U U U D X U U U U U U U D U 8450.0ns U U U D X D U U U U U U D U 8475.0ns U U U D H D U U U U U U D U 8500.0ns U U U D X U U U U U U U D U 8550.0ns U U U D X D U U U U U U D U 8575.0ns U U U D H D U U U U U U D U 8600.0ns U U U D X U U U U U U U D U 8650.0ns U U U D X D U U U U U U D U 8675.0ns U U U D H D U U U U U U D U 8700.0ns U U U D X U U U U U U U D U 8750.0ns U U U D X D U U U U U U D U 8775.0ns U U U D H D U U U U U U D U 8800.0ns U U U D X U U U U U U U D U 8850.0ns U U U D X D U U U U U U D U 8875.0ns U U U D H D U U U U U U D U 8900.0ns U U U D X U U U U U U U D U 8925.0ns D U U D X U U U U U U U D U 8950.0ns D U U D X D U U U U U U D U 8975.0ns D U U D L D U U U U U U D U 9000.0ns D U U D X U U U U U U U D U 9050.0ns D U U D X D U U U U U U D U 9075.0ns D U U D L D U U U U U U D U 9100.0ns D U U D X U U U U U U U D U 9150.0ns D U U D X D U U U U U U D U 9175.0ns D U U D L D U U U U U U D U 9200.0ns D U U D X U U U U U U U D U 9250.0ns D U U D X D U U U U U U D U 9275.0ns D U U D L D U U U U U U D U 9300.0ns D U U D X U U U U U U U D U 9350.0ns D U U D X D U U U U U U D U 9375.0ns D U U D L D U U U U U U D U 9400.0ns D U U D X U U U U U U U D U 9450.0ns D U U D X D U U U U U U D U 9475.0ns D U U D L D U U U U U U D U 9500.0ns D U U D X U U U U U U U D U 9550.0ns D U U D X D U U U U U U D U 9575.0ns D U U D L D U U U U U U D U 9600.0ns D U U D X U U U U U U U D U 9650.0ns D U U D X D U U U U U U D U 9675.0ns D U U D L D U U U U U U D U 9700.0ns D U U D X U U U U U U U D U 9750.0ns D U U D X D U U U U U U D U 9775.0ns D U U D L D U U U U U U D U 9800.0ns D U U D X U U U U U U U D U 9850.0ns D U U D X D U U U U U U D U 9875.0ns D U U D L D U U U U U U D U 9900.0ns D U U D X U U U U U U U D U 9925.0ns U U U D X U U U U U U U D U 9950.0ns U U U D X D U U U U U U D U 9975.0ns U U U D H D U U U U U U D U 10000.0ns U U U D X U U U U U U U D U 10050.0ns U U U D X D U U U U U U D U 10075.0ns U U U D H D U U U U U U D U 10100.0ns U U U D X U U U U U U U D U 10150.0ns U U U D X D U U U U U U D U 10175.0ns U U U D H D U U U U U U D U 10200.0ns U U U D X U U U U U U U D U 10250.0ns U U U D X D U U U U U U D U 10275.0ns U U U D H D U U U U U U D U 10300.0ns U U U D X U U U U U U U D U 10350.0ns U U U D X D U U U U U U D U 10375.0ns U U U D H D U U U U U U D U 10400.0ns U U U D X U U U U U U U D U 10450.0ns U U U D X D U U U U U U D U 10475.0ns U U U D H D U U U U U U D U 10500.0ns U U U D X U U U U U U U D U 10550.0ns U U U D X D U U U U U U D U 10575.0ns U U U D H D U U U U U U D U 10600.0ns U U U D X U U U U U U U D U 10650.0ns U U U D X D U U U U U U D U 10675.0ns U U U D H D U U U U U U D U 10700.0ns U U U D X U U U U U U U D U 10750.0ns U U U D X D U U U U U U D U 10775.0ns U U U D H D U U U U U U D U 10800.0ns U U U D X U U U U U U U D U 10850.0ns U U U D X D U U U U U U D U 10875.0ns U U U D H D U U U U U U D U 10900.0ns U U U D X U U U U U U U D U 10925.0ns D U U D X U U U U U U U D U 10950.0ns D U U D X D U U U U U U D U 10975.0ns D U U D L D U U U U U U D U 11000.0ns D U U D X U U U U U U U D U 11050.0ns D U U D X D U U U U U U D U 11075.0ns D U U D L D U U U U U U D U 11100.0ns D U U D X U U U U U U U D U 11150.0ns D U U D X D U U U U U U D U 11175.0ns D U U D L D U U U U U U D U 11200.0ns D U U D X U U U U U U U D U 11250.0ns D U U D X D U U U U U U D U 11275.0ns D U U D L D U U U U U U D U 11300.0ns D U U D X U U U U U U U D U 11350.0ns D U U D X D U U U U U U D U 11375.0ns D U U D L D U U U U U U D U 11400.0ns D U U D X U U U U U U U D U 11450.0ns D U U D X D U U U U U U D U 11475.0ns D U U D L D U U U U U U D U 11500.0ns D U U D X U U U U U U U D U 11550.0ns D U U D X D U U U U U U D U 11575.0ns D U U D L D U U U U U U D U 11600.0ns D U U D X U U U U U U U D U 11650.0ns D U U D X D U U U U U U D U 11675.0ns D U U D L D U U U U U U D U 11700.0ns D U U D X U U U U U U U D U 11750.0ns D U U D X D U U U U U U D U 11775.0ns D U U D L D U U U U U U D U 11800.0ns D U U D X U U U U U U U D U 11850.0ns D U U D X D U U U U U U D U 11875.0ns D U U D L D U U U U U U D U 11900.0ns D U U D X U U U U U U U D U 11925.0ns U U U D X U U U U U U U D U 11950.0ns U U U D X D U U U U U U D U 11975.0ns U U U D H D U U U U U U D U 12000.0ns U U U D X U U U U U U U D U 12050.0ns U U U D X D U U U U U U D U 12075.0ns U U U D H D U U U U U U D U 12100.0ns U U U D X U U U U U U U D U 12150.0ns U U U D X D U U U U U U D U 12175.0ns U U U D H D U U U U U U D U 12200.0ns U U U D X U U U U U U U D U 12250.0ns U U U D X D U U U U U U D U 12275.0ns U U U D H D U U U U U U D U 12300.0ns U U U D X U U U U U U U D U 12350.0ns U U U D X D U U U U U U D U 12375.0ns U U U D H D U U U U U U D U 12400.0ns U U U D X U U U U U U U D U 12450.0ns U U U D X D U U U U U U D U 12475.0ns U U U D H D U U U U U U D U 12500.0ns U U U D X U U U U U U U D U 12550.0ns U U U D X D U U U U U U D U 12575.0ns U U U D H D U U U U U U D U 12600.0ns U U U D X U U U U U U U D U 12650.0ns U U U D X D U U U U U U D U 12675.0ns U U U D H D U U U U U U D U 12700.0ns U U U D X U U U U U U U D U 12750.0ns U U U D X D U U U U U U D U 12775.0ns U U U D H D U U U U U U D U 12800.0ns U U U D X U U U U U U U D U 12850.0ns U U U D X D U U U U U U D U 12875.0ns U U U D H D U U U U U U D U 12900.0ns U U U D X U U U U U U U D U 12925.0ns D U U D X U U U U U U U D U 12950.0ns D U U D X D U U U U U U D U 12975.0ns D U U D L D U U U U U U D U 13000.0ns D U U D X U U U U U U U D U 13050.0ns D U U D X D U U U U U U D U 13075.0ns D U U D L D U U U U U U D U 13100.0ns D U U D X U U U U U U U D U 13150.0ns D U U D X D U U U U U U D U 13175.0ns D U U D L D U U U U U U D U 13200.0ns D U U D X U U U U U U U D U 13250.0ns D U U D X D U U U U U U D U 13275.0ns D U U D L D U U U U U U D U 13300.0ns D U U D X U U U U U U U D U 13350.0ns D U U D X D U U U U U U D U 13375.0ns D U U D L D U U U U U U D U 13400.0ns D U U D X U U U U U U U D U 13450.0ns D U U D X D U U U U U U D U 13475.0ns D U U D L D U U U U U U D U 13500.0ns D U U D X U U U U U U U D U 13550.0ns D U U D X D U U U U U U D U 13575.0ns D U U D L D U U U U U U D U 13600.0ns D U U D X U U U U U U U D U 13650.0ns D U U D X D U U U U U U D U 13675.0ns D U U D L D U U U U U U D U 13700.0ns D U U D X U U U U U U U D U 13750.0ns D U U D X D U U U U U U D U 13775.0ns D U U D L D U U U U U U D U 13800.0ns D U U D X U U U U U U U D U 13850.0ns D U U D X D U U U U U U D U 13875.0ns D U U D L D U U U U U U D U 13900.0ns D U U D X U U U U U U U D U 13925.0ns U U U D X U U U U U U U D U 13950.0ns U U U D X D U U U U U U D U 13975.0ns U U U D H D U U U U U U D U 14000.0ns U U U D X U U U U U U U D U 14050.0ns U U U D X D U U U U U U D U 14075.0ns U U U D H D U U U U U U D U 14100.0ns U U U D X U U U U U U U D U 14150.0ns U U U D X D U U U U U U D U 14175.0ns U U U D H D U U U U U U D U 14200.0ns U U U D X U U U U U U U D U 14250.0ns U U U D X D U U U U U U D U 14275.0ns U U U D H D U U U U U U D U 14300.0ns U U U D X U U U U U U U D U 14350.0ns U U U D X D U U U U U U D U 14375.0ns U U U D H D U U U U U U D U 14400.0ns U U U D X U U U U U U U D U 14450.0ns U U U D X D U U U U U U D U 14475.0ns U U U D H D U U U U U U D U 14500.0ns U U U D X U U U U U U U D U 14550.0ns U U U D X D U U U U U U D U 14575.0ns U U U D H D U U U U U U D U 14600.0ns U U U D X U U U U U U U D U 14650.0ns U U U D X D U U U U U U D U 14675.0ns U U U D H D U U U U U U D U 14700.0ns U U U D X U U U U U U U D U 14750.0ns U U U D X D U U U U U U D U 14775.0ns U U U D H D U U U U U U D U 14800.0ns U U U D X U U U U U U U D U 14850.0ns U U U D X D U U U U U U D U 14875.0ns U U U D H D U U U U U U D U 14900.0ns U U U D X U U U U U U U D U 14925.0ns D D U U X U U U U U U U U D 14950.0ns D D U U X D U U U U U U U D 14975.0ns D D U U H D U U U U U U U D # comment above last vector - 3 15000.0ns D D U U X U U U U U U U U D # comment above last vector - 2 15050.0ns D D U U X D U U U U U U U D # comment above last vector - 1 15075.0ns D D U U H D U U U U U U U D # comment above last vector 15100.0ns D D U U X U U U U U U U U D # comment after last vector U D L D U U U U U U D U 7600.0ns D U U D X U U U U U U U D U 7650.0ns D U U D X D U U U U U U D U 7675.0ns D U U D L D U U U U U U D U 7700.0ns D U U D X U U U U U U U D U 7750.0ns D U U D X D U U U U U U D U 7775.0ns D U U D L D U U U U U U D U 7800.0ns D U U D X U U U U U U U D U 7850.0ns D U U D X D U U U U U U D U 7875.0ns D U U D L D U U U U U U D U 7900.0ns D U U D X U U U U U U U D U 7925.0ns U U U D X U U U U U U U D U INTERFACES/TERADYNE/TDSCATAL/exp1.sdf000064400001440000012000000015151103104161000173030ustar00jcosleystaff00000400000023#====================================================# # This is TDS signal defination file # # DESIGN NAME: multiplier # # CUSTOMER: Source III, Inc. # # LIBRARY TYPE: library_zip # # REVISION: 1.00 # # # #====================================================# \si 1 I # undefined i1[A] 2 I # undefined i2[B] 3 I # undefined i3[C] 4 I # undefined so[1] 5 O # undefined ck 6 I # undefined bus[3][7] 7 I O # undefined bus[3][6] 8 I O # undefined bus[3][5] 9 IO # undefined bus[3][4] 10 IO # undefined bus[3][3] 11 IO # undefined bus[3][2] 12 I O # undefined bus[3][1] 13 I O # undefined bus[3][0] 14 I O # undefined INTERFACES/TERADYNE/TDSCATAL/exp2.vtran000064400001440000012000000057211103104161000176650ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: TDS < to > CATALYST # # Original File: "exp1.tds" # # Target File: "exp1.catl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { ###################################################################### Translate a TSSI TDS file to TERADYNE This VTRAN command file translates a TSSI TDS file, using a canned reader, to a TERADYNE-formated file. The TDS file is a print-on-change simulation data file. For each of the statements below, only those which will change for different designs are commented. All others will always be there. #######################################################################} { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.tds"; {#### INPUT VECTOR FILE ####} aux_file "exp1.sdf"; {#### TDS Signal Definition File #### } tabular_format tds; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the TDS # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin cycle 100; { #### The cycle time #### } disable_vector_filter; align_to_step 100, 99; { #### state character translations for 'TDS'->''CATALYST #### } state_trans 'D'->'0', 'U'->'1', 'N'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus_$vec; {##### Flatten Busses ####} tester_format teradyne -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp1.cytl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/WGLJ973/000075500001440000012000000000001103104161000155355ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/WGLJ973/exp2.vtran000064400001440000012000000052421103104161000174720ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J973 # # Original File: "exp1.wgl" # # Target File: "exp2.j973 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'J973'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'X', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp2.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/WGLJ973/exp1.vtran000064400001440000012000000054031103104161000174700ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J973 # # Original File: "exp1.wgl" # # Target File: "exp1.j973 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'J973'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'X', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp1.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/WGLJ973/exp3.vtran000064400001440000012000000052511103104161000174730ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J973 # # Original File: "exp1.wgl" # # Target File: "exp3.j973 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -cycle -scan ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'J973'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'X', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp3.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/WGLJ971/000075500001440000012000000000001103104161000155335ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/WGLJ971/exp2.vtran000064400001440000012000000046531103104161000174750ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J971 # # Original File: "exp1.wgl" # # Target File: "exp2.j971 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J971'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs '-'->'X'; state_trans outputs '1'->'H', '0'->'L', '-'->'X', 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp2.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLJ971/exp1.vtran000064400001440000012000000050111103104161000174610ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J971 # # Original File: "exp1.wgl" # # Target File: "exp1.j971 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J971'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs '-'->'X'; state_trans outputs '1'->'H', '0'->'L', '-'->'X', 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp1.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLJ971/exp3.vtran000064400001440000012000000046621103104161000174760ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J971 # # Original File: "exp1.wgl" # # Target File: "exp3.j971 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J971'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs '-'->'X'; state_trans outputs '1'->'H', '0'->'L', '-'->'X', 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp3.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLJ750/000075500001440000012000000000001103104161000155265ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/WGLJ750/exp2.vtran000064400001440000012000000047521103104161000174700ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J750 # # Original File: "exp1.wgl" # # Target File: "exp2.j750 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J750'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp2.testertim"; {#### OUTPUT FORMAT ####} target_file "exp2.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLJ750/exp1.vtran000064400001440000012000000047761103104161000174750ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J750 # # Original File: "exp1.wgl" # # Target File: "exp1.j750 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J750'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp1.testertim"; {#### OUTPUT FORMAT ####} target_file "exp1.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLJ750/exp3.vtran000064400001440000012000000047611103104161000174710ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > J750 # # Original File: "exp1.wgl" # # Target File: "exp3.j750 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'J750'#### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp3.testertim"; {#### OUTPUT FORMAT ####} target_file "exp3.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/README000064400001440000012000000713501103104161000154150ustar00jcosleystaff00000400000023TERADYNE -------- The main directory is "TERADYNE" and the sub-directories are -> EVCDFLEX -> EVCDJ750 -> WGLCATAL -> WGLFLEX -> WGLJ950 -> WGLJ971 -> WGLJ973 -> VCDJ973 -> STILCATAL -> STILFLEX -> STILJ750 -> STILJ971 -> STILJ973 -> TDSCATAL -> VCDJ973T -> CATALSTIL -> CATALVERILOG -> FLEXSTIL -> FLEXVERILOG -> J750PLUSSTIL -> J750PLUSVERILOG -> J750STIL -> J750VERILOG The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLJ971" contains the translation of WGL file to J971 output format. Sub-directory -> "EVCDJ750" contains the translation of EVCD file to J750 output format. Sub-directory -> "FLEXSTIL" contains the translation of FLEX file to STIL output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... This interface creates a Teradyne vector file for the Catalyst, FLEX, J750, J971 or J973 tester models. The current implementation supports the creation of a Catalyst timing file with timing for pins. This version also supports scan data structures in the Teradyne file. The invocation of this interface, and the optional [] parameters allowed are (some parameters apply only to specific tester models as indicated in the comments): TESTER_FORMAT teradyne [, -CATALYST | -FLEX+ | -J750 | -J971 | -J973] { tester model } [, -USE_TSET_NAMES] { use names instead of index - J750 only } [, -AUTO_GROUP] { uses algorithm to group signals } [, -ENCAPSULATE_TIMING] { timing encapsulated in C function } [, -MINIMIZE_SCAN ] { minimize length of scan data } [, SCANIN_DEFAULT = "state"] { any input 'X' is mapped to this } [, WR_TIMESET_FILE = "filename"] { Create pin timing in "filename" } [, MAX_SCAN_GROUP_SIZE = "nnn"] { Default nnn=500, for long scan chains } { sets max group size - Catalyst only } [, MAX_LINE_LENGTH = "nn"] { defines max length of line in tvf } { defaults to 99999 characters } [, TIME_STAMPS = "ON" | "OFF"] { enables/disables timestamps in file } { default is ON } [, TERMINATE = "HALT"] { default is no program termination } [, TIMESET_NAME = "name"] { default is ts1 - if not in OVF } [, REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat. } { Don't use with WGL or STIL input } [, PATTERN_NAME = "name"] { default "pattern_start" - J971/973,J750 } [, SOURCE_SELECT_GROUP = "name"] { default "default_src" - J971/973 only } [, PATGEN = "name"] { default "100Mhz" - J971/973 only } ; Pin timing sets will only be created for the Catalyst tester if the WR_TIMESET_FILE parameter is specified with a file name. The pin timing in this file is expressed in terms which are relative to the CYCLE time (period) of the vectors. The interface supports multiple timesets. For Catalyst scan chains, all chains are grouped into a single scan_template and are defined with scan lengths equal to the longest chain. During scan operations, scan chains which are shorter get padded appropriately. The -MINIMIZE_SCAN flag alters handling of scan data in the Teradyne Catalyst and J971/3 tester output formats. Normally, for these tester formats, all scan chains are normallized (padded) to the length of the longest scan chain for each scan operation being performed, regardless of whether or not the longest chain was actually being scanned each time. This flag causes the length of the scan data on all scan pins, for any given scan operation, to be only as long as the longest scan chain which is actually being scanned in that particular scan operation. For the J971/J973 formats, scan-in and scan-out pins are forced to 0 & L respectively in the scan setup vector. Also, this format generates up to 3 files: the vector file, a pin file and (if scan is present) a scan file. When specifying the TARGET_FILE name for this interface, specify a root name - e.g. "Pattern1". The interface will then automatically create the 3 files as "Pattern1.lvmadr", "Pattern1.pinadr" and "Pattern1.scanadr". The SOURCE_SELECT_GROUP parameter applies only to the J971 and J973 tester interface, as does the PATGEN parameter which is used in the timing file. PATTERN_NAME parameter applies to all Teradyne tester formats. The TERMINATE command can optionally be used to add a microcode at the beginning of the last vector line - this would usually be HALT. This output formatter assumes that the vector data it receives from the reader is cycle-data. Therefore, the WGL or STIL reader should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -cycle flag prevents the WGL & STIL readers from flattening-out timing when the file is being read. The -scan flag tells the readers to maintain the scan data separately, i.e. do not flatten it out. Since the TERADYNE format supports a scan data structure, we may not want the readers to flatten it out. If the input vectors are coming from a print-on-change format, then vtran would need to collapse them to cycle-data using one of the ALIGN commands in the PROC_BLOCK. The examples include several WGL translations, a STIL translation, as well as EVCD, VCD and TSSI translations. Note that for STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is to be scan data translated. Also, the number of scan bits specified in a single SHIFT operation in a STIL file should not exceed the length of the scan chain. An example command file for an WGL -> CATALYST translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > CATALYST # # Original File: "exp1.wgl" # # Target File: "exp1.catl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'CATALYST'#### } state_trans outputs '1'->'H', '0'->'L'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { ##### This puts the vertical pin names in as comments#### } rename_bus_pins $bus_$vec; { #### Flatten Busses #### } simulator teradyne -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp1.catl"; {#### OUTPUT VECTOR FILE ####} end; ################################################################################ Beginning with vtran release 7.0, a number of the tester output interface options include a canned reader which is specifically designed to read the vtran-generated tester files and translate these directly to a Verilog or VHDL testbench (or actually any flat format). These canned readers are "Read-Back" modules which provide a direct way to verify the tester files, thru testbench re-simulation, prior to trying them on the tester. Note that these Read-Back modules support only the subset of the tester syntax used by vtran when generating the test programs and only support a flat translation, thus they are not intended for use as a general-purpose translation tool for the tester languages. The Teradyne tester canned reader optionally will generate cyclized output formats. This reader still supports only the subset of tester syntax used by vtran when generating the test programs. This tester canned reader has several options that allow the user to control whether scan vectors, single-vector repeats, and loops are retained or flattened in the output format, when cycle-based output is selected. The vtran command files for using the canned reader module to create cycle-based output formats are typically quite simple, as illustrated below. The vtran command files for using the Read-Back module to create a verification testbench are typically quite simple, as illustrated below. An example command file for a J750->Verilog testbench translation might look like: ovf_block begin tabular_format J750; orig_file = "exp1.tp"; aux_file = "exp1.tim"; end proc_block begin state_trans 'H'->'1', 'L'->'0'; disable_vector_filter; end tvf_block begin target_file = "exp1.v"; simulator verilog_tb -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "designX", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; end; end The reader takes 2 files: the ORIG_FILE is the J750 test vector file, and the AUX_FILE is the timing file generated by vtran during translation. The J750 reader requires that both files be available. An example command file for a Catalyst->Verilog testbench translation might look like: ovf_block begin tabular_format Catalyst; orig_file = "exp1.tp"; aux_file = "exp1.tim"; end proc_block begin state_trans 'H'->'1', 'L'->'0'; disable_vector_filter; end tvf_block begin target_file = "exp1.v"; simulator verilog_tb -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "designX", INSTANCE_NAME = "scratch", timescale = "1ps/1ps" ; end; end The reader takes 2 files: the ORIG_FILE is the Catalyst test vector file, and the AUX_FILE is the timing file generated by vtran during translation. The Catalyst reader requires that both files be available. An example command file for a J973->Verilog testbench translation might look like: OVF_BLOCK BEGIN orig_file = "exp1.lvmadr"; aux_file = "exp1.waveadr"; TABULAR_FORMAT J973; END; PROC_BLOCK BEGIN state_trans 'L'->'0', 'H'->'1', 'M'->'Z'; state_trans inputs 'X'->'Z'; disable_vector_filter; END; TVF_BLOCK BEGIN simulator verilog_tb ; target_file = "exp1.v"; END; END; The reader takes 2 files: the ORIG_FILE is the J973 test vector file, and the AUX_FILE is the timing file generated by vtran during translation. The J973 reader requires that both files be available. The example translations below demonstrate how to generate the basic cycle-based output and how to generate unflattened scan output (for the tester formats that support unflattened scan). The example translations in the sub-directories can be run by typing: vtran cycn.vtran or vtran scann.vtran where n=1,2................... Teradyne J750 Cycle-based Output: ................................. The J750 Reader optionally will generate cycle-based timing and vectors. To select this feature, include the flag "-cycle" with the tabular_format command in the OVF_BLOCK of the Vtran command file. If an "import" statement is in the J750 vector file, the J750 timeset names may be used in the output files. If there is no "import" statement, the timeset names will be of the form TS, where is a timeset number starting at 1. The Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that cycle-based output must be selected to enable the Scan option. The Reader, by default, will not flatten loops and repeated vectors if cycle-based output is selected. To disable this feature, include the flag "-expand_loops" and/or "-expand_reps" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that if cycle-based output is not selected, loops and repeated vectors will be flattened. The Reader optionally will read the BASIC_TIMING and BASIC_TIMING_FORMULAS timing files generated by Vtran for the J750+ Target. To select one of these features, include the flag "-basic_timing" or "basic_timing_formulas" with the tabular_format command in the OVF_BLOCK of the Vtran command file. The basic_timing files do not enable the Reader to reliably distinguish between pure output signals and bidirectional signals. The user optionally may include the INPUTS, OUTPUTS, and BIDIRECTS fields in the OVF_BLOCK of the command file to specify the direction of some or all of the signals. If these fields are not included in the command file, the Reader will treat a signal as a pure output if its drive time is zero, and will treat the signal as a bidirectional if its drive time is non-zero. This may cause incorrect values in the Target file, if the Reader treats a signal as a pure output when it actually is a bidirectional signal. [In the future, the Reader might be changed to make an extra pass over the J750 vectors, to use the vector values to try to distinguish pure output signals from bidirectional signals. But this also would incorrectly identify a bidirectional signal as a pure output, if the signal only has output values in the ovf file.] Example 1: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format J750 -cycle; {#### INPUT FORMAT ####} end; In this case, Vtran will read J750 source files with the default timing format, and create cycle-based data for the Target files. Loops and repeated vectors will be available for inclusion in the Target files. Example 2: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format J750 -cycle -scan -expand_loops; {#### INPUT FORMAT ####} end; In this case, Vtran will read J750 source files with the default timing format, and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files, as will repeated vectors. Loops will be flattened. Example 3: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format J750 -cycle -scan -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; In this case, Vtran will read J750 source files with the default timing format, and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files. Loops and repeated vectors will be flattened. Example 4: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format J750 -basic_timing; {#### INPUT FORMAT ####} end; In this case, Vtran will read J750 source files and generate a flattened event stream for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran J750+ target basic_timing option. Example 5: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format J750 -basic_timing_formulas; end; In this case, Vtran will read J750 source files and generate a flattened event stream for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran J750+ target basic_timing_formulas option. Example 6: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format J750 -basic_timing -cycle; end; In this case, Vtran will read J750 source files and create cycle-based data for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran J750+ target basic_timing option. An example command file for a J750->STIL translation might look like: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format J750 -cycle -scan ; end; proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; tvf_block begin; resolution = 0.1; simulator stil; target_file "exp1.stil"; end; Teradyne J750+/FLEX Cycle-based Output: ....................................... The FLEX and J750+ Readers optionally will generate cycle-based timing and vectors. To select this feature, include the flag "-cycle" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Using these readers without the -cycle flag will result in the files being flattened to an event stream - this would be the option used when generating a testbench (Verilog or VHDL) for program verification. If an "import" statement is in the FLEX or J750+ vector file, the FLEX or J750+ timeset names may be used in the output files. If there is no import" statement, the timeset names will be of the form TS, where is a timeset number starting at 1. The J750+ Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that cycle-based output must be selected to enable the Scan option. The FLEX Reader does not support unflattened Scan. The J750+ Reader, by default, will not flatten loops and repeated vectors if cycle-based output is selected. The FLEX Reader, by default, will not flatten repeated vectors if cycle-based output is selected. To disable these features, include the flag "-expand_loops" and/or "-expand_reps" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that if cycle-based output is not selected, loops and repeated vectors will be flattened by both Readers. The Readers optionally will read the BASIC_TIMING and BASIC_TIMING_FORMULAS timing files generated by Vtran for the J750+ and FLEX Targets. To select one of these features, include the flag "-basic_timing" or "basic_timing_formulas" with the tabular_format command in the OVF_BLOCK of the Vtran command file. The timing file name is specified with the aux_file command in the OVF_BLOCK of the Vtran command file. The basic_timing files do not enable the Reader to reliably distinguish between pure output signals and bidirectional signals. The user optionally may include the INPUTS, OUTPUTS, and BIDIRECTS fields in the OVF_BLOCK of the command file to specify the direction of some or all of the signals. If these fields are not included in the command file, the Reader will treat a signal as a pure output if its drive time is zero, and will treat the signal as a bidirectional if its drive time is non-zero. This may cause incorrect values in the Target file, if the Reader treats a signal as a pure output when it actually is a bidirectional signal. [In the future, the Reader might be changed to make an extra pass over the vectors, to use the vector values to try to distinguish pure output signals from bidirectional signals. But this also would incorrectly identify a bidirectional signal as a pure output, if the signal only has output values in the ovf file.] The standard timing format for FLEX and J750+ uses two files. A file name prefix is specified with the aux_file command in the OVF_BLOCK of the Vtran command file. The suffix "_tsets.txt" is appended to this prefix to find the timesets file. The suffix "_esets.txt" is appended to this prefix to find the edgesets file. These files are similar to the BASIC_TIMING files. Therefore, the user optionally may include the INPUTS, OUTPUTS, and BIDIRECTS fields in the OVF_BLOCK of the command file to specify the direction of some or all of the signals, as described above. The Readers support an optional AC Specs file, and references in the timing file(s) to variables defined in the AC Specs file. Both the AC Specs file and the timing file(s) can use expressions in the time fields. This feature is available both with the standard and the basic timing formats. A file name prefix is specified with the aux_file command in the OVF_BLOCK of the Vtran command file. The suffix "_acspecs.txt" is appended to this prefix to find the AC Specs file. The timing in the target file will consist of constant time values; the variable definitions and references will not be preserved in the Vtran output files. The user may use Vtran commands to specify a Selector and/or a Category name. The Selector and Category are used to choose one of several possible values for the variables found in the timing file(s). If the Selector is not specified by the user, "Typ" is the default. If the Category is not specified by the user, the first Category found in the AC Specs file is used. The Selector and Category are defined with the "-specs_selector" and "-specs_category" flags in the tabular_format command in the OVF_BLOCK of the Vtran command file. See examples below for the usage of these flags. The Readers support an optional pinmap file, and references in the timing file(s) to groups defined in the pinmap file. This feature is available both with the standard and the basic timing formats. A file name prefix is specified with the aux_file command in the OVF_BLOCK of the Vtran command file. The suffix "_pinmap.txt" is appended to this prefix to find the pinmap file. Example 1: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files with the default timing format, and create cycle-based data for the Target files. Repeated vectors will be available for inclusion in the Target files. The timing is defined in files exp1.tim_tsets.txt and exp1.tim_esets.txt. Example 2: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle -expand_reps; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files with the default timing format, and create cycle-based data for the Target files. Repeated vectors will be flattened. The timing is defined in files exp1.tim_tsets.txt and exp1.tim_esets.txt. Example 3: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format J750+ -cycle -scan -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; In this case, Vtran will read J750+ source files with the default timing format, and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files. Loops and repeated vectors will be flattened. The timing is defined in files exp1.tim_tsets.txt and exp1.tim_esets.txt. Example 4: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -basic_timing; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files and generate a flattened event stream for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran FLEX+ target basic_timing option. Example 5: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -basic_timing_formulas; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files and generate a flattened event stream for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran FLEX+ target basic_timing_formulas option. Example 6: ovf_block begin; orig_file "exp1.tp"; {#### INPUT VECTOR FILE ####} aux_file "exp1.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -basic_timing -cycle; {#### INPUT FORMAT ####} end; In this case, Vtran will read FLEX source files and create cycle-based data for the Target files. The timing defined in the file exp1.tim is in the format generated with the Vtran J750+ target basic_timing option. Example 7: ovf_block begin; orig_file "specs3.flex"; {#### INPUT VECTOR FILE ####} aux_file "specs3.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle -SPECS_CATEGORY=Cat5 -SPECS_SELECTOR=Min ; {#### INPUT FORMAT ####} end; In this case, Vtran will use the AC Specs file specs3.tim_acspecs.txt, in conjunction with the FLEX timing files specs3.tim_tsets.txt and specs3.tim_esets.txt, to create timing for the output file. The Min values in Category Cat5 will be used to resolve references to variables. Example 8: ovf_block begin; orig_file "specs3.flex"; {#### INPUT VECTOR FILE ####} aux_file "specs3.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle -basic_timing; {#### INPUT FORMAT ####} end; In this case, Vtran will use the AC Specs file specs3.tim_acspecs.txt, if it exists, in conjunction with the basic timing file specs3.tim_basic_ts.txt, to create timing for the output file. The default Typ values in the first Category will be used to resolve references to variables. Example 9: ovf_block begin; orig_file "specs2.flex"; {#### INPUT VECTOR FILE ####} aux_file "specs2.tim"; {#### AUX TIMING FILE ####} tabular_format FLEX -cycle ; {#### INPUT FORMAT ####} end; In this case, Vtran will use the pinmap file specs2.tim_pinmap.txt to resolve signal group references in the FLEX timing files specs2.tim_tsets.txt and specs2.tim_esets.txt files. Teradyne Catalyst Cycle-based Output: ..................................... The Catalyst Reader optionally will generate cycle-based timing and vectors. To select this feature, include the flag "-cycle" with the tabular_format command in the OVF_BLOCK of the Vtran command file. The Reader optionally will generate unflattened Scan data. To select this feature, include the flags "-cycle -scan" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that cycle-based output must be selected to enable the Scan option. The Reader, by default, will not flatten loops and repeated vectors if cycle-based output is selected. To disable this feature, include the flag "-expand_loops" and/or "-expand_reps" with the tabular_format command in the OVF_BLOCK of the Vtran command file. Note that if cycle-based output is not selected, loops and repeated vectors will be flattened. Example 1: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format catalyst -cycle; end; In this case, Vtran will read the Catalyst source file and create cycle-based data for the Target files. Loops and repeated vectors will be available for inclusion in the Target files. Example 2: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format catalyst -cycle -scan -expand_loops; end; In this case, Vtran will read the Catalyst source file and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files, as will repeated vectors. Loops will be flattened. Example 3: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format catalyst -cycle -scan -expand_loops -expand_reps; end; In this case, Vtran will read the Catalyst source file and create cycle-based data for the Target files. Scan chain data and Scan vectors will be available for inclusion in the Target files. Loops and repeated vectors will be flattened. An example command file for a Catalyst->STIL translation might look like: ovf_block begin; orig_file "exp1.tp"; aux_file "exp1.tim"; tabular_format catalyst -cycle -scan ; end; proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; tvf_block begin; resolution = 0.1; { rename_bus_pins $bus_$vec; } simulator stil scanin_condition = "0"; target_file "exp1.stil"; end; e features, include the flag "-basic_timing" or "basic_timing_formulas" with the tabular_format command in the OVF_BLOCK of the Vtran command file. The timing file name is specified with the aux_file command in the OVF_BLOCK of the Vtran command file. The basic_timing files do nINTERFACES/TERADYNE/VCDJ973T/000075500001440000012000000000001103104161000156445ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/VCDJ973T/exp2.vtran000064400001440000012000000156521103104161000176070ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD(Print-on-change) < to > J973 # # Original File: "exp1.vcd" # # Target File: "exp2.j973 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ############################################################ The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. ##############################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,,S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS ,,S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,,L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,,T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,,S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; INPUTS ,,SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,,S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into J973 format # #======================================================================# } PROC_BLOCK BEGIN { #### state character translations for 'VCD'->'J973'#### } state_trans 'z'->'Z'; state_trans pure_inputs 'X'->'0', 'x'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X' ; { ########################################################### In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. ##############################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { ################################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the Teradyne file needs to be in cycle-based format. Now we can define some timing for the Teradyne file since the VCD file does not contain this info separately. #####################################################################} Include "../../DATA/exp1A.tcyc" END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN SIMULATOR TERADYNE {#### OUTPUT VECTOR FILE ####} -J973, -AUTO_GROUP, MAX_LINE_LENGTH = "80", REPEAT_THRESHOLD = "5", TIME_STAMPS = "OFF", WR_TIMESET_FILE = "exp2.tim", ; TARGET_FILE "exp2.j973"; {#### OUTPUT FORMAT ####} END; S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , INTERFACES/TERADYNE/VCDJ973T/exp1.vtran000064400001440000012000000176111103104161000176030ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD(Print-on-change) < to > J973 # # Original File: "exp1A.vcd" # # Target File: "exp1.j973 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ############################################################ The VCD file does not contain signal direction information, so we must specify all signals and their directions. The order will define order in output file, double commas (,,) put space in front of signal. ##############################################################} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS ,,S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS ,,S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS ,,L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS ,,T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS ,,S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; INPUTS ,,SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS ,,S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS ,,TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS ,,EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into J973 format # #======================================================================# } PROC_BLOCK BEGIN { #### state character translations for 'VCD'->'J973'#### } state_trans 'z'->'Z'; state_trans pure_inputs 'X'->'0', 'x'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X' ; { ########################################################### In the VCD file, input (force) vector data and output (sense) data for bidirectional signals is not distinguished or separated. Therefore, we must separate the input from output data somehow. Using control signal states is the most common method. ##############################################################} BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { ############################################################### The vector data in the VCD file is in a print-on-change format. The vector data for the Teradyne file needs to be in cycle-based format. We therefore must use one of the ALIGN processes to collapse the data from print-on-change to cycle-based. Here we use ALIGN_TO_CYCLE for this, strobing all pure input signals and all output signals at 49 nS into the 50 nS cycle, but strobing bidirectional inputs at 10 nS into the cycle ###################################################################} CYCLE = 50; ALIGN_TO_CYCLE 50 PURE_INPUTS @ 49, BIDIR_INPUTS @ 10, ALL_OUTPUTS @ 49 ; { ################################################################### Now we can define some timing for the Teradyne file since the VCD file does not contain this info separately and we just removed all pin timing with the ALIGN_TO_CYCLE process above #####################################################################} ADD_PIN HECS_CLK = 1; {#### add clock pin - not necessary if already in data #### } PINTYPE NRZ * @ 5; {#### drive all inputs at 5 #### } PINTYPE STB * @ 45; { #### strobe all outputs at 45#### } PINTYPE RZ HECS_CLK @ 20, 30; { ####clock pin behavior ####} END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN SIMULATOR TERADYNE {#### OUTPUT VECTOR FILE ####} -J973, -AUTO_GROUP, MAX_LINE_LENGTH = "80", REPEAT_THRESHOLD = "5", TIME_STAMPS = "OFF", WR_TIMESET_FILE = "exp1.tim", ; TARGET_FILE "exp1.j973"; {#### OUTPUT FORMAT ####} END; o we must specify all signals and their directions. The order will define order in output file, double INTERFACES/TERADYNE/STILCATAL/000075500001440000012000000000001103104161000160475ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/STILCATAL/exp1.vtran000064400001440000012000000051271103104161000200050ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp1.catl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'CATALYST' #### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format teradyne {#### OUTPUT FORMAT ####} -CATALYST, -AUTO_GROUP, WR_TIMESET_FILE = "exp1.tms" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp1.catl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/STILCATAL/exp2.vtran000064400001440000012000000047631103104161000200130ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp2.catl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'CATALYST' #### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format teradyne {#### OUTPUT FORMAT ####} -CATALYST, -AUTO_GROUP, WR_TIMESET_FILE = "exp2.tms" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp2.catl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/STILCATAL/exp3.vtran000064400001440000012000000047701103104161000200120ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp3.catl " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'CATALYST' #### } state_trans 'P'->'^'; state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format teradyne {#### OUTPUT FORMAT ####} -CATALYST, -AUTO_GROUP, WR_TIMESET_FILE = "exp3.tms" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp3.catl"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/EVCDJ750/000075500001440000012000000000001103104161000156165ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/EVCDJ750/exp1.vtran000064400001440000012000000100551133466624400175760ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > J750 # # Original File: "exp1.evcd" # # Target File: "exp1.j750 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into J750 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'J750' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1', 'Z'->'X', 'T'->'X', 'x'->'X', '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'0', 'f'->'X', 'F'->'X'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'X', 'F'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR TERADYNE {#### OUTPUT FORMAT ####} -J750, -AUTO_GROUP, MAX_LINE_LENGTH = "800", TIME_STAMPS = "ON", WR_TIMESET_FILE = "exp1.tim", ; target_file "exp1.j750"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/TERADYNE/EVCDJ750/exp2.vtran000064400001440000012000000074621133466626700176140ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > J750 # # Original File: "exp1.evcd" # # Target File: "exp2.j750 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into J750 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'J750' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1', 'Z'->'X', 'T'->'X', 'x'->'X', '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'0', 'f'->'X', 'F'->'X'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'X', 'F'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR TERADYNE {#### OUTPUT FORMAT ####} -J750, -AUTO_GROUP, MAX_LINE_LENGTH = "800", TIME_STAMPS = "ON", WR_TIMESET_FILE = "exp2.tim", ; target_file "exp2.j750"; {#### OUTPUT VECTOR FILE ####} end end evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states INTERFACES/TERADYNE/WGLCATAL/000075500001440000012000000000001127164315000157425ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/WGLCATAL/exp1.vtran000064400001440000012000000046121127142105500176740ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > CATALYST # # Original File: "exp1.wgl" # # Target File: "exp2.catl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'CATALYST'#### } state_trans outputs '1'->'H', '0'->'L'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { ##### This puts the vertical pin names in as comments#### } rename_bus_pins $bus_$vec; { #### Flatten Busses #### } simulator teradyne -catalyst -auto_group , {#### OUTPUT FORMAT ####} wr_timeset_file = "exp1.tim" ; target_file "exp1.catl"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLCATAL/exp2.vtran000064400001440000012000000045471114307727000177100ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > CATALYST # # Original File: "exp1.wgl" # # Target File: "exp2.catl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'CATALYST'#### } state_trans outputs '1'->'H', '0'->'L'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { ##### This puts the vertical pin names in as comments#### } rename_bus_pins $bus_$vec; { #### Flatten Busses #### } simulator teradyne -catalyst -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp2.catl"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLCATAL/exp4.vtran000064400001440000012000000050641114307735000177040ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > CATALYST # # Original File: "exp4.wgl" # # Target File: "exp4.catl " # # Command File: "exp4.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "exp4.lsim"; {#### INPUT VECTOR FILE ####} tabular_format lsim ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'CATALYST'#### } state_trans 'x'->'X', '?'->'X', 'z'->'Z'; state_trans inputs 'l'->'0', 'h'->'1', 'H'->'1', 'L'->'0'; state_trans outputs 'l'->'L', 'h'->'H', '1'->'H', '0'->'L'; cycle = 488; align_to_step 488 487; { #### Collapse to cycle data #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments ####} rename_bus_pins $bus_$vec; { #### Flatten Busses #### } tester_format teradyne -catalyst -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp4.catl"; {#### OUTPUT VECTOR FILE ####} end; {#### INPUT VECTOR FILE ####} tabular_format lsim ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================#INTERFACES/TERADYNE/WGLCATAL/exp3.vtran000064400001440000012000000045551114307732100177050ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > CATALYST # # Original File: "exp1.wgl" # # Target File: "exp3.catl " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into CATALYST format # #======================================================================# } proc_block begin; { #### state character translations for 'WGL'->'CATALYST'#### } state_trans outputs '1'->'H', '0'->'L'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { ##### This puts the vertical pin names in as comments#### } rename_bus_pins $bus_$vec; { #### Flatten Busses #### } simulator teradyne -catalyst -auto_group ; {#### OUTPUT FORMAT ####} target_file "exp3.catl"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLCATAL/exp4.lsim000064400001440000012000001133011103104161000174720ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp4.lsim" # # Original File: "exp4.lsim" # # Target File: "exp4.catl " # # Command File: "exp4.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# CODEFILE UNITS nS {#### INPUT/OUTPUT PIN DESCRIPTION ####} INPUTS RES,FSC,DD,TS0,TS1,TS2,SEL24,IO1(to=40),IO2(to=40), I1,REXT,ID_H,ID_M,ID_L; OUTPUTS O1(to=max),DU(to=max),IO1(to=max),IO2(to=max); CODING(ROM) # !initialize @0 <1110000XXXXXXX >XX..; # !clockdef sysclk_DCL 488 # !subclock sysclk_DCL DCL 0.00%,l 0.00%,t 50.00%,t @488 <1010000XXXXXXX >XX..; @976 <1000000ZZXXXXX >XXLH; @1464 <1010000XXXXXXX >XH..; @1952 <1000000XXXXXXX >XL..; @2440 <1010000XXXXXXX >XH..; @2928 <1000000XXXXXXX >XL..; @3416 <0010000XXXXXXX >XX..; @3904 <0010000XXXXXXX >XX..; @4392 <0010000XXXXXXX >XX..; @4880 <0000000ZZXXXXX >XXHL; @5368 <0010000XXXXXXX >XX..; @5856 <0000000XXXXXXX >XX..; @6344 <0010000XXXXXXX >XX..; @6832 <0000000XXXXXXX >XX..; @7320 <0010000XXXXXXX >XX..; @7808 <0010000XXXXXXX >XX..; @8296 <0010000XXXXXXX >XX..; @8784 <0010000XXXXXXX >XX..; @9272 <0010000XXXXXXX >XX..; @9760 <0010000XXXXXXX >XX..; @10248 <0010000XXXXXXX >XX..; @10736 <0010000XXXXXXX >XX..; @11224 <0010000XXXXXXX >XX..; @11712 <0000000XXXXXXX >XX..; @12200 <0000000XXXXXXX >XX..; @12688 <0000000XXXXXXX >XX..; @13176 <0000000XXXXXXX >XX..; @13664 <0000000XXXXXXX >XX..; @14152 <0000000XXXXXXX >XX..; @14640 <0010000XXXXXXX >XX..; @15128 <0010000XXXXXXX >XX..; @15616 <00h0000XXXXXXX >XX..; @16104 <00h0000XXXXXXX >XX..; @16592 <00h0000XXXXXXX >XX..; @17080 <00h0000XXXXXXX >XX..; @17568 <00h0000XXXXXXX >XX..; @18056 <00h0000XXXXXXX >XX..; @18544 <00h0000XXXXXXX >XX..; @19032 <00h0000XXXXXXX >XX..; @19520 <00h0000XXXXXXX >XX..; @20008 <00h0000XXXXXXX >XX..; @20496 <00h0000XXXXXXX >XX..; @20984 <00h0000XXXXXXX >XX..; @21472 <00h0000XXXXXXX >XX..; @21960 <00h0000XXXXXXX >XX..; @22448 <00h0000XXXXXXX >XX..; @22936 <00h0000XXXXXXX >XX..; @23424 <00h0000XXXXXXX >XX..; @23912 <00h0000XXXXXXX >XX..; @24400 <00h0000XXXXXXX >XX..; @24888 <00h0000XXXXXXX >XX..; @25376 <00h0000XXXXXXX >XX..; @25864 <00h0000XXXXXXX >XX..; @26352 <00h0000XXXXXXX >XX..; @26840 <00h0000XXXXXXX >XX..; @27328 <00h0000XXXXXXX >XX..; @27816 <00h0000XXXXXXX >XX..; @28304 <00h0000XXXXXXX >XX..; @28792 <00h0000XXXXXXX >XX..; @29280 <00h0000XXXXXXX >XX..; @29768 <00h0000XXXXXXX >XX..; @30256 <00h0000XXXXXXX >XX..; @30744 <00h0000XXXXXXX >XX..; @31232 <00h0000XXXXXXX >XX..; @31720 <00h0000XXXXXXX >XX..; @32208 <00h0000XXXXXXX >XX..; @32696 <00h0000XXXXXXX >XX..; @33184 <00h0000XXXXXXX >XX..; @33672 <00h0000XXXXXXX >XX..; @34160 <00h0000XXXXXXX >XX..; @34648 <00h0000XXXXXXX >XX..; @35136 <00h0000XXXXXXX >XX..; @35624 <00h0000XXXXXXX >XX..; @36112 <00h0000XXXXXXX >XX..; @36600 <00h0000XXXXXXX >XX..; @37088 <00h0000XXXXXXX >XX..; @37576 <00h0000XXXXXXX >XX..; @38064 <00h0000XXXXXXX >XX..; @38552 <00h0000XXXXXXX >XX..; @39040 <00h0000XXXXXXX >XX..; @39528 <00h0000XXXXXXX >XX..; @40016 <00h0000XXXXXXX >XX..; @40504 <00h0000XXXXXXX >XX..; @40992 <00h0000XXXXXXX >XX..; @41480 <00h0000XXXXXXX >XX..; @41968 <00h0000XXXXXXX >XX..; @42456 <00h0000XXXXXXX >XX..; @42944 <00h0000XXXXXXX >XX..; @43432 <00h0000XXXXXXX >XX..; @43920 <00h0000XXXXXXX >XX..; @44408 <00h0000XXXXXXX >XX..; @44896 <00h0000XXXXXXX >XX..; @45384 <00h0000XXXXXXX >XX..; @45872 <00h0000XXXXXXX >XX..; @46360 <00h0000XXXXXXX >XX..; @46848 <00h0000XXXXXXX >XX..; @47336 <00h0000XXXXXXX >XX..; @47824 <00h0000XXXXXXX >XX..; @48312 <00h0000XXXXXXX >XX..; @48800 <00h0000XXXXXXX >XX..; @49288 <00h0000XXXXXXX >XX..; @49776 <00h0000XXXXXXX >XX..; @50264 <00h0000XXXXXXX >XX..; @50752 <00h0000XXXXXXX >XX..; @51240 <00h0000XXXXXXX >XX..; @51728 <00h0000XXXXXXX >XX..; @52216 <00h0000XXXXXXX >XX..; @52704 <00h0000XXXXXXX >XX..; @53192 <00h0000XXXXXXX >XX..; @53680 <00h0000XXXXXXX >XX..; @54168 <00h0000XXXXXXX >XX..; @54656 <00h0000XXXXXXX >XX..; @55144 <00h0000XXXXXXX >XX..; @55632 <00h0000XXXXXXX >XX..; @56120 <00h0000XXXXXXX >XX..; @56608 <00h0000XXXXXXX >XX..; @57096 <00h0000XXXXXXX >XX..; @57584 <00h0000XXXXXXX >XX..; @58072 <00h0000XXXXXXX >XX..; @58560 <00h0000XXXXXXX >XX..; @59048 <00h0000XXXXXXX >XX..; @59536 <00h0000XXXXXXX >XX..; @60024 <00h0000XXXXXXX >XX..; @60512 <00h0000XXXXXXX >XX..; @61000 <00h0000XXXXXXX >XX..; @61488 <00h0000XXXXXXX >XX..; @61976 <00h0000XXXXXXX >XX..; @62464 <00h0000XXXXXXX >XX..; @62952 <00h0000XXXXXXX >XX..; @63440 <00h0000XXXXXXX >XX..; @63928 <00h0000XXXXXXX >XX..; @64416 <00h0000XXXXXXX >XX..; @64904 <00h0000XXXXXXX >XX..; @65392 <00h0000XXXXXXX >XX..; @65880 <00h0000XXXXXXX >XX..; @66368 <00h0000XXXXXXX >XX..; @66856 <00h0000XXXXXXX >XX..; @67344 <00h0000XXXXXXX >XX..; @67832 <00h0000XXXXXXX >XX..; @68320 <00h0000XXXXXXX >XX..; @68808 <00h0000XXXXXXX >XX..; @69296 <00h0000XXXXXXX >XX..; @69784 <00h0000XXXXXXX >XX..; @70272 <00h0000XXXXXXX >XX..; @70760 <00h0000XXXXXXX >XX..; @71248 <00h0000XXXXXXX >XX..; @71736 <00h0000XXXXXXX >XX..; @72224 <00h0000XXXXXXX >XX..; @72712 <00h0000XXXXXXX >XX..; @73200 <00h0000XXXXXXX >XX..; @73688 <00h0000XXXXXXX >XX..; @74176 <00h0000XXXXXXX >XX..; @74664 <00h0000XXXXXXX >XX..; @75152 <00h0000XXXXXXX >XX..; @75640 <00h0000XXXXXXX >XX..; @76128 <00h0000XXXXXXX >XX..; @76616 <00h0000XXXXXXX >XX..; @77104 <00h0000XXXXXXX >XX..; @77592 <00h0000XXXXXXX >XX..; @78080 <00h0000XXXXXXX >XX..; @78568 <00h0000XXXXXXX >XX..; @79056 <00h0000XXXXXXX >XX..; @79544 <00h0000XXXXXXX >XX..; @80032 <00h0000XXXXXXX >XX..; @80520 <00h0000XXXXXXX >XX..; @81008 <00h0000XXXXXXX >XX..; @81496 <00h0000XXXXXXX >XX..; @81984 <00h0000XXXXXXX >XX..; @82472 <00h0000XXXXXXX >XX..; @82960 <00h0000XXXXXXX >XX..; @83448 <00h0000XXXXXXX >XX..; @83936 <00h0000XXXXXXX >XX..; @84424 <00h0000XXXXXXX >XX..; @84912 <00h0000XXXXXXX >XX..; @85400 <00h0000XXXXXXX >XX..; @85888 <00h0000XXXXXXX >XX..; @86376 <00h0000XXXXXXX >XX..; @86864 <00h0000XXXXXXX >XX..; @87352 <00h0000XXXXXXX >XX..; @87840 <00h0000XXXXXXX >XX..; @88328 <00h0000XXXXXXX >XX..; @88816 <00h0000XXXXXXX >XX..; @89304 <00h0000XXXXXXX >XX..; @89792 <00h0000XXXXXXX >XX..; @90280 <00h0000XXXXXXX >XX..; @90768 <00h0000XXXXXXX >XX..; @91256 <00h0000XXXXXXX >XX..; @91744 <00h0000XXXXXXX >XX..; @92232 <00h0000XXXXXXX >XX..; @92720 <00h0000XXXXXXX >XX..; @93208 <00h0000XXXXXXX >XX..; @93696 <00h0000XXXXXXX >XX..; @94184 <00h0000XXXXXXX >XX..; @94672 <00h0000XXXXXXX >XX..; @95160 <00h0000XXXXXXX >XX..; @95648 <00h0000XXXXXXX >XX..; @96136 <00h0000XXXXXXX >XX..; @96624 <00h0000XXXXXXX >XX..; @97112 <00h0000XXXXXXX >XX..; @97600 <00h0000XXXXXXX >XX..; @98088 <00h0000XXXXXXX >XX..; @98576 <00h0000XXXXXXX >XX..; @99064 <00h0000XXXXXXX >XX..; @99552 <00h0000XXXXXXX >XX..; @100040 <00h0000XXXXXXX >XX..; @100528 <00h0000XXXXXXX >XX..; @101016 <00h0000XXXXXXX >XX..; @101504 <00h0000XXXXXXX >XX..; @101992 <00h0000XXXXXXX >XX..; @102480 <00h0000XXXXXXX >XX..; @102968 <00h0000XXXXXXX >XX..; @103456 <00h0000XXXXXXX >XX..; @103944 <00h0000XXXXXXX >XX..; @104432 <00h0000XXXXXXX >XX..; @104920 <00h0000XXXXXXX >XX..; @105408 <00h0000XXXXXXX >XX..; @105896 <00h0000XXXXXXX >XX..; @106384 <00h0000XXXXXXX >XX..; @106872 <00h0000XXXXXXX >XX..; @107360 <00h0000XXXXXXX >XX..; @107848 <00h0000XXXXXXX >XX..; @108336 <00h0000XXXXXXX >XX..; @108824 <00h0000XXXXXXX >XX..; @109312 <00h0000XXXXXXX >XX..; @109800 <00h0000XXXXXXX >XX..; @110288 <00h0000XXXXXXX >XX..; @110776 <00h0000XXXXXXX >XX..; @111264 <00h0000XXXXXXX >XX..; @111752 <00h0000XXXXXXX >XX..; @112240 <00h0000XXXXXXX >XX..; @112728 <00h0000XXXXXXX >XX..; @113216 <00h0000XXXXXXX >XX..; @113704 <00h0000XXXXXXX >XX..; @114192 <00h0000XXXXXXX >XX..; @114680 <00h0000XXXXXXX >XX..; @115168 <00h0000XXXXXXX >XX..; @115656 <00h0000XXXXXXX >XX..; @116144 <00h0000XXXXXXX >XX..; @116632 <00h0000XXXXXXX >XX..; @117120 <00h0000XXXXXXX >XX..; @117608 <00h0000XXXXXXX >XX..; @118096 <00h0000XXXXXXX >XX..; @118584 <00h0000XXXXXXX >XX..; @119072 <00h0000XXXXXXX >XX..; @119560 <00h0000XXXXXXX >XX..; @120048 <00h0000XXXXXXX >XX..; @120536 <00h0000XXXXXXX >XX..; @121024 <00h0000XXXXXXX >XX..; @121512 <00h0000XXXXXXX >XX..; @122000 <00h0000XXXXXXX >XX..; @122488 <00h0000XXXXXXX >XX..; @122976 <00h0000XXXXXXX >XX..; @123464 <00h0000XXXXXXX >XX..; @123952 <00h0000XXXXXXX >XX..; @124440 <00h0000XXXXXXX >XX..; @124928 <0110000XXXXXXX >XX..; @125416 <0000000XXXXXXX >XX..; @125904 <0010000XXXXXXX >XX..; @126392 <0000000XXXXXXX >XX..; @126880 <0000000XXXXXXX >XX..; @127368 <0010000XXXXXXX >XX..; @127856 <0010000XXXXXXX >XX..; @128344 <0010000XXXXXXX >XX..; @128832 <0010000XXXXXXX >XX..; @129320 <0010000XXXXXXX >XX..; @129808 <0000000XXXXXXX >XX..; @130296 <0010000XXXXXXX >XX..; @130784 <0000000XXXXXXX >XX..; @131272 <0010000XXXXXXX >XX..; @131760 <0000000XXXXXXX >XX..; @132248 <0010000XXXXXXX >XX..; @132736 <0010000XXXXXXX >XX..; @133224 <0010000XXXXXXX >XX..; @133712 <0010000XXXXXXX >XX..; @134200 <0010000XXXXXXX >XX..; @134688 <0010000XXXXXXX >XX..; @135176 <0010000XXXXXXX >XX..; @135664 <0010000XXXXXXX >XX..; @136152 <0010000XXXXXXX >XX..; @136640 <0000000XXXXXXX >XX..; @137128 <0000000XXXXXXX >XX..; @137616 <0000000XXXXXXX >XX..; @138104 <0000000XXXXXXX >XX..; @138592 <0000000XXXXXXX >XX..; @139080 <0000000XXXXXXX >XX..; @139568 <0010000XXXXXXX >XX..; @140056 <0010000XXXXXXX >XX..; @140544 <00h0000XXXXXXX >XX..; @141032 <00h0000XXXXXXX >XX..; @141520 <00h0000XXXXXXX >XX..; @142008 <00h0000XXXXXXX >XX..; @142496 <00h0000XXXXXXX >XX..; @142984 <00h0000XXXXXXX >XX..; @143472 <00h0000XXXXXXX >XX..; @143960 <00h0000XXXXXXX >XX..; @144448 <00h0000XXXXXXX >XX..; @144936 <00h0000XXXXXXX >XX..; @145424 <00h0000XXXXXXX >XX..; @145912 <00h0000XXXXXXX >XX..; @146400 <00h0000XXXXXXX >XX..; @146888 <00h0000XXXXXXX >XX..; @147376 <00h0000XXXXXXX >XX..; @147864 <00h0000XXXXXXX >XX..; @148352 <00h0000XXXXXXX >XX..; @148840 <00h0000XXXXXXX >XX..; @149328 <00h0000XXXXXXX >XX..; @149816 <00h0000XXXXXXX >XX..; @150304 <00h0000XXXXXXX >XX..; @150792 <00h0000XXXXXXX >XX..; @151280 <00h0000XXXXXXX >XX..; @151768 <00h0000XXXXXXX >XX..; @152256 <00h0000XXXXXXX >XX..; @152744 <00h0000XXXXXXX >XX..; @153232 <00h0000XXXXXXX >XX..; @153720 <00h0000XXXXXXX >XX..; @154208 <00h0000XXXXXXX >XX..; @154696 <00h0000XXXXXXX >XX..; @155184 <00h0000XXXXXXX >XX..; @155672 <00h0000XXXXXXX >XX..; @156160 <00h0000XXXXXXX >XX..; @156648 <00h0000XXXXXXX >XX..; @157136 <00h0000XXXXXXX >XX..; @157624 <00h0000XXXXXXX >XX..; @158112 <00h0000XXXXXXX >XX..; @158600 <00h0000XXXXXXX >XX..; @159088 <00h0000XXXXXXX >XX..; @159576 <00h0000XXXXXXX >XX..; @160064 <00h0000XXXXXXX >XX..; @160552 <00h0000XXXXXXX >XX..; @161040 <00h0000XXXXXXX >XX..; @161528 <00h0000XXXXXXX >XX..; @162016 <00h0000XXXXXXX >XX..; @162504 <00h0000XXXXXXX >XX..; @162992 <00h0000XXXXXXX >XX..; @163480 <00h0000XXXXXXX >XX..; @163968 <00h0000XXXXXXX >XX..; @164456 <00h0000XXXXXXX >XX..; @164944 <00h0000XXXXXXX >XX..; @165432 <00h0000XXXXXXX >XX..; @165920 <00h0000XXXXXXX >XX..; @166408 <00h0000XXXXXXX >XX..; @166896 <00h0000XXXXXXX >XX..; @167384 <00h0000XXXXXXX >XX..; @167872 <00h0000XXXXXXX >XX..; @168360 <00h0000XXXXXXX >XX..; @168848 <00h0000XXXXXXX >XX..; @169336 <00h0000XXXXXXX >XX..; @169824 <00h0000XXXXXXX >XX..; @170312 <00h0000XXXXXXX >XX..; @170800 <00h0000XXXXXXX >XX..; @171288 <00h0000XXXXXXX >XX..; @171776 <00h0000XXXXXXX >XX..; @172264 <00h0000XXXXXXX >XX..; @172752 <00h0000XXXXXXX >XX..; @173240 <00h0000XXXXXXX >XX..; @173728 <00h0000XXXXXXX >XX..; @174216 <00h0000XXXXXXX >XX..; @174704 <00h0000XXXXXXX >XX..; @175192 <00h0000XXXXXXX >XX..; @175680 <00h0000XXXXXXX >XX..; @176168 <00h0000XXXXXXX >XX..; @176656 <00h0000XXXXXXX >XX..; @177144 <00h0000XXXXXXX >XX..; @177632 <00h0000XXXXXXX >XX..; @178120 <00h0000XXXXXXX >XX..; @178608 <00h0000XXXXXXX >XX..; @179096 <00h0000XXXXXXX >XX..; @179584 <00h0000XXXXXXX >XX..; @180072 <00h0000XXXXXXX >XX..; @180560 <00h0000XXXXXXX >XX..; @181048 <00h0000XXXXXXX >XX..; @181536 <00h0000XXXXXXX >XX..; @182024 <00h0000XXXXXXX >XX..; @182512 <00h0000XXXXXXX >XX..; @183000 <00h0000XXXXXXX >XX..; @183488 <00h0000XXXXXXX >XX..; @183976 <00h0000XXXXXXX >XX..; @184464 <00h0000XXXXXXX >XX..; @184952 <00h0000XXXXXXX >XX..; @185440 <00h0000XXXXXXX >XX..; @185928 <00h0000XXXXXXX >XX..; @186416 <00h0000XXXXXXX >XX..; @186904 <00h0000XXXXXXX >XX..; @187392 <00h0000XXXXXXX >XX..; @187880 <00h0000XXXXXXX >XX..; @188368 <00h0000XXXXXXX >XX..; @188856 <00h0000XXXXXXX >XX..; @189344 <00h0000XXXXXXX >XX..; @189832 <00h0000XXXXXXX >XX..; @190320 <00h0000XXXXXXX >XX..; @190808 <00h0000XXXXXXX >XX..; @191296 <00h0000XXXXXXX >XX..; @191784 <00h0000XXXXXXX >XX..; @192272 <00h0000XXXXXXX >XX..; @192760 <00h0000XXXXXXX >XX..; @193248 <00h0000XXXXXXX >XX..; @193736 <00h0000XXXXXXX >XX..; @194224 <00h0000XXXXXXX >XX..; @194712 <00h0000XXXXXXX >XX..; @195200 <00h0000XXXXXXX >XX..; @195688 <00h0000XXXXXXX >XX..; @196176 <00h0000XXXXXXX >XX..; @196664 <00h0000XXXXXXX >XX..; @197152 <00h0000XXXXXXX >XX..; @197640 <00h0000XXXXXXX >XX..; @198128 <00h0000XXXXXXX >XX..; @198616 <00h0000XXXXXXX >XX..; @199104 <00h0000XXXXXXX >XX..; @199592 <00h0000XXXXXXX >XX..; @200080 <00h0000XXXXXXX >XX..; @200568 <00h0000XXXXXXX >XX..; @201056 <00h0000XXXXXXX >XX..; @201544 <00h0000XXXXXXX >XX..; @202032 <00h0000XXXXXXX >XX..; @202520 <00h0000XXXXXXX >XX..; @203008 <00h0000XXXXXXX >XX..; @203496 <00h0000XXXXXXX >XX..; @203984 <00h0000XXXXXXX >XX..; @204472 <00h0000XXXXXXX >XX..; @204960 <00h0000XXXXXXX >XX..; @205448 <00h0000XXXXXXX >XX..; @205936 <00h0000XXXXXXX >XX..; @206424 <00h0000XXXXXXX >XX..; @206912 <00h0000XXXXXXX >XX..; @207400 <00h0000XXXXXXX >XX..; @207888 <00h0000XXXXXXX >XX..; @208376 <00h0000XXXXXXX >XX..; @208864 <00h0000XXXXXXX >XX..; @209352 <00h0000XXXXXXX >XX..; @209840 <00h0000XXXXXXX >XX..; @210328 <00h0000XXXXXXX >XX..; @210816 <00h0000XXXXXXX >XX..; @211304 <00h0000XXXXXXX >XX..; @211792 <00h0000XXXXXXX >XX..; @212280 <00h0000XXXXXXX >XX..; @212768 <00h0000XXXXXXX >XX..; @213256 <00h0000XXXXXXX >XX..; @213744 <00h0000XXXXXXX >XX..; @214232 <00h0000XXXXXXX >XX..; @214720 <00h0000XXXXXXX >XX..; @215208 <00h0000XXXXXXX >XX..; @215696 <00h0000XXXXXXX >XX..; @216184 <00h0000XXXXXXX >XX..; @216672 <00h0000XXXXXXX >XX..; @217160 <00h0000XXXXXXX >XX..; @217648 <00h0000XXXXXXX >XX..; @218136 <00h0000XXXXXXX >XX..; @218624 <00h0000XXXXXXX >XX..; @219112 <00h0000XXXXXXX >XX..; @219600 <00h0000XXXXXXX >XX..; @220088 <00h0000XXXXXXX >XX..; @220576 <00h0000XXXXXXX >XX..; @221064 <00h0000XXXXXXX >XX..; @221552 <00h0000XXXXXXX >XX..; @222040 <00h0000XXXXXXX >XX..; @222528 <00h0000XXXXXXX >XX..; @223016 <00h0000XXXXXXX >XX..; @223504 <00h0000XXXXXXX >XX..; @223992 <00h0000XXXXXXX >XX..; @224480 <00h0000XXXXXXX >XX..; @224968 <00h0000XXXXXXX >XX..; @225456 <00h0000XXXXXXX >XX..; @225944 <00h0000XXXXXXX >XX..; @226432 <00h0000XXXXXXX >XX..; @226920 <00h0000XXXXXXX >XX..; @227408 <00h0000XXXXXXX >XX..; @227896 <00h0000XXXXXXX >XX..; @228384 <00h0000XXXXXXX >XX..; @228872 <00h0000XXXXXXX >XX..; @229360 <00h0000XXXXXXX >XX..; @229848 <00h0000XXXXXXX >XX..; @230336 <00h0000XXXXXXX >XX..; @230824 <00h0000XXXXXXX >XX..; @231312 <00h0000XXXXXXX >XX..; @231800 <00h0000XXXXXXX >XX..; @232288 <00h0000XXXXXXX >XX..; @232776 <00h0000XXXXXXX >XX..; @233264 <00h0000XXXXXXX >XX..; @233752 <00h0000XXXXXXX >XX..; @234240 <00h0000XXXXXXX >XX..; @234728 <00h0000XXXXXXX >XX..; @235216 <00h0000XXXXXXX >XX..; @235704 <00h0000XXXXXXX >XX..; @236192 <00h0000XXXXXXX >XX..; @236680 <00h0000XXXXXXX >XX..; @237168 <00h0000XXXXXXX >XX..; @237656 <00h0000XXXXXXX >XX..; @238144 <00h0000XXXXXXX >XX..; @238632 <00h0000XXXXXXX >XX..; @239120 <00h0000XXXXXXX >XX..; @239608 <00h0000XXXXXXX >XX..; @240096 <00h0000XXXXXXX >XX..; @240584 <00h0000XXXXXXX >XX..; @241072 <00h0000XXXXXXX >XX..; @241560 <00h0000XXXXXXX >XX..; @242048 <00h0000XXXXXXX >XX..; @242536 <00h0000XXXXXXX >XX..; @243024 <00h0000XXXXXXX >XX..; @243512 <00h0000XXXXXXX >XX..; @244000 <00h0000XXXXXXX >XX..; @244488 <00h0000XXXXXXX >XX..; @244976 <00h0000XXXXXXX >XX..; @245464 <00h0000XXXXXXX >XX..; @245952 <00h0000XXXXXXX >XX..; @246440 <00h0000XXXXXXX >XX..; @246928 <00h0000XXXXXXX >XX..; @247416 <00h0000XXXXXXX >XX..; @247904 <00h0000XXXXXXX >XX..; @248392 <00h0000XXXXXXX >XX..; @248880 <00h0000XXXXXXX >XX..; @249368 <00h0000XXXXXXX >XX..; @249856 <01100000000000 >XX..; @250344 <00000000001000 >XX..; @250832 <00100000001000 >XX..; @251320 <00000000001000 >XX..; @251808 <00000000001000 >XX..; @252296 <00000000001000 >XX..; @252784 <00000000000000 >XX..; @253272 <00100000000000 >XX..; @253760 <00100000000000 >XX..; @254248 <00100000000000 >XX..; @254736 <00000000000000 >XX..; @255224 <00100000000000 >XX..; @255712 <00000000000000 >XX..; @256200 <00100000000000 >XX..; @256688 <00000000000000 >XX..; @257176 <00100000000000 >XX..; @257664 <00100000000000 >XH..; @258152 <00000000000000 >XH..; @258640 <00000000000000 >XH..; @259128 <00000000000000 >XH..; @259616 <00000000000000 >XH..; @260104 <00000000000000 >XH..; @260592 <00000000000000 >XH..; @261080 <00100000000000 >XH..; @261568 <00000000000000 >XX..; @262056 <00000000000000 >XX..; @262544 <00000000000000 >XX..; @263032 <00000000000000 >XX..; @263520 <00000000000000 >XX..; @264008 <00000000000000 >XX..; @264496 <00100000000000 >XH..; @264984 <00000000000000 >XH..; @265472 <00l00000000000 >XH..; @265960 <00l00000000000 >XH..; @266448 <00l00000000000 >XH..; @266936 <00l00000000000 >XH..; @267424 <00l00000000000 >XH..; @267912 <00l00000000000 >XH..; @268400 <00l00000000000 >XH..; @268888 <00l00000000000 >XH..; @269376 <00l00000000000 >XH..; @269864 <00l00000000000 >XH..; @270352 <00l00000000000 >XH..; @270840 <00l00000000000 >XH..; @271328 <00l00000000000 >XH..; @271816 <00l00000000000 >XH..; @272304 <00l00000000000 >XH..; @272792 <00l00000000000 >XH..; @273280 <00l00000000000 >XH..; @273768 <00l00000000000 >XH..; @274256 <00l00000000000 >XH..; @274744 <00l00000000000 >XH..; @275232 <00l00000000000 >XH..; @275720 <00l00000000000 >XH..; @276208 <00l00000000000 >XH..; @276696 <00l00000000000 >XH..; @277184 <00l00000000000 >XH..; @277672 <00l00000000000 >XH..; @278160 <00l00000000000 >XH..; @278648 <00l00000000000 >XH..; @279136 <00l00000000000 >XH..; @279624 <00l00000000000 >XH..; @280112 <00l00000000000 >XH..; @280600 <00l00000000000 >XH..; @281088 <00l00000000000 >XH..; @281576 <00l00000000000 >XH..; @282064 <00l00000000000 >XH..; @282552 <00l00000000000 >XH..; @283040 <00l00000000000 >XH..; @283528 <00l00000000000 >XH..; @284016 <00l00000000000 >XH..; @284504 <00l00000000000 >XH..; @284992 <00l00000000000 >XH..; @285480 <00l00000000000 >XH..; @285968 <00l00000000000 >XH..; @286456 <00l00000000000 >XH..; @286944 <00l00000000000 >XH..; @287432 <00l00000000000 >XH..; @287920 <00l00000000000 >XH..; @288408 <00l00000000000 >XH..; @288896 <00l00000000000 >XH..; @289384 <00l00000000000 >XH..; @289872 <00l00000000000 >XH..; @290360 <00l00000000000 >XH..; @290848 <00l00000000000 >XH..; @291336 <00l00000000000 >XH..; @291824 <00l00000000000 >XH..; @292312 <00l00000000000 >XH..; @292800 <00l00000000000 >XH..; @293288 <00l00000000000 >XH..; @293776 <00l00000000000 >XH..; @294264 <00l00000000000 >XH..; @294752 <00l00000000000 >XH..; @295240 <00l00000000000 >XH..; @295728 <00l00000000000 >XH..; @296216 <00l00000000000 >XH..; @296704 <00l00000000000 >XH..; @297192 <00l00000000000 >XH..; @297680 <00l00000000000 >XH..; @298168 <00l00000000000 >XH..; @298656 <00l00000000000 >XH..; @299144 <00l00000000000 >XH..; @299632 <00l00000000000 >XH..; @300120 <00l00000000000 >XH..; @300608 <00l00000000000 >XH..; @301096 <00l00000000000 >XH..; @301584 <00l00000000000 >XH..; @302072 <00l00000000000 >XH..; @302560 <00l00000000000 >XH..; @303048 <00l00000000000 >XH..; @303536 <00l00000000000 >XH..; @304024 <00l00000000000 >XH..; @304512 <00l00000000000 >XH..; @305000 <00l00000000000 >XH..; @305488 <00l00000000000 >XH..; @305976 <00l00000000000 >XH..; @306464 <00l00000000000 >XH..; @306952 <00l00000000000 >XH..; @307440 <00l00000000000 >XH..; @307928 <00l00000000000 >XH..; @308416 <00l00000000000 >XH..; @308904 <00l00000000000 >XH..; @309392 <00l00000000000 >XH..; @309880 <00l00000000000 >XH..; @310368 <00l00000000000 >XH..; @310856 <00l00000000000 >XH..; @311344 <00l00000000000 >XH..; @311832 <00l00000000000 >XH..; @312320 <00l00000000000 >XH..; @312808 <00l00000000000 >XH..; @313296 <00l00000000000 >XH..; @313784 <00l00000000000 >XH..; @314272 <00l00000000000 >XH..; @314760 <00l00000000000 >XH..; @315248 <00l00000000000 >XH..; @315736 <00l00000000000 >XH..; @316224 <00l00000000000 >XH..; @316712 <00l00000000000 >XH..; @317200 <00l00000000000 >XH..; @317688 <00l00000000000 >XH..; @318176 <00l00000000000 >XH..; @318664 <00l00000000000 >XH..; @319152 <00l00000000000 >XH..; @319640 <00l00000000000 >XH..; @320128 <00l00000000000 >XH..; @320616 <00l00000000000 >XH..; @321104 <00l00000000000 >XH..; @321592 <00l00000000000 >XH..; @322080 <00l00000000000 >XH..; @322568 <00l00000000000 >XH..; @323056 <00l00000000000 >XH..; @323544 <00l00000000000 >XH..; @324032 <00l00000000000 >XH..; @324520 <00l00000000000 >XH..; @325008 <00l00000000000 >XH..; @325496 <00l00000000000 >XH..; @325984 <00l00000000000 >XH..; @326472 <00l00000000000 >XH..; @326960 <00l00000000000 >XH..; @327448 <00l00000000000 >XH..; @327936 <00l00000000000 >XH..; @328424 <00l00000000000 >XH..; @328912 <00l00000000000 >XH..; @329400 <00l00000000000 >XH..; @329888 <00l00000000000 >XH..; @330376 <00l00000000000 >XH..; @330864 <00l00000000000 >XH..; @331352 <00l00000000000 >XH..; @331840 <00l00000000000 >XH..; @332328 <00l00000000000 >XH..; @332816 <00l00000000000 >XH..; @333304 <00l00000000000 >XH..; @333792 <00l00000000000 >XH..; @334280 <00l00000000000 >XH..; @334768 <00l00000000000 >XH..; @335256 <00l00000000000 >XH..; @335744 <00l00000000000 >XH..; @336232 <00l00000000000 >XH..; @336720 <00l00000000000 >XH..; @337208 <00l00000000000 >XH..; @337696 <00l00000000000 >XH..; @338184 <00l00000000000 >XH..; @338672 <00l00000000000 >XH..; @339160 <00l00000000000 >XH..; @339648 <00l00000000000 >XH..; @340136 <00l00000000000 >XH..; @340624 <00l00000000000 >XH..; @341112 <00l00000000000 >XH..; @341600 <00l00000000000 >XH..; @342088 <00l00000000000 >XH..; @342576 <00l00000000000 >XH..; @343064 <00l00000000000 >XH..; @343552 <00l00000000000 >XH..; @344040 <00l00000000000 >XH..; @344528 <00l00000000000 >XH..; @345016 <00l00000000000 >XH..; @345504 <00l00000000000 >XH..; @345992 <00l00000000000 >XH..; @346480 <00l00000000000 >XH..; @346968 <00l00000000000 >XH..; @347456 <00l00000000000 >XH..; @347944 <00l00000000000 >XH..; @348432 <00l00000000000 >XH..; @348920 <00l00000000000 >XH..; @349408 <00l00000000000 >XH..; @349896 <00l00000000000 >XH..; @350384 <00l00000000000 >XH..; @350872 <00l00000000000 >XH..; @351360 <00l00000000000 >XH..; @351848 <00l00000000000 >XH..; @352336 <00l00000000000 >XH..; @352824 <00l00000000000 >XH..; @353312 <00l00000000000 >XH..; @353800 <00l00000000000 >XH..; @354288 <00l00000000000 >XH..; @354776 <00l00000000000 >XH..; @355264 <00l00000000000 >XH..; @355752 <00l00000000000 >XH..; @356240 <00l00000000000 >XH..; @356728 <00l00000000000 >XH..; @357216 <00l00000000000 >XH..; @357704 <00l00000000000 >XH..; @358192 <00l00000000000 >XH..; @358680 <00l00000000000 >XH..; @359168 <00l00000000000 >XH..; @359656 <00l00000000000 >XH..; @360144 <00l00000000000 >XH..; @360632 <00l00000000000 >XH..; @361120 <00l00000000000 >XH..; @361608 <00l00000000000 >XH..; @362096 <00l00000000000 >XH..; @362584 <00l00000000000 >XH..; @363072 <00l00000000000 >XH..; @363560 <00l00000000000 >XH..; @364048 <00l00000000000 >XH..; @364536 <00l00000000000 >XH..; @365024 <00l00000000000 >XH..; @365512 <00l00000000000 >XH..; @366000 <00l00000000000 >XH..; @366488 <00l00000000000 >XH..; @366976 <00l00000000000 >XH..; @367464 <00l00000000000 >XH..; @367952 <00l00000000000 >XH..; @368440 <00l00000000000 >XH..; @368928 <00l00000000000 >XH..; @369416 <00l00000000000 >XH..; @369904 <00l00000000000 >XH..; @370392 <00l00000000000 >XH..; @370880 <00l00000000000 >XH..; @371368 <00l00000000000 >XH..; @371856 <00l00000000000 >XH..; @372344 <00l00000000000 >XH..; @372832 <00l00000000000 >XH..; @373320 <00l00000000000 >XH..; @373808 <00l00000000000 >XH..; @374296 <00l00000000000 >XH..; @374784 <01100000000000 >XX..; @375272 <00000000000000 >XX..; @375760 <00000000000000 >XX..; @376248 <00000000000000 >XX..; @376736 <00000000000000 >XX..; @377224 <00000000000000 >XX..; @377712 <00000000000000 >XX..; @378200 <00100000000000 >XX..; @378688 <00100000000000 >XX..; @379176 <00100000000000 >XX..; @379664 <00000000000000 >XX..; @380152 <00100000000000 >XX..; @380640 <00000000000000 >XX..; @381128 <00100000000000 >XX..; @381616 <00000000000000 >XX..; @382104 <00100000000000 >XX..; @382592 <00100000000000 >XH..; @383080 <00000000000000 >XH..; @383568 <00000000000000 >XH..; @384056 <00000000000000 >XH..; @384544 <00000000000000 >XH..; @385032 <00000000000000 >XH..; @385520 <00000000000000 >XH..; @386008 <00100000000000 >XH..; @386496 <00000000000000 >XX..; @386984 <00000000000000 >XX..; @387472 <00000000000000 >XX..; @387960 <00000000000000 >XX..; @388448 <00000000000000 >XX..; @388936 <00000000000000 >XX..; @389424 <00100000000000 >XL..; @389912 <00000000000000 >XH..; @390400 <00l00000000000 >XH..; @390888 <00l00000000000 >XH..; @391376 <00l00000000000 >XH..; @391864 <00l00000000000 >XH..; @392352 <00l00000000000 >XH..; @392840 <00l00000000000 >XH..; @393328 <00l00000000000 >XH..; @393816 <00l00000000000 >XH..; @394304 <00l00000000000 >XH..; @394792 <00l00000000000 >XH..; @395280 <00l00000000000 >XH..; @395768 <00l00000000000 >XH..; @396256 <00l00000000000 >XH..; @396744 <00l00000000000 >XH..; @397232 <00l00000000000 >XH..; @397720 <00l00000000000 >XH..; @398208 <00l00000000000 >XH..; @398696 <00l00000000000 >XH..; @399184 <00l00000000000 >XH..; @399672 <00l00000000000 >XH..; @400160 <00l00000000000 >XH..; @400648 <00l00000000000 >XH..; @401136 <00l00000000000 >XH..; @401624 <00l00000000000 >XH..; @402112 <00l00000000000 >XH..; @402600 <00l00000000000 >XH..; @403088 <00l00000000000 >XH..; @403576 <00l00000000000 >XH..; @404064 <00l00000000000 >XH..; @404552 <00l00000000000 >XH..; @405040 <00l00000000000 >XH..; @405528 <00l00000000000 >XH..; @406016 <00l00000000000 >XH..; @406504 <00l00000000000 >XH..; @406992 <00l00000000000 >XH..; @407480 <00l00000000000 >XH..; @407968 <00l00000000000 >XH..; @408456 <00l00000000000 >XH..; @408944 <00l00000000000 >XH..; @409432 <00l00000000000 >XH..; @409920 <00l00000000000 >XH..; @410408 <00l00000000000 >XH..; @410896 <00l00000000000 >XH..; @411384 <00l00000000000 >XH..; @411872 <00l00000000000 >XH..; @412360 <00l00000000000 >XH..; @412848 <00l00000000000 >XH..; @413336 <00l00000000000 >XH..; @413824 <00l00000000000 >XH..; @414312 <00l00000000000 >XH..; @414800 <00l00000000000 >XH..; @415288 <00l00000000000 >XH..; @415776 <00l00000000000 >XH..; @416264 <00l00000000000 >XH..; @416752 <00l00000000000 >XH..; @417240 <00l00000000000 >XH..; @417728 <00l00000000000 >XH..; @418216 <00l00000000000 >XH..; @418704 <00l00000000000 >XH..; @419192 <00l00000000000 >XH..; @419680 <00l00000000000 >XH..; @420168 <00l00000000000 >XH..; @420656 <00l00000000000 >XH..; @421144 <00l00000000000 >XH..; @421632 <00l00000000000 >XH..; @422120 <00l00000000000 >XH..; @422608 <00l00000000000 >XH..; @423096 <00l00000000000 >XH..; @423584 <00l00000000000 >XH..; @424072 <00l00000000000 >XH..; @424560 <00l00000000000 >XH..; @425048 <00l00000000000 >XH..; @425536 <00l00000000000 >XH..; @426024 <00l00000000000 >XH..; @426512 <00l00000000000 >XH..; @427000 <00l00000000000 >XH..; @427488 <00l00000000000 >XH..; @427976 <00l00000000000 >XH..; @428464 <00l00000000000 >XH..; @428952 <00l00000000000 >XH..; @429440 <00l00000000000 >XH..; @429928 <00l00000000000 >XH..; @430416 <00l00000000000 >XH..; @430904 <00l00000000000 >XH..; @431392 <00l00000000000 >XH..; @431880 <00l00000000000 >XH..; @432368 <00l00000000000 >XH..; @432856 <00l00000000000 >XH..; @433344 <00l00000000000 >XH..; @433832 <00l00000000000 >XH..; @434320 <00l00000000000 >XH..; @434808 <00l00000000000 >XH..; @435296 <00l00000000000 >XH..; @435784 <00l00000000000 >XH..; @436272 <00l00000000000 >XH..; @436760 <00l00000000000 >XH..; @437248 <00l00000000000 >XH..; @437736 <00l00000000000 >XH..; @438224 <00l00000000000 >XH..; @438712 <00l00000000000 >XH..; @439200 <00l00000000000 >XH..; @439688 <00l00000000000 >XH..; @440176 <00l00000000000 >XH..; @440664 <00l00000000000 >XH..; @441152 <00l00000000000 >XH..; @441640 <00l00000000000 >XH..; @442128 <00l00000000000 >XH..; @442616 <00l00000000000 >XH..; @443104 <00l00000000000 >XH..; @443592 <00l00000000000 >XH..; @444080 <00l00000000000 >XH..; @444568 <00l00000000000 >XH..; @445056 <00l00000000000 >XH..; @445544 <00l00000000000 >XH..; @446032 <00l00000000000 >XH..; @446520 <00l00000000000 >XH..; @447008 <00l00000000000 >XH..; @447496 <00l00000000000 >XH..; @447984 <00l00000000000 >XH..; @448472 <00l00000000000 >XH..; @448960 <00l00000000000 >XH..; @449448 <00l00000000000 >XH..; @449936 <00l00000000000 >XH..; @450424 <00l00000000000 >XH..; @450912 <00l00000000000 >XH..; @451400 <00l00000000000 >XH..; @451888 <00l00000000000 >XH..; @452376 <00l00000000000 >XH..; @452864 <00l00000000000 >XH..; @453352 <00l00000000000 >XH..; @453840 <00l00000000000 >XH..; @454328 <00l00000000000 >XH..; @454816 <00l00000000000 >XH..; @455304 <00l00000000000 >XH..; @455792 <00l00000000000 >XH..; @456280 <00l00000000000 >XH..; @456768 <00l00000000000 >XH..; @457256 <00l00000000000 >XH..; @457744 <00l00000000000 >XH..; @458232 <00l00000000000 >XH..; @458720 <00l00000000000 >XH..; @459208 <00l00000000000 >XH..; @459696 <00l00000000000 >XH..; @460184 <00l00000000000 >XH..; @460672 <00l00000000000 >XH..; @461160 <00l00000000000 >XH..; @461648 <00l00000000000 >XH..; @462136 <00l00000000000 >XH..; @462624 <00l00000000000 >XH..; @463112 <00l00000000000 >XH..; @463600 <00l00000000000 >XH..; @464088 <00l00000000000 >XH..; @464576 <00l00000000000 >XH..; @465064 <00l00000000000 >XH..; @465552 <00l00000000000 >XH..; @466040 <00l00000000000 >XH..; @466528 <00l00000000000 >XH..; @467016 <00l00000000000 >XH..; @467504 <00l00000000000 >XH..; @467992 <00l00000000000 >XH..; @468480 <00l00000000000 >XH..; @468968 <00l00000000000 >XH..; @469456 <00l00000000000 >XH..; @469944 <00l00000000000 >XH..; @470432 <00l00000000000 >XH..; @470920 <00l00000000000 >XH..; @471408 <00l00000000000 >XH..; @471896 <00l00000000000 >XH..; @472384 <00l00000000000 >XH..; @472872 <00l00000000000 >XH..; @473360 <00l00000000000 >XH..; @473848 <00l00000000000 >XH..; @474336 <00l00000000000 >XH..; @474824 <00l00000000000 >XH..; @475312 <00l00000000000 >XH..; @475800 <00l00000000000 >XH..; @476288 <00l00000000000 >XH..; @476776 <00l00000000000 >XH..; @477264 <00l00000000000 >XH..; @477752 <00l00000000000 >XH..; @478240 <00l00000000000 >XH..; @478728 <00l00000000000 >XH..; @479216 <00l00000000000 >XH..; @479704 <00l00000000000 >XH..; @480192 <00l00000000000 >XH..; @480680 <00l00000000000 >XH..; @481168 <00l00000000000 >XH..; @481656 <00l00000000000 >XH..; @482144 <00l00000000000 >XH..; @482632 <00l00000000000 >XH..; @483120 <00l00000000000 >XH..; @483608 <00l00000000000 >XH..; @484096 <00l00000000000 >XH..; @484584 <00l00000000000 >XH..; @485072 <00l00000000000 >XH..; @485560 <00l00000000000 >XH..; @486048 <00l00000000000 >XH..; @486536 <00l00000000000 >XH..; @487024 <00l00000000000 >XH..; @487512 <00l00000000000 >XH..; @488000 <00l00000000000 >XH..; @488488 <00l00000000000 >XH..; @488976 <00l00000000000 >XH..; @489464 <00l00000000000 >XH..; @489952 <00l00000000000 >XH..; @490440 <00l00000000000 >XH..; @490928 <00l00000000000 >XH..; @491416 <00l00000000000 >XH..; @491904 <00l00000000000 >XH..; @492392 <00l00000000000 >XH..; @492880 <00l00000000000 >XH..; @493368 <00l00000000000 >XH..; @493856 <00l00000000000 >XH..; @494344 <00l00000000000 >XH..; @494832 <00l00000000000 >XH..; @495320 <00l00000000000 >XH..; @495808 <00l00000000000 >XH..; @496296 <00l00000000000 >XH..; @496784 <00l00000000000 >XH..; @497272 <00l00000000000 >XH..; @497760 <00l00000000000 >XH..; @498248 <00l00000000000 >XH..; @498736 <00l00000000000 >XH..; @499224 <00l00000000000 >XH..; @499712 <01000000000000 >XX..; @500200 <00000000000000 >XX..; @500688 <00100000000000 >XX..; @501176 <00100000000000 >XX..; @501664 <00100000000000 >XX..; @502152 <00000000000000 >XX..; @502640 <00000000000000 >XX..; @503128 <00000000000000 >XX..; @503616 <00100000000000 >XX..; @504104 <00100000000000 >XX..; @504592 <00000000000000 >XX..; @505080 <00100000000000 >XX..; @505568 <00000000000000 >XX..; @506056 <00100000000000 >XX..; @506544 <00000000000000 >XX..; @507032 <00100000000000 >XX..; @507520 <00000000000000 >XH..; @508008 <00000000000000 >XH..; @508496 <00000000000000 >XH..; @508984 <00000000000000 >XH..; @509472 <00000000000000 >XH..; @509960 <00100000000000 >XH..; @510448 <00000000000000 >XH..; @510936 <00100000000000 >XH..; @511424 <00000000000000 >XX..; @511912 <00000000000000 >XX..; @512400 <00000000000000 >XX..; @512888 <00000000000000 >XX..; @513376 <00000000000000 >XX..; @513864 <00000000000000 >XX..; @514352 <00100000000000 >XL..; @514840 <00100000000000 >XH..; @515328 <00h00000000000 >XH..; @515816 <00h00000000000 >XH..; @516304 <00h00000000000 >XH..; @516792 <00h00000000000 >XH..; @517280 <00h00000000000 >XH..; @517768 <00h00000000000 >XH..; @518256 <00h00000000000 >XH..; @518744 <00h00000000000 >XH..; @519232 <00h00000000000 >XH..; @519720 <00h00000000000 >XH..; @520208 <00h00000000000 >XH..; @520696 <00h00000000000 >XH..; @521184 <00h00000000000 >XH..; @521672 <00h00000000000 >XH..; @522160 <00h00000000000 >XH..; @522648 <00h00000000000 >XH..; @523136 <00h00000000000 >XH..; @523624 <00h00000000000 >XH..; @524112 <00h00000000000 >XH..; @524600 <00h00000000000 >XH..; @525088 <00h00000000000 >XH..; @525576 <00h00000000000 >XH..; @526064 <00h00000000000 >XH..; @526552 <00h00000000000 >XH..; @527040 <00h00000000000 >XH..; @527528 <00h00000000000 >XH..; @528016 <00h00000000000 >XH..; @528504 <00h00000000000 >XH..; @528992 <00h00000000000 >XH..; @529480 <00h00000000000 >XH..; @529968 <00h00000000000 >XH..; @530456 <00h00000000000 >XH..; @530944 <00h00000000000 >XH..; @531432 <00h00000000000 >XH..; @531920 <00h00000000000 >XH..; @532408 <00h00000000000 >XH..; @532896 <00h00000000000 >XH..; @533384 <00h00000000000 >XH..; @533872 <00h00000000000 >XH..; @534360 <00h00000000000 >XH..; @534848 <00h00000000000 >XH..; @535336 <00h00000000000 >XH..; @535824 <00h00000000000 >XH..; @536312 <00h00000000000 >XH..; @536800 <00h00000000000 >XH..; @537288 <00h00000000000 >XH..; @537776 <00h00000000000 >XH..; @538264 <00h00000000000 >XH..; @538752 <00h00000000000 >XH..; @539240 <00h00000000000 >XH..; @539728 <00h00000000000 >XH..; @540216 <00h00000000000 >XH..; @540704 <00h00000000000 >XH..; @541192 <00h00000000000 >XH..; @541680 <00h00000000000 >XH..; @542168 <00h00000000000 >XH..; @542656 <00h00000000000 >XH..; @543144 <00h00000000000 >XH..; @543632 <00h00000000000 >XH..; @544120 <00h00000000000 >XH..; @544608 <00h00000000000 >XH..; @545096 <00h00000000000 >XH..; @545584 <00h00000000000 >XH..; @546072 <00h00000000000 >XH..; @546560 <00h00000000000 >XH..; @547048 <00h00000000000 >XH..; @547536 <00h00000000000 >XH..; @548024 <00h00000000000 >XH..; @548512 <00h00000000000 >XH..; @549000 <00h00000000000 >XH..; @549488 <00h00000000000 >XH..; @549976 <00h00000000000 >XH..; @550464 <00h00000000000 >XH..; @550952 <00h00000000000 >XH..; @551440 <00h00000000000 >XH..; @551928 <00h00000000000 >XH..; @552416 <00h00000000000 >XH..; @552904 <00h00000000000 >XH..; @553392 <00h00000000000 >XH..; @553880 <00h00000000000 >XH..; @554368 <00h00000000000 >XH..; @554856 <00h00000000000 >XH..; @555344 <00h00000000000 >XH..; @555832 <00h00000000000 >XH..; @556320 <00h00000000000 >XH..; @556808 <00h00000000000 >XH..; @557296 <00h00000000000 >XH..; @557784 <00h00000000000 >XH..; @558272 <00h00000000000 >XH..; @558760 <00h00000000000 >XH..; @559248 <00h00000000000 >XH..; @559736 <00h00000000000 >XH..; @560224 <00h00000000000 >XH..; @560712 <00h00000000000 >XH..; @561200 <00h00000000000 >XH..; @561688 <00h00000000000 >XH..; @562176 <00h00000000000 >XH..; @562664 <00h00000000000 >XH..; @563152 <00h00000000000 >XH..; @563640 <00h00000000000 >XH..; @564128 <00h00000000000 >XH..; @564616 <00h00000000000 >XH..; @565104 <00h00000000000 >XH..; @565592 <00h00000000000 >XH..; @566080 <00h00000000000 >XH..; @566568 <00h00000000000 >XH..; @567056 <00h00000000000 >XH..; @567544 <00h00000000000 >XH..; @568032 <00h00000000000 >XH..; @568520 <00h00000000000 >XH..; @569008 <00h00000000000 >XH..; @569496 <00h00000000000 >XH..; @569984 <00h00000000000 >XH..; @570472 <00h00000000000 >XH..; @570960 <00h00000000000 >XH..; @571448 <00h00000000000 >XH..; @571936 <00h00000000000 >XH..; @572424 <00h00000000000 >XH..; @572912 <00h00000000000 >XH..; @573400 <00h00000000000 >XH..; @573888 <00h00000000000 >XH..; @574376 <00h00000000000 >XH..; @574864 <00h00000000000 >XH..; @575352 <00h00000000000 >XH..; @575840 <00h00000000000 >XH..; @576328 <00h00000000000 >XH..; @576816 <00h00000000000 >XH..; @577304 <00h00000000000 >XH..; @577792 <00h00000000000 >XH..; @578280 <00h00000000000 >XH..; @578768 <00h00000000000 >XH..; @579256 <00h00000000000 >XH..; @579744 <00h00000000000 >XH..; @580232 <00h00000000000 >XH..; @580720 <00h00000000000 >XH..; @581208 <00h00000000000 >XH..; @581696 <00h00000000000 >XH..; @582184 <00h00000000000 >XH..; @582672 <00h00000000000 >XH..; @583160 <00h00000000000 >XH..; @583648 <00h00000000000 >XH..; @584136 <00h00000000000 >XH..; @584624 <00h00000000000 >XH..; @585112 <00h00000000000 >XH..; @585600 <00h00000000000 >XH..; @586088 <00h00000000000 >XH..; @586576 <00h00000000000 >XH..; @587064 <00h00000000000 >XH..; @587552 <00h00000000000 >XH..; @588040 <00h00000000000 >XH..; @588528 <00h00000000000 >XH..; @589016 <00h00000000000 >XH..; @589504 <00h00000000000 >XH..; @589992 <00h00000000000 >XH..; @590480 <00h00000000000 >XH..; @590968 <00h00000000000 >XH..; @591456 <00h00000000000 >XH..; @591944 <00h00000000000 >XH..; @592432 <00h00000000000 >XH..; @592920 <00h00000000000 >XH..; @593408 <00h00000000000 >XH..; @593896 <00h00000000000 >XH..; @594384 <00h00000000000 >XH..; @594872 <00h00000000000 >XH..; @595360 <00h00000000000 >XH..; END H..; @434808 <00l00000000000 >XH..; @435296 <00l00000000000 >XH..; @435784 <00l00000000000 >XH..; @436272 <00l00000000000 >XH..; @436760 <00l00000000000 >XH..; @437248 <00l00000000000 >XH..; @437736 <00l00000000000 >XH..; @438224 <00l00000000000 >XH..; @438712 <00l00000000000 >XH..; @439200 <00l00000000000 >XH..; @439INTERFACES/TERADYNE/STILJ750/000075500001440000012000000000001103104161000156505ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/STILJ750/exp1.vtran000064400001440000012000000047211103104161000176050ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J750 # # Original File: "exp1.stil" # # Target File: "exp1.j750 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J750'#### } state_trans pure_inputs 'X'->'0'; state_trans bidir_inputs 'X'->'0'; state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp1.testertim"; {#### OUTPUT FORMAT ####} target_file "exp1.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ750/exp2.vtran000064400001440000012000000046661103104161000176160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J750 # # Original File: "exp1.stil" # # Target File: "exp2.j750 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J750'#### } state_trans pure_inputs 'X'->'0'; state_trans bidir_inputs 'X'->'0'; state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp2.testertim"; {#### OUTPUT FORMAT ####} target_file "exp2.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ750/exp3.vtran000064400001440000012000000046741103104161000176160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J750 # # Original File: "exp1.stil" # # Target File: "exp3.j750 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE -SCAN ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J750 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J750'#### } state_trans pure_inputs 'X'->'0'; state_trans bidir_inputs 'X'->'0'; state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { header 100; } { #### This puts the vertical pin names in as comments #### } rename_bus_pins $bus_$vec; tester_format teradyne -J750, -auto_group, -use_tset_names, wr_timeset_file="exp3.testertim"; {#### OUTPUT FORMAT ####} target_file "exp3.j750"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ971/000075500001440000012000000000001103104161000156555ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/STILJ971/exp1.vtran000064400001440000012000000050071103104161000176100ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J971 # # Original File: "exp1.stil" # # Target File: "exp1.j971 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE -expand_loops -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J971'#### } state_trans pure_inputs 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs 'X'->'Z'; { #### no undefined inputs #### } state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp1.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ971/exp2.vtran000064400001440000012000000046441103104161000176170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J971 # # Original File: "exp1.stil" # # Target File: "exp2.j971 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J971'#### } state_trans pure_inputs 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs 'X'->'Z'; { #### no undefined inputs #### } state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp2.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ971/exp3.vtran000064400001440000012000000046521103104161000176170ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J971 # # Original File: "exp1.stil" # # Target File: "exp3.j971 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -CYCLE -SCAN ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J971 format # #======================================================================# } proc_block begin; { #### state character translations for 'STIL'->'J971'#### } state_trans pure_inputs 'X'->'0'; { #### no undefined inputs #### } state_trans bidir_inputs 'X'->'Z'; { #### no undefined inputs #### } state_trans outputs 'Z'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; tester_format teradyne {#### OUTPUT FORMAT ####} -J971, TERMINATE = "stop", -auto_group ; target_file "exp3.j971"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILJ973/000075500001440000012000000000001103104161000156575ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/STILJ973/exp1.vtran000064400001440000012000000051431103104161000176130ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J973 # # Original File: "exp1.stil" # # Target File: "exp1.j973 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'J973'#### } state_trans inputs 'X'->'0'; state_trans outputs 'Z'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp1.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/STILJ973/exp2.vtran000064400001440000012000000051111103104161000176070ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J973 # # Original File: "exp1.stil" # # Target File: "exp2.j973 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'J973'#### } state_trans inputs 'X'->'0'; state_trans outputs 'Z'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp2.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/STILJ973/exp3.vtran000064400001440000012000000051171103104161000176160ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > J973 # # Original File: "exp1.stil" # # Target File: "exp3.j973 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.stil"; {#### INPUT VECTOR FILE ####} tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into J973 format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'J973'#### } state_trans inputs 'X'->'0'; state_trans outputs 'Z'->'X'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin rename_bus_pins $bus$vec; { #### remove bus []'s #### } comments on; { #### pass comments #### } merge_bidirects 10HLXZ; target_file "exp3.j973"; {#### OUTPUT VECTOR FILE ####} header 80; {#### Pin names as vertical comments #### } tester_format Teradyne, {#### OUTPUT FORMAT ####} -J973, -AUTO_GROUP, { #### Auto creation of pin groups #### } Pattern_Name = "Circuit1_Vecs", Terminate = "stop", Source_Select_Group = "prim_src"; end end; INTERFACES/TERADYNE/EVCDFLEX/000075500001440000012000000000001137104243500157445ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/EVCDFLEX/exp1.vtran000064400001440000012000000101541137104243000176710ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > FLEX # # Original File: "exp1.evcd" # # Target File: "exp1.flex " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.6.1 (C) 2006 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'FLEX' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1', 'Z'->'X', 'T'->'X', 'x'->'X', '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'0', 'f'->'X', 'F'->'X'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'X', 'F'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 19, ma[7] @ 19; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; TESTER_FORMAT TERADYNE {#### OUTPUT FORMAT ####} -FLEX, -AUTO_GROUP, -BASIC_TIMING_FORMULAS, MAX_LINE_LENGTH = "800", TIME_STAMPS = "ON", WR_TIMESET_FILE = "exp1_tim", ; target_file "exp1.flex"; {#### OUTPUT VECTOR FILE ####} create_statistics "file.rpt" * ; end end INTERFACES/TERADYNE/EVCDFLEX/exp2.vtran000064400001440000012000000075201133466614400177120ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > FLEX # # Original File: "exp1.evcd" # # Target File: "exp2.flex " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'FLEX' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1', 'Z'->'X', 'T'->'X', 'x'->'X', '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'0', 'f'->'X', 'F'->'X'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'X', 'F'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'M', 'F'->'M'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; TESTER_FORMAT TERADYNE {#### OUTPUT FORMAT ####} -FLEX, -AUTO_GROUP, -BASIC_TIMING_FORMULAS, MAX_LINE_LENGTH = "800", TIME_STAMPS = "ON", WR_TIMESET_FILE = "exp2_tim", ; target_file "exp2.flex"; {#### OUTPUT VECTOR FILE ####} end end INTERFACES/TERADYNE/EVCDFLEX/exp1.flex000064400001440000012000001645051137104243500175140ustar00jcosleystaff00000400000023// // Converted by vtran version: 9.1.4 // Date: Fri May 7 09:51:41 2010 // Source file: ../../DATA/exp1.evcd // Filetype: FLEX // import_all_undefineds = yes; opcode_mode = single; import tset ts1 ; vector ($tset clki, clk2x, vcxo_ctrl, bclko, test, bopt, (devid[3], devid[2], devid[1], devid[0]), dsp_only, hrst_, (had[31], had[30], had[29], had[28], had[27], had[26], had[25], had[24], had[23], had[22], had[21], had[20], had[19], had[18], had[17], had[16], had[15], had[14], had[13], had[12], had[11], had[10], had[9], had[8], had[7], had[6], had[5], had[4], had[3], had[2], had[1], had[0]), (hc13, hc11), (hc9_0[9], hc9_0[8], hc9_0[7], hc9_0[6], hc9_0[5], hc9_0[4], hc9_0[3], hc9_0[2], hc9_0[1], hc9_0[0]), (fa22, fa23), uart_rx, uart_tx, usbp, usbn, em1_tx_clk, (em1_txd[3], em1_txd[2], em1_txd[1], em1_txd[0]), em1_tx_en, em1_txer, em1_crs, em1_col, em1_rx_clk, (em1_rxd[3], em1_rxd[2], em1_rxd[1], em1_rxd[0]), em1_rxdv, em1_rxer, em1_mdc, em1_mdio, (md[15], md[14], md[13], md[12], md[11], md[10], md[9], md[8], md[7], md[6], md[5], md[4], md[3], md[2], md[1], md[0]), (ma[12], ma[11], ma[10], ma[9], ma[8], ma[7], ma[6], ma[5], ma[4], ma[3], ma[2], ma[1], ma[0]), (mb[1], mb[0]), (mm[1], mm[0]), mras_, mcas_, mwe_, (mcs_[1], mcs_[0]), mcke, mclk, (gpio42_40[42], gpio42_40[41], gpio42_40[40]), (gpio38, gpio33, gpio26, gpio25), (gpio22_13[22], gpio22_13[21], gpio22_13[20], gpio22_13[19], gpio22_13[18], gpio22_13[17], gpio22_13[16], gpio22_13[15], gpio22_13[14], gpio22_13[13], gpio8_5[8], gpio8_5[7], gpio8_5[6], gpio8_5[5]), (gpio3, gpio2, gpio1), trst_, tck, tms, tdi, tdo, afetx0, (aferx0, aferx1), fafe_sclk, fafe_stb, fafe_ctrlin, fafe_ctrlout, mon_done, mon_clk, mon_out, vregenn ) { > 1 1 M X X 0 1 0000 0 0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XX XXXXXXXXXX XX M X X X 0 XXXX X X 0 0 0 M000 0 0 X X XXXXXXXXXXXXXXXX XXXXX11XXXXXX XX XX X X X XX X L XXX XX0X XXXXXXXXXXXXXX XXX 0 0 1 0 M M MM 0 M M 0 X X X 1 ; // 0 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 20 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 40 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 60 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 80 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 100 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 120 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 140 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 160 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 180 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 200 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 220 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 240 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 260 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 280 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 300 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 320 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 340 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 360 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 380 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 400 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 420 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 440 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 460 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 480 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 500 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 520 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 540 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 560 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 580 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 600 > 1 1 M L L 0 1 0000 0 0 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 620 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 640 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 660 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLLMMMMMMMMMMMMMMMM 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 680 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 700 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 720 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 740 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 760 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 780 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 800 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 820 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 840 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 860 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 880 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 900 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 920 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 940 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 960 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 980 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1000 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1020 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1040 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1060 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1080 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1100 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1120 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1140 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1160 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1180 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1200 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1220 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1240 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1260 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1280 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1300 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1320 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1340 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1360 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1380 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1400 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1420 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1440 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1460 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1480 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1500 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1520 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1540 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1560 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1580 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1600 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1620 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1640 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1660 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1680 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1700 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1720 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1740 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1760 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1780 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L 1 0 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1800 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LLLLL11XXXXXX LL HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1820 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LXXXX11XXXXXX XX HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1840 > 1 1 M L H 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LXXXX11XXXXXX XX HH H H H HH L L MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1860 > 1 1 M L L 0 1 0000 0 1 HHHLLLLLLLLLLLLL1111111111111111 00 00000000L0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LXXXX11XXXXXX XX HH H H H HH L H MMM LX1M MXXHXLXXMMXHMX MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1880 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M XXXXXXXXXXXXXXXX LXXXX11XXXXXX XX HH H H H HH L L MMM XX1M MXXHXHXXMMXHMX MMX 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1900 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M MMMMMMMMMMMMMMMM LXXXX11MMMMMM XX HH H H H HH L H MMM MM1M MMMHMHMMMMMHMM MMM 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1920 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M MMMMMMMMMMMMMMMM LXXXX11MMMMMM XX HH H H H HH L L MMM MM1M MMMHMHMMMMMHMM MMM 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1940 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0000000100000000 LXXXX11000000 XX HH H H H HH L H MMM 001M M00H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1960 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0000000100000000 LXXXX01000000 XX HH H H H HH L L MMM 001M M00H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 1980 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0000000100000000 LXXXX01011101 XX HH H H H HH L H MMM 001M M00H0H00MM1HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2000 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0000000100000000 LXXXX10011101 XX HH H H H HH L L MMM 001M M00H0H00MM1HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2020 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101000000010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2040 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101000000010 LLLLL10000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2060 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2080 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2100 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2120 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2140 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2160 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2180 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2200 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2220 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2240 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2260 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2280 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2300 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2320 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2340 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2360 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2380 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2400 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2420 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2440 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2460 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2480 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2500 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2520 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2540 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2560 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2580 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2600 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2620 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2640 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2660 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2680 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2700 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2720 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2740 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2760 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2780 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2800 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2820 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LHLLLL LL HH H H H HH L H MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2840 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LHLLLL LL HH H H H HH L L MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2860 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2880 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2900 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL01100100 LL HH H H H HH L H MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2920 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL10100100 LL HH H H H HH L L MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2940 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2960 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 2980 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3000 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3020 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3040 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3060 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3080 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3100 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3120 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3140 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3160 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3180 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3200 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3220 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3240 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3260 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3280 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3300 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3320 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3340 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3360 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3380 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3400 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3420 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3440 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3460 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3480 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3500 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LHLLLL LL HH H H H HH L H MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3520 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LHLLLL LL HH H H H HH L L MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3540 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3560 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3580 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL01100100 LL HH H H H HH L H MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3600 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL10100100 LL HH H H H HH L L MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3620 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3640 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3660 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3680 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3700 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3720 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3740 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3760 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3780 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3800 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3820 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3840 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3860 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3880 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3900 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3920 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3940 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3960 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 3980 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4000 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4020 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4040 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4060 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4080 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4100 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4120 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4140 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4160 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4180 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LHLLLL LL HH H H H HH L H MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4200 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHLLLLHLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LHLLLL LL HH H H H HH L L MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4220 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4240 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4260 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL01100100 LL HH H H H HH L H MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4280 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0111101111010110 LLLLL10100100 LL HH H H H HH L L MMM 111M M11H0H00MM0HM0 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4300 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4320 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4340 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4360 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4380 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4400 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4420 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4440 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4460 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4480 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4500 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4520 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLLHLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4540 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4560 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4580 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLHLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4600 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4620 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4640 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4660 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4680 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL11000001 LL HH H H H HH L L MMM 001M M01H0H00MM1HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4700 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4720 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4740 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4760 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4780 > 1 1 M L L 0 1 0000 0 1 MMMMMMMMMMMMMMMMXXXXXXXXXXXXXXXX 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L H MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4800 > 1 1 M L H 0 1 0000 0 1 MMMMMMMMMMMMMMMM1111111111111111 00 00000000H0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M 0001101100100010 LLLLL10000001 LL HH H H H HH L L MMM 001M M01H0H00MM0HM1 MM0 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4820 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL10LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4840 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLL1111111111111111 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LLLLLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4860 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHHLLLHLH 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL11LHHLLH LL HH H H H HH L H MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4880 > 1 1 M L H 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLHHHLLLHLH 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LHHLLH LL HH H H H HH L L MMM LL1M MLLHLHLHMMLHMH MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4900 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLHLLLLL 00 0000000LH0 LL M L X X 0 LLLL L L 0 0 0 M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLLLL LL HH H H H HH L H MMM LL1M MLLHLHLLMMHHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4920 } M000 0 0 L M LLLLLLLLLLLLLLLL LLLLL01LLLHLL LL HH H H H HH L L MMM LL1M MLLHLHLLMMLHML MML 0 0 1 0 M M MM 0 M M 0 L L L 1 ; // 4060 > 1 1 M L L 0 1 0000 0 1 LLLLLLLLLLLLLLLLLLLLLLLLLLLINTERFACES/TERADYNE/EVCDFLEX/exp1_tim_pinmap.txt000064400001440000012000000053541137104243500216060ustar00jcosleystaff00000400000023DFF 1.0 Pin Map Group Name Pin Name Type Comment clki I/O clk2x I/O vcxo_ctrl I/O bclko I/O test I/O bopt I/O devid[3] I/O devid[2] I/O devid[1] I/O devid[0] I/O dsp_only I/O hrst_ I/O had[31] I/O had[30] I/O had[29] I/O had[28] I/O had[27] I/O had[26] I/O had[25] I/O had[24] I/O had[23] I/O had[22] I/O had[21] I/O had[20] I/O had[19] I/O had[18] I/O had[17] I/O had[16] I/O had[15] I/O had[14] I/O had[13] I/O had[12] I/O had[11] I/O had[10] I/O had[9] I/O had[8] I/O had[7] I/O had[6] I/O had[5] I/O had[4] I/O had[3] I/O had[2] I/O had[1] I/O had[0] I/O hc13 I/O hc11 I/O hc9_0[9] I/O hc9_0[8] I/O hc9_0[7] I/O hc9_0[6] I/O hc9_0[5] I/O hc9_0[4] I/O hc9_0[3] I/O hc9_0[2] I/O hc9_0[1] I/O hc9_0[0] I/O fa22 I/O fa23 I/O uart_rx I/O uart_tx I/O usbp I/O usbn I/O em1_tx_clk I/O em1_txd[3] I/O em1_txd[2] I/O em1_txd[1] I/O em1_txd[0] I/O em1_tx_en I/O em1_txer I/O em1_crs I/O em1_col I/O em1_rx_clk I/O em1_rxd[3] I/O em1_rxd[2] I/O em1_rxd[1] I/O em1_rxd[0] I/O em1_rxdv I/O em1_rxer I/O em1_mdc I/O em1_mdio I/O md[15] I/O md[14] I/O md[13] I/O md[12] I/O md[11] I/O md[10] I/O md[9] I/O md[8] I/O md[7] I/O md[6] I/O md[5] I/O md[4] I/O md[3] I/O md[2] I/O md[1] I/O md[0] I/O ma[12] I/O ma[11] I/O ma[10] I/O ma[9] I/O ma[8] I/O ma[7] I/O ma[6] I/O ma[5] I/O ma[4] I/O ma[3] I/O ma[2] I/O ma[1] I/O ma[0] I/O mb[1] I/O mb[0] I/O mm[1] I/O mm[0] I/O mras_ I/O mcas_ I/O mwe_ I/O mcs_[1] I/O mcs_[0] I/O mcke I/O mclk I/O gpio42_40[42] I/O gpio42_40[41] I/O gpio42_40[40] I/O gpio38 I/O gpio33 I/O gpio26 I/O gpio25 I/O gpio22_13[22] I/O gpio22_13[21] I/O gpio22_13[20] I/O gpio22_13[19] I/O gpio22_13[18] I/O gpio22_13[17] I/O gpio22_13[16] I/O gpio22_13[15] I/O gpio22_13[14] I/O gpio22_13[13] I/O gpio8_5[8] I/O gpio8_5[7] I/O gpio8_5[6] I/O gpio8_5[5] I/O gpio3 I/O gpio2 I/O gpio1 I/O trst_ I/O tck I/O tms I/O tdi I/O tdo I/O afetx0 I/O aferx0 I/O aferx1 I/O fafe_sclk I/O fafe_stb I/O fafe_ctrlin I/O fafe_ctrlout I/O mon_done I/O mon_clk I/O mon_out I/O vregenn I/O INTERFACES/TERADYNE/EVCDFLEX/exp1_tim_basic_ts.txt000064400001440000012000000264571137104243500221200ustar00jcosleystaff00000400000023DFF 1.1 Time Sets (Basic) Timing Mode: Single Cycle Pin/Group Data Drive Compare Time Set Period CPP Name Setup Src Fmt On Data Return Off Mode Open Close Comment ts1 20.000E-09 1 clki i/o PAT RL 0 =C7*0.500 =C7*1.000 Off ts1 20.000E-09 1 clk2x i/o PAT NR 0 0 =C8 Edge =C8*0.900 ts1 20.000E-09 1 vcxo_ctrl i/o PAT NR 0 0 =C9 Edge =C9*0.900 ts1 20.000E-09 1 bclko i/o PAT NR 0 0 =C10 Edge =C10*0.900 ts1 20.000E-09 1 test i/o PAT NR 0 =C11*0.250 Off ts1 20.000E-09 1 bopt i/o PAT NR 0 =C12*0.250 Off ts1 20.000E-09 1 devid[3] i/o PAT NR 0 =C13*0.250 =C13 Edge =C13*0.900 ts1 20.000E-09 1 devid[2] i/o PAT NR 0 =C14*0.250 =C14 Edge =C14*0.900 ts1 20.000E-09 1 devid[1] i/o PAT NR 0 =C15*0.250 =C15 Edge =C15*0.900 ts1 20.000E-09 1 devid[0] i/o PAT NR 0 =C16*0.250 =C16 Edge =C16*0.900 ts1 20.000E-09 1 dsp_only i/o PAT NR 0 =C17*0.250 Off ts1 20.000E-09 1 hrst_ i/o PAT NR 0 =C18*0.250 Off ts1 20.000E-09 1 had[31] i/o PAT NR 0 0 =C19 Edge =C19*0.900 ts1 20.000E-09 1 had[30] i/o PAT NR 0 0 =C20 Edge =C20*0.900 ts1 20.000E-09 1 had[29] i/o PAT NR 0 0 =C21 Edge =C21*0.900 ts1 20.000E-09 1 had[28] i/o PAT NR 0 0 =C22 Edge =C22*0.900 ts1 20.000E-09 1 had[27] i/o PAT NR 0 0 =C23 Edge =C23*0.900 ts1 20.000E-09 1 had[26] i/o PAT NR 0 0 =C24 Edge =C24*0.900 ts1 20.000E-09 1 had[25] i/o PAT NR 0 0 =C25 Edge =C25*0.900 ts1 20.000E-09 1 had[24] i/o PAT NR 0 0 =C26 Edge =C26*0.900 ts1 20.000E-09 1 had[23] i/o PAT NR 0 0 =C27 Edge =C27*0.900 ts1 20.000E-09 1 had[22] i/o PAT NR 0 0 =C28 Edge =C28*0.900 ts1 20.000E-09 1 had[21] i/o PAT NR 0 0 =C29 Edge =C29*0.900 ts1 20.000E-09 1 had[20] i/o PAT NR 0 0 =C30 Edge =C30*0.900 ts1 20.000E-09 1 had[19] i/o PAT NR 0 0 =C31 Edge =C31*0.900 ts1 20.000E-09 1 had[18] i/o PAT NR 0 0 =C32 Edge =C32*0.900 ts1 20.000E-09 1 had[17] i/o PAT NR 0 0 =C33 Edge =C33*0.900 ts1 20.000E-09 1 had[16] i/o PAT NR 0 0 =C34 Edge =C34*0.900 ts1 20.000E-09 1 had[15] i/o PAT NR 0 =C35*0.250 =C35 Edge =C35*0.900 ts1 20.000E-09 1 had[14] i/o PAT NR 0 =C36*0.250 =C36 Edge =C36*0.900 ts1 20.000E-09 1 had[13] i/o PAT NR 0 =C37*0.250 =C37 Edge =C37*0.900 ts1 20.000E-09 1 had[12] i/o PAT NR 0 =C38*0.250 =C38 Edge =C38*0.900 ts1 20.000E-09 1 had[11] i/o PAT NR 0 =C39*0.250 =C39 Edge =C39*0.900 ts1 20.000E-09 1 had[10] i/o PAT NR 0 =C40*0.250 =C40 Edge =C40*0.900 ts1 20.000E-09 1 had[9] i/o PAT NR 0 =C41*0.250 =C41 Edge =C41*0.900 ts1 20.000E-09 1 had[8] i/o PAT NR 0 =C42*0.250 =C42 Edge =C42*0.900 ts1 20.000E-09 1 had[7] i/o PAT NR 0 =C43*0.250 =C43 Edge =C43*0.900 ts1 20.000E-09 1 had[6] i/o PAT NR 0 =C44*0.250 =C44 Edge =C44*0.900 ts1 20.000E-09 1 had[5] i/o PAT NR 0 =C45*0.250 =C45 Edge =C45*0.900 ts1 20.000E-09 1 had[4] i/o PAT NR 0 =C46*0.250 =C46 Edge =C46*0.900 ts1 20.000E-09 1 had[3] i/o PAT NR 0 =C47*0.250 =C47 Edge =C47*0.900 ts1 20.000E-09 1 had[2] i/o PAT NR 0 =C48*0.250 =C48 Edge =C48*0.900 ts1 20.000E-09 1 had[1] i/o PAT NR 0 =C49*0.250 =C49 Edge =C49*0.900 ts1 20.000E-09 1 had[0] i/o PAT NR 0 =C50*0.250 =C50 Edge =C50*0.900 ts1 20.000E-09 1 hc13 i/o PAT NR 0 =C51*0.250 =C51 Edge =C51*0.900 ts1 20.000E-09 1 hc11 i/o PAT NR 0 =C52*0.250 =C52 Edge =C52*0.900 ts1 20.000E-09 1 hc9_0[9] i/o PAT NR 0 =C53*0.250 =C53 Edge =C53*0.900 ts1 20.000E-09 1 hc9_0[8] i/o PAT NR 0 =C54*0.250 =C54 Edge =C54*0.900 ts1 20.000E-09 1 hc9_0[7] i/o PAT NR 0 =C55*0.250 =C55 Edge =C55*0.900 ts1 20.000E-09 1 hc9_0[6] i/o PAT NR 0 =C56*0.250 =C56 Edge =C56*0.900 ts1 20.000E-09 1 hc9_0[5] i/o PAT NR 0 =C57*0.250 =C57 Edge =C57*0.900 ts1 20.000E-09 1 hc9_0[4] i/o PAT NR 0 =C58*0.250 =C58 Edge =C58*0.900 ts1 20.000E-09 1 hc9_0[3] i/o PAT NR 0 =C59*0.250 =C59 Edge =C59*0.900 ts1 20.000E-09 1 hc9_0[2] i/o PAT NR 0 =C60*0.250 =C60 Edge =C60*0.900 ts1 20.000E-09 1 hc9_0[1] i/o PAT NR 0 0 =C61 Edge =C61*0.900 ts1 20.000E-09 1 hc9_0[0] i/o PAT NR 0 =C62*0.250 =C62 Edge =C62*0.900 ts1 20.000E-09 1 fa22 i/o PAT NR 0 0 =C63 Edge =C63*0.900 ts1 20.000E-09 1 fa23 i/o PAT NR 0 0 =C64 Edge =C64*0.900 ts1 20.000E-09 1 uart_rx i/o PAT NR 0 0 =C65 Edge =C65*0.900 ts1 20.000E-09 1 uart_tx i/o PAT NR 0 0 =C66 Edge =C66*0.900 ts1 20.000E-09 1 usbp i/o PAT NR 0 =C67*0.250 =C67 Edge =C67*0.900 ts1 20.000E-09 1 usbn i/o PAT NR 0 =C68*0.250 =C68 Edge =C68*0.900 ts1 20.000E-09 1 em1_tx_clk i/o PAT NR 0 =C69*0.250 Off ts1 20.000E-09 1 em1_txd[3] i/o PAT NR 0 0 =C70 Edge =C70*0.900 ts1 20.000E-09 1 em1_txd[2] i/o PAT NR 0 0 =C71 Edge =C71*0.900 ts1 20.000E-09 1 em1_txd[1] i/o PAT NR 0 0 =C72 Edge =C72*0.900 ts1 20.000E-09 1 em1_txd[0] i/o PAT NR 0 0 =C73 Edge =C73*0.900 ts1 20.000E-09 1 em1_tx_en i/o PAT NR 0 0 =C74 Edge =C74*0.900 ts1 20.000E-09 1 em1_txer i/o PAT NR 0 0 =C75 Edge =C75*0.900 ts1 20.000E-09 1 em1_crs i/o PAT NR 0 =C76*0.250 Off ts1 20.000E-09 1 em1_col i/o PAT NR 0 =C77*0.250 Off ts1 20.000E-09 1 em1_rx_clk i/o PAT NR 0 =C78*0.250 Off ts1 20.000E-09 1 em1_rxd[3] i/o PAT NR 0 0 =C79 Edge =C79*0.900 ts1 20.000E-09 1 em1_rxd[2] i/o PAT NR 0 =C80*0.250 Off ts1 20.000E-09 1 em1_rxd[1] i/o PAT NR 0 =C81*0.250 Off ts1 20.000E-09 1 em1_rxd[0] i/o PAT NR 0 =C82*0.250 Off ts1 20.000E-09 1 em1_rxdv i/o PAT NR 0 =C83*0.250 Off ts1 20.000E-09 1 em1_rxer i/o PAT NR 0 =C84*0.250 Off ts1 20.000E-09 1 em1_mdc i/o PAT NR 0 0 =C85 Edge =C85*0.900 ts1 20.000E-09 1 em1_mdio i/o PAT NR 0 0 =C86 Edge =C86*0.900 ts1 20.000E-09 1 md[15] i/o PAT NR 0 =C87*0.250 =C87 Edge =C87*0.900 ts1 20.000E-09 1 md[14] i/o PAT NR 0 =C88*0.250 =C88 Edge =C88*0.900 ts1 20.000E-09 1 md[13] i/o PAT NR 0 =C89*0.250 =C89 Edge =C89*0.900 ts1 20.000E-09 1 md[12] i/o PAT NR 0 =C90*0.250 =C90 Edge =C90*0.900 ts1 20.000E-09 1 md[11] i/o PAT NR 0 =C91*0.250 =C91 Edge =C91*0.900 ts1 20.000E-09 1 md[10] i/o PAT NR 0 =C92*0.250 =C92 Edge =C92*0.900 ts1 20.000E-09 1 md[9] i/o PAT NR 0 =C93*0.250 =C93 Edge =C93*0.900 ts1 20.000E-09 1 md[8] i/o PAT NR 0 =C94*0.250 =C94 Edge =C94*0.900 ts1 20.000E-09 1 md[7] i/o PAT NR 0 =C95*0.250 =C95 Edge =C95*0.900 ts1 20.000E-09 1 md[6] i/o PAT NR 0 =C96*0.250 =C96 Edge =C96*0.900 ts1 20.000E-09 1 md[5] i/o PAT NR 0 =C97*0.250 =C97 Edge =C97*0.900 ts1 20.000E-09 1 md[4] i/o PAT NR 0 =C98*0.250 =C98 Edge =C98*0.900 ts1 20.000E-09 1 md[3] i/o PAT NR 0 =C99*0.250 =C99 Edge =C99*0.900 ts1 20.000E-09 1 md[2] i/o PAT NR 0 =C100*0.250 =C100 Edge =C100*0.900 ts1 20.000E-09 1 md[1] i/o PAT NR 0 =C101*0.250 =C101 Edge =C101*0.900 ts1 20.000E-09 1 md[0] i/o PAT NR 0 =C102*0.250 =C102 Edge =C102*0.900 ts1 20.000E-09 1 ma[12] i/o PAT NR 0 0 =C103 Edge =C103*0.900 ts1 20.000E-09 1 ma[11] i/o PAT NR 0 0 =C104 Edge =C104*0.900 ts1 20.000E-09 1 ma[10] i/o PAT NR 0 0 =C105 Edge =C105*0.900 ts1 20.000E-09 1 ma[9] i/o PAT NR 0 0 =C106 Edge =C106*0.900 ts1 20.000E-09 1 ma[8] i/o PAT NR 0 0 =C107 Edge =C107*0.900 ts1 20.000E-09 1 ma[7] i/o PAT NR 0 =C108*0.950 Off ts1 20.000E-09 1 ma[6] i/o PAT NR 0 =C109*0.950 Off ts1 20.000E-09 1 ma[5] i/o PAT NR 0 =C110*0.250 =C110 Edge =C110*0.900 ts1 20.000E-09 1 ma[4] i/o PAT NR 0 =C111*0.250 =C111 Edge =C111*0.900 ts1 20.000E-09 1 ma[3] i/o PAT NR 0 =C112*0.250 =C112 Edge =C112*0.900 ts1 20.000E-09 1 ma[2] i/o PAT NR 0 =C113*0.250 =C113 Edge =C113*0.900 ts1 20.000E-09 1 ma[1] i/o PAT NR 0 =C114*0.250 =C114 Edge =C114*0.900 ts1 20.000E-09 1 ma[0] i/o PAT NR 0 =C115*0.250 =C115 Edge =C115*0.900 ts1 20.000E-09 1 mb[1] i/o PAT NR 0 0 =C116 Edge =C116*0.900 ts1 20.000E-09 1 mb[0] i/o PAT NR 0 0 =C117 Edge =C117*0.900 ts1 20.000E-09 1 mm[1] i/o PAT NR 0 0 =C118 Edge =C118*0.900 ts1 20.000E-09 1 mm[0] i/o PAT NR 0 0 =C119 Edge =C119*0.900 ts1 20.000E-09 1 mras_ i/o PAT NR 0 0 =C120 Edge =C120*0.900 ts1 20.000E-09 1 mcas_ i/o PAT NR 0 0 =C121 Edge =C121*0.900 ts1 20.000E-09 1 mwe_ i/o PAT NR 0 0 =C122 Edge =C122*0.900 ts1 20.000E-09 1 mcs_[1] i/o PAT NR 0 0 =C123 Edge =C123*0.900 ts1 20.000E-09 1 mcs_[0] i/o PAT NR 0 0 =C124 Edge =C124*0.900 ts1 20.000E-09 1 mcke i/o PAT NR 0 0 =C125 Edge =C125*0.900 ts1 20.000E-09 1 mclk i/o PAT NR 0 0 =C126 Edge =C126*0.900 ts1 20.000E-09 1 gpio42_40[42] i/o PAT NR 0 0 =C127 Edge =C127*0.900 ts1 20.000E-09 1 gpio42_40[41] i/o PAT NR 0 0 =C128 Edge =C128*0.900 ts1 20.000E-09 1 gpio42_40[40] i/o PAT NR 0 0 =C129 Edge =C129*0.900 ts1 20.000E-09 1 gpio38 i/o PAT NR 0 =C130*0.250 =C130 Edge =C130*0.900 ts1 20.000E-09 1 gpio33 i/o PAT NR 0 =C131*0.250 =C131 Edge =C131*0.900 ts1 20.000E-09 1 gpio26 i/o PAT NR 0 =C132*0.250 Off ts1 20.000E-09 1 gpio25 i/o PAT NR 0 0 =C133 Edge =C133*0.900 ts1 20.000E-09 1 gpio22_13[22] i/o PAT NR 0 0 =C134 Edge =C134*0.900 ts1 20.000E-09 1 gpio22_13[21] i/o PAT NR 0 =C135*0.250 =C135 Edge =C135*0.900 ts1 20.000E-09 1 gpio22_13[20] i/o PAT NR 0 =C136*0.250 =C136 Edge =C136*0.900 ts1 20.000E-09 1 gpio22_13[19] i/o PAT NR 0 0 =C137 Edge =C137*0.900 ts1 20.000E-09 1 gpio22_13[18] i/o PAT NR 0 =C138*0.250 =C138 Edge =C138*0.900 ts1 20.000E-09 1 gpio22_13[17] i/o PAT NR 0 0 =C139 Edge =C139*0.900 ts1 20.000E-09 1 gpio22_13[16] i/o PAT NR 0 =C140*0.250 =C140 Edge =C140*0.900 ts1 20.000E-09 1 gpio22_13[15] i/o PAT NR 0 =C141*0.250 =C141 Edge =C141*0.900 ts1 20.000E-09 1 gpio22_13[14] i/o PAT NR 0 0 =C142 Edge =C142*0.900 ts1 20.000E-09 1 gpio22_13[13] i/o PAT NR 0 0 =C143 Edge =C143*0.900 ts1 20.000E-09 1 gpio8_5[8] i/o PAT NR 0 =C144*0.250 =C144 Edge =C144*0.900 ts1 20.000E-09 1 gpio8_5[7] i/o PAT NR 0 0 =C145 Edge =C145*0.900 ts1 20.000E-09 1 gpio8_5[6] i/o PAT NR 0 0 =C146 Edge =C146*0.900 ts1 20.000E-09 1 gpio8_5[5] i/o PAT NR 0 =C147*0.250 =C147 Edge =C147*0.900 ts1 20.000E-09 1 gpio3 i/o PAT NR 0 0 =C148 Edge =C148*0.900 ts1 20.000E-09 1 gpio2 i/o PAT NR 0 0 =C149 Edge =C149*0.900 ts1 20.000E-09 1 gpio1 i/o PAT NR 0 =C150*0.250 =C150 Edge =C150*0.900 ts1 20.000E-09 1 trst_ i/o PAT NR 0 =C151*0.250 Off ts1 20.000E-09 1 tck i/o PAT NR 0 =C152*0.250 Off ts1 20.000E-09 1 tms i/o PAT NR 0 =C153*0.250 Off ts1 20.000E-09 1 tdi i/o PAT NR 0 =C154*0.250 Off ts1 20.000E-09 1 tdo i/o PAT NR 0 0 =C155 Edge =C155*0.900 ts1 20.000E-09 1 afetx0 i/o PAT NR 0 0 =C156 Edge =C156*0.900 ts1 20.000E-09 1 aferx0 i/o PAT NR 0 0 =C157 Edge =C157*0.900 ts1 20.000E-09 1 aferx1 i/o PAT NR 0 0 =C158 Edge =C158*0.900 ts1 20.000E-09 1 fafe_sclk i/o PAT NR 0 =C159*0.250 Off ts1 20.000E-09 1 fafe_stb i/o PAT NR 0 0 =C160 Edge =C160*0.900 ts1 20.000E-09 1 fafe_ctrlin i/o PAT NR 0 0 =C161 Edge =C161*0.900 ts1 20.000E-09 1 fafe_ctrlout i/o PAT NR 0 =C162*0.250 Off ts1 20.000E-09 1 mon_done i/o PAT NR 0 0 =C163 Edge =C163*0.900 ts1 20.000E-09 1 mon_clk i/o PAT NR 0 0 =C164 Edge =C164*0.900 ts1 20.000E-09 1 mon_out i/o PAT NR 0 0 =C165 Edge =C165*0.900 ts1 20.000E-09 1 vregenn i/o PAT NR 0 =C166*0.250 Off INTERFACES/TERADYNE/EVCDFLEX/file.rpt000064400001440000012000000552771137104243500174320ustar00jcosleystaff00000400000023Statistics Report ****************************************************************************** Converted by Vtran version: 9.1.4 Translation Date: Fri May 7 09:51:41 2010 Vtran Command File: exp1.vtran Source File: ../../DATA/exp1.evcd Output File: exp1.flex ****************************************************************************** ** Command Parameters ** Report File: file.rpt Output and Bidirectional Signals: clk2x vcxo_ctrl bclko had[3[31] had[3[30] had[2[29] had[2[28] had[2[27] had[2[26] had[2[25] had[2[24] had[2[23] had[2[22] had[2[21] had[2[20] had[1[19] had[1[18] had[1[17] had[1[16] hc9_0[[1] fa22 fa23 uart_rx uart_tx em1_txd[[3] em1_txd[[2] em1_txd[[1] em1_txd[[0] em1_tx_en em1_txer em1_rxd[[3] em1_mdc em1_mdio ma[1[12] ma[1[11] ma[1[10] ma[[9] ma[[8] mb[[1] mb[[0] mm[[1] mm[[0] mras_ mcas_ mwe_ mcs_[[1] mcs_[[0] mcke mclk gpio42_40[4[42] gpio42_40[4[41] gpio42_40[4[40] gpio25 gpio22_13[2[22] gpio22_13[1[19] gpio22_13.O[1[18] gpio22_13[1[17] gpio22_13.O[1[16] gpio22_13.O[1[15] gpio22_13[1[14] gpio22_13[1[13] gpio8_5.O[[8] gpio8_5[[7] gpio8_5[[6] gpio8_5.O[[5] gpio3 gpio2 gpio1.O tdo afetx0 aferx0 aferx1 fafe_stb fafe_ctrlin mon_done mon_clk mon_out devid.O[[3] devid.O[[2] devid.O[[1] devid.O[[0] had.O[1[15] had.O[1[14] had.O[1[13] had.O[1[12] had.O[1[11] had.O[1[10] had.O[[9] had.O[[8] had.O[[7] had.O[[6] had.O[[5] had.O[[4] had.O[[3] had.O[[2] had.O[[1] had.O[[0] hc13.O hc11.O hc9_0.O[[9] hc9_0.O[[8] hc9_0.O[[7] hc9_0.O[[6] hc9_0.O[[5] hc9_0.O[[4] hc9_0.O[[3] hc9_0.O[[2] hc9_0.O[[0] usbp.O usbn.O md.O[1[15] md.O[1[14] md.O[1[13] md.O[1[12] md.O[1[11] md.O[1[10] md.O[[9] md.O[[8] md.O[[7] md.O[[6] md.O[[5] md.O[[4] md.O[[3] md.O[[2] md.O[[1] md.O[[0] ma.O[[5] ma.O[[4] ma.O[[3] ma.O[[2] ma.O[[1] ma.O[[0] gpio38.O gpio33.O gpio22_13.O[2[21] gpio22_13.O[2[20] Input and Bidirectional Signals: clki test bopt devid[[3] devid[[2] devid[[1] devid[[0] dsp_only hrst_ had[1[15] had[1[14] had[1[13] had[1[12] had[1[11] had[1[10] had[[9] had[[8] had[[7] had[[6] had[[5] had[[4] had[[3] had[[2] had[[1] had[[0] hc13 hc11 hc9_0[[9] hc9_0[[8] hc9_0[[7] hc9_0[[6] hc9_0[[5] hc9_0[[4] hc9_0[[3] hc9_0[[2] hc9_0[[0] usbp usbn em1_tx_clk em1_crs em1_col em1_rx_clk em1_rxd[[2] em1_rxd[[1] em1_rxd[[0] em1_rxdv em1_rxer md[1[15] md[1[14] md[1[13] md[1[12] md[1[11] md[1[10] md[[9] md[[8] md[[7] md[[6] md[[5] md[[4] md[[3] md[[2] md[[1] md[[0] ma[[7] ma[[6] ma[[5] ma[[4] ma[[3] ma[[2] ma[[1] ma[[0] gpio38 gpio33 gpio26 gpio22_13[2[21] gpio22_13[2[20] gpio22_13[1[18] gpio22_13[1[16] gpio22_13[1[15] gpio8_5[[8] gpio8_5[[5] gpio1 trst_ tck tms tdi fafe_sclk fafe_ctrlout vregenn Bidirectional Signals: devid[[3] devid[[2] devid[[1] devid[[0] had[1[15] had[1[14] had[1[13] had[1[12] had[1[11] had[1[10] had[[9] had[[8] had[[7] had[[6] had[[5] had[[4] had[[3] had[[2] had[[1] had[[0] hc13 hc11 hc9_0[[9] hc9_0[[8] hc9_0[[7] hc9_0[[6] hc9_0[[5] hc9_0[[4] hc9_0[[3] hc9_0[[2] hc9_0[[0] usbp usbn md[1[15] md[1[14] md[1[13] md[1[12] md[1[11] md[1[10] md[[9] md[[8] md[[7] md[[6] md[[5] md[[4] md[[3] md[[2] md[[1] md[[0] ma[[5] ma[[4] ma[[3] ma[[2] ma[[1] ma[[0] gpio38 gpio33 gpio22_13[2[21] gpio22_13[2[20] gpio22_13[1[18] gpio22_13[1[16] gpio22_13[1[15] gpio8_5[[8] gpio8_5[[5] gpio1 logic0 states: 0DL logic1 states: 1UH Start Time: 0ns End Time: 4920ns The report below provides statistics first for output and bidirectional signals, then for input and bidirectional signals, then for bidirectional signals. For output and bidirectional signals, the entries list the number of compares to a logic-0 state, the cycle time of the first comparison, the number of compares to a logic-1 state, and the cycle time of the first comparison. For input and bidirectional signals, the entries list the number of transitions from a logic-1 state to a logic-0 state, the cycle time of the first of these transitions, the number of transitions from a logic-0 state to a logic-1 state, and the cycle time of the first of these transitions. A transition from other states (such as X or Z) will be counted only if preceded by the opposite state. For bidirectional signals, the entries list the number of transitions from an input state to an output state, the cycle time of the first of these transitions, the number of transitions from an output state to an input state, and the cycle time of the first of these transitions. Vectors with Z or X states on both input and output parts are ignored. logic 1 logic 0 Signal Name (first compare) (first compare) ----------- --------------- --------------- clk2x 0 0 vcxo_ctrl 0 246 (20ns) bclko 105 (740ns) 141 (20ns) had[3[31] 94 (20ns) 105 (2080ns) had[3[30] 94 (20ns) 105 (2080ns) had[2[29] 94 (20ns) 105 (2080ns) had[2[28] 0 199 (20ns) had[2[27] 0 199 (20ns) had[2[26] 0 199 (20ns) had[2[25] 0 199 (20ns) had[2[24] 0 199 (20ns) had[2[23] 0 199 (20ns) had[2[22] 0 199 (20ns) had[2[21] 0 199 (20ns) had[2[20] 0 199 (20ns) had[1[19] 0 199 (20ns) had[1[18] 0 199 (20ns) had[1[17] 0 199 (20ns) had[1[16] 0 199 (20ns) hc9_0[[1] 152 (1900ns) 94 (20ns) fa22 0 246 (20ns) fa23 0 246 (20ns) uart_rx 0 0 uart_tx 0 246 (20ns) em1_txd[[3] 0 246 (20ns) em1_txd[[2] 0 246 (20ns) em1_txd[[1] 0 246 (20ns) em1_txd[[0] 0 246 (20ns) em1_tx_en 0 246 (20ns) em1_txer 0 246 (20ns) em1_rxd[[3] 0 0 em1_mdc 0 246 (20ns) em1_mdio 0 0 ma[1[12] 0 246 (20ns) ma[1[11] 0 236 (20ns) ma[1[10] 0 236 (20ns) ma[[9] 0 236 (20ns) ma[[8] 0 236 (20ns) mb[[1] 0 236 (20ns) mb[[0] 0 236 (20ns) mm[[1] 246 (20ns) 0 mm[[0] 246 (20ns) 0 mras_ 246 (20ns) 0 mcas_ 246 (20ns) 0 mwe_ 246 (20ns) 0 mcs_[[1] 246 (20ns) 0 mcs_[[0] 246 (20ns) 0 mcke 0 246 (20ns) mclk 106 (720ns) 141 (0ns) gpio42_40[4[42] 0 0 gpio42_40[4[41] 0 0 gpio42_40[4[40] 0 0 gpio25 0 0 gpio22_13[2[22] 0 0 gpio22_13[1[19] 246 (20ns) 0 gpio22_13.O[1[18] 0 105 (2080ns) gpio22_13[1[17] 152 (1900ns) 94 (20ns) gpio22_13.O[1[16] 0 105 (2080ns) gpio22_13.O[1[15] 8 (2840ns) 97 (2080ns) gpio22_13[1[14] 0 0 gpio22_13[1[13] 0 0 gpio8_5.O[[8] 9 (4640ns) 96 (2080ns) gpio8_5[[7] 246 (20ns) 0 gpio8_5[[6] 0 0 gpio8_5.O[[5] 28 (2840ns) 77 (2080ns) gpio3 0 0 gpio2 0 0 gpio1.O 0 199 (20ns) tdo 0 0 afetx0 0 0 aferx0 0 0 aferx1 0 0 fafe_stb 0 0 fafe_ctrlin 0 0 mon_done 0 246 (20ns) mon_clk 0 246 (20ns) mon_out 0 246 (20ns) 247 (0ns) 0 0 247 (0ns) 0 0 0 0 0 0 0 0 devid.O[[3] 0 0 devid.O[[2] 0 0 devid.O[[1] 0 0 devid.O[[0] 0 0 had.O[1[15] 0 105 (2080ns) had.O[1[14] 0 105 (2080ns) had.O[1[13] 0 105 (2080ns) had.O[1[12] 0 105 (2080ns) had.O[1[11] 0 105 (2080ns) had.O[1[10] 0 105 (2080ns) had.O[[9] 0 105 (2080ns) had.O[[8] 6 (3520ns) 97 (2080ns) had.O[[7] 6 (3520ns) 97 (2080ns) had.O[[6] 2 (4880ns) 103 (2080ns) had.O[[5] 5 (4640ns) 96 (2080ns) had.O[[4] 0 105 (2080ns) had.O[[3] 11 (3960ns) 85 (2080ns) had.O[[2] 17 (3280ns) 77 (2080ns) had.O[[1] 0 105 (2080ns) had.O[[0] 2 (4880ns) 103 (2080ns) hc13.O 0 0 hc11.O 0 0 hc9_0.O[[9] 0 0 hc9_0.O[[8] 0 0 hc9_0.O[[7] 0 0 hc9_0.O[[6] 0 0 hc9_0.O[[5] 0 0 hc9_0.O[[4] 0 0 hc9_0.O[[3] 0 0 hc9_0.O[[2] 0 105 (2080ns) hc9_0.O[[0] 0 0 usbp.O 0 0 usbn.O 0 0 md.O[1[15] 0 105 (2080ns) md.O[1[14] 0 105 (2080ns) md.O[1[13] 0 105 (2080ns) md.O[1[12] 0 105 (2080ns) md.O[1[11] 0 105 (2080ns) md.O[1[10] 0 105 (2080ns) md.O[[9] 0 105 (2080ns) md.O[[8] 0 105 (2080ns) md.O[[7] 0 105 (2080ns) md.O[[6] 0 105 (2080ns) md.O[[5] 0 105 (2080ns) md.O[[4] 0 105 (2080ns) md.O[[3] 0 105 (2080ns) md.O[[2] 0 105 (2080ns) md.O[[1] 0 105 (2080ns) md.O[[0] 0 105 (2080ns) ma.O[[5] 0 105 (2080ns) ma.O[[4] 8 (2840ns) 97 (2080ns) ma.O[[3] 2 (4880ns) 103 (2080ns) ma.O[[2] 20 (3960ns) 85 (2080ns) ma.O[[1] 0 105 (2080ns) ma.O[[0] 2 (4880ns) 103 (2080ns) gpio38.O 0 199 (20ns) gpio33.O 0 105 (2080ns) gpio22_13.O[2[21] 0 105 (2080ns) gpio22_13.O[2[20] 0 105 (2080ns) transitions to logic 1 transitions to logic 0 Signal Name (first transition) (first transition) ----------- ---------------------- ---------------------- clki 0 0 test 0 0 bopt 0 0 devid[[3] 0 0 devid[[2] 0 0 devid[[1] 0 0 devid[[0] 0 0 dsp_only 0 0 hrst_ 1 (640ns) 0 had[1[15] 0 0 had[1[14] 0 0 had[1[13] 0 0 had[1[12] 0 0 had[1[11] 0 0 had[1[10] 0 0 had[[9] 0 0 had[[8] 0 0 had[[7] 0 0 had[[6] 0 0 had[[5] 0 0 had[[4] 0 0 had[[3] 0 0 had[[2] 0 0 had[[1] 0 0 had[[0] 0 0 hc13 0 0 hc11 0 0 hc9_0[[9] 0 0 hc9_0[[8] 0 0 hc9_0[[7] 0 0 hc9_0[[6] 0 0 hc9_0[[5] 0 0 hc9_0[[4] 0 0 hc9_0[[3] 0 0 hc9_0[[2] 0 0 hc9_0[[0] 0 0 usbp 0 0 usbn 0 0 em1_tx_clk 0 0 em1_crs 0 0 em1_col 0 0 em1_rx_clk 0 0 em1_rxd[[2] 0 0 em1_rxd[[1] 0 0 em1_rxd[[0] 0 0 em1_rxdv 0 0 em1_rxer 0 0 md[1[15] 0 0 md[1[14] 3 (2920ns) 3 (2960ns) md[1[13] 3 (2920ns) 3 (2960ns) md[1[12] 1 (2040ns) 0 md[1[11] 1 (2040ns) 0 md[1[10] 0 0 md[[9] 1 (2040ns) 0 md[[8] 1 (2360ns) 1 (2040ns) md[[7] 3 (2920ns) 3 (2960ns) md[[6] 3 (2920ns) 3 (2960ns) md[[5] 4 (2360ns) 3 (2920ns) md[[4] 3 (2920ns) 3 (2960ns) md[[3] 0 0 md[[2] 3 (2920ns) 3 (2960ns) md[[1] 1 (2040ns) 0 md[[0] 0 0 ma[[7] 17 (2020ns) 18 (1980ns) ma[[6] 17 (2260ns) 17 (2020ns) ma[[5] 3 (2920ns) 3 (2960ns) ma[[4] 1 (2000ns) 1 (2040ns) ma[[3] 1 (2000ns) 1 (2040ns) ma[[2] 4 (2000ns) 4 (2040ns) ma[[1] 0 0 ma[[0] 4 (2000ns) 3 (2920ns) gpio38 3 (2920ns) 3 (2960ns) gpio33 3 (2920ns) 3 (2960ns) gpio26 1 (20ns) 0 gpio22_13[2[21] 3 (2920ns) 3 (2960ns) gpio22_13[2[20] 1 (2040ns) 0 gpio22_13[1[18] 0 0 gpio22_13[1[16] 0 0 gpio22_13[1[15] 0 0 gpio8_5[[8] 9 (2000ns) 9 (2040ns) gpio8_5[[5] 4 (2360ns) 3 (2920ns) gpio1 0 0 trst_ 0 0 tck 0 0 tms 0 0 tdi 0 0 fafe_sclk 0 0 fafe_ctrlout 0 0 vregenn 0 0 transitions to input transitions to output Signal Name (first transition) (first transition) ----------- -------------------- --------------------- devid[[3] 0 0 devid[[2] 0 0 devid[[1] 0 0 devid[[0] 0 0 had[1[15] 16 (2180ns) 17 (2080ns) had[1[14] 16 (2180ns) 17 (2080ns) had[1[13] 16 (2180ns) 17 (2080ns) had[1[12] 16 (2180ns) 17 (2080ns) had[1[11] 16 (2180ns) 17 (2080ns) had[1[10] 16 (2180ns) 17 (2080ns) had[[9] 16 (2180ns) 17 (2080ns) had[[8] 16 (2180ns) 17 (2080ns) had[[7] 16 (2180ns) 17 (2080ns) had[[6] 16 (2180ns) 17 (2080ns) had[[5] 16 (2180ns) 17 (2080ns) had[[4] 16 (2180ns) 17 (2080ns) had[[3] 16 (2180ns) 17 (2080ns) had[[2] 16 (2180ns) 17 (2080ns) had[[1] 16 (2180ns) 17 (2080ns) had[[0] 16 (2180ns) 17 (2080ns) hc13 0 0 hc11 0 0 hc9_0[[9] 0 0 hc9_0[[8] 0 0 hc9_0[[7] 0 0 hc9_0[[6] 0 0 hc9_0[[5] 0 0 hc9_0[[4] 0 0 hc9_0[[3] 0 0 hc9_0[[2] 16 (2360ns) 17 (2080ns) hc9_0[[0] 0 0 usbp 0 0 usbn 0 0 md[1[15] 16 (2360ns) 17 (2080ns) md[1[14] 16 (2360ns) 17 (2080ns) md[1[13] 16 (2360ns) 17 (2080ns) md[1[12] 16 (2360ns) 17 (2080ns) md[1[11] 16 (2360ns) 17 (2080ns) md[1[10] 16 (2360ns) 17 (2080ns) md[[9] 16 (2360ns) 17 (2080ns) md[[8] 16 (2360ns) 17 (2080ns) md[[7] 16 (2360ns) 17 (2080ns) md[[6] 16 (2360ns) 17 (2080ns) md[[5] 16 (2360ns) 17 (2080ns) md[[4] 16 (2360ns) 17 (2080ns) md[[3] 16 (2360ns) 17 (2080ns) md[[2] 16 (2360ns) 17 (2080ns) md[[1] 16 (2360ns) 17 (2080ns) md[[0] 16 (2360ns) 17 (2080ns) ma[[5] 16 (2360ns) 17 (2080ns) ma[[4] 16 (2360ns) 17 (2080ns) ma[[3] 16 (2360ns) 17 (2080ns) ma[[2] 16 (2360ns) 17 (2080ns) ma[[1] 16 (2360ns) 17 (2080ns) ma[[0] 16 (2360ns) 17 (2080ns) gpio38 17 (1960ns) 17 (2080ns) gpio33 16 (2360ns) 17 (2080ns) gpio22_13[2[21] 16 (2360ns) 17 (2080ns) gpio22_13[2[20] 16 (2360ns) 17 (2080ns) gpio22_13[1[18] 16 (2360ns) 17 (2080ns) gpio22_13[1[16] 16 (2360ns) 17 (2080ns) gpio22_13[1[15] 16 (2360ns) 17 (2080ns) gpio8_5[[8] 16 (2360ns) 17 (2080ns) gpio8_5[[5] 16 (2360ns) 17 (2080ns) gpio1 17 (1960ns) 17 (2080ns) 105 (2080ns) md.O[[1] 0 105 (2080ns) md.O[[0] 0 105 (2080ns) ma.O[[5] 0 105 (2080ns) ma.O[[4] 8 (2840ns) 97 (2080ns) ma.O[[3] 2 (4880nsINTERFACES/TERADYNE/STILFLEX/000075500001440000012000000000001121203362300157675ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/STILFLEX/exp1.vtran000064400001440000012000000050161103104161000177140ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp1.flex " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'FLEX' #### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0', 'X'->'0' ; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block tester_format teradyne {#### OUTPUT FORMAT ####} -FLEX, -AUTO_GROUP, -USE_TSET_NAMES, WR_TIMESET_FILE = "exp1" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp1.flex"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TERADYNE/STILFLEX/exp2.vtran000064400001440000012000000050031103104161000177110ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp2.flex " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'FLEX' #### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0', 'X'->'0' ; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format teradyne {#### OUTPUT FORMAT ####} -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp2" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp2.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/STILFLEX/exp3.vtran000064400001440000012000000050111103104161000177110ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > CATALYST # # Original File: "exp1.stil" # # Target File: "exp3.flex " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format CATALYST # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'FLEX' #### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0', 'X'->'0' ; state_trans outputs 'T'->'X', 'x'->'X', 'l'->'L', 'h'->'H', 't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin tester_format teradyne {#### OUTPUT FORMAT ####} -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp3" {#### TIMING DATA FOR VECTOR FILE "exp1.stil" ####} ; target_file = "exp3.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLFLEX/000075500001440000012000000000001103104161000156375ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/WGLFLEX/exp1.vtran000064400001440000012000000046611103104161000175770ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > FLEX # # Original File: "exp1.wgl" # # Target File: "exp1.flex " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -expand_loops -expand_reps; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'FLEX' #### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; TESTER_FORMAT TERADYNE -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp1" ; {#### OUTPUT FORMAT ####} target_file "exp1.formula.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLFLEX/exp2.vtran000064400001440000012000000046271103104161000176020ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > FLEX # # Original File: "exp1.wgl" # # Target File: "exp2.flex " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'FLEX' #### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; TESTER_FORMAT TERADYNE -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp2" ; {#### OUTPUT FORMAT ####} target_file "exp2.formula.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/WGLFLEX/exp3.vtran000064400001440000012000000046351103104161000176020ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > FLEX # # Original File: "exp1.wgl" # # Target File: "exp3.flex " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl -CYCLE -scan ; {#### INPUT FORMAT ####} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into FLEX format # #======================================================================# } proc_block begin { #### state character translations for 'WGL'->'FLEX' #### } state_trans pure_inputs '-'->'0', 'X'->'0'; state_trans bidir_inputs '-'->'Z', 'X'->'0'; state_trans outputs '0'->'L', '1'->'H', 'Z'->'X', '-'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; rename_bus_pins $bus_$vec; TESTER_FORMAT TERADYNE -FLEX, -AUTO_GROUP -USE_TSET_NAMES -BASIC_TIMING_FORMULAS WR_TIMESET_FILE = "exp3" ; {#### OUTPUT FORMAT ####} target_file "exp3.formula.flex"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/FLEXSTIL/000075500001440000012000000000001103104161000157615ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/FLEXSTIL/cyc1.teratim_tsets.txt000064400001440000012000000035411103104161000222520ustar00jcosleystaff00000400000023DFF 1.3 Time Sets Timing Mode: Single Master Timeset Name: Time Domain: Cycle Pin Group Time Set Period Name Clock Period Setup Edge Set Comment TS1 90.0E-09 out0 i/o es1 TS1 90.0E-09 out1 i/o es1 TS1 90.0E-09 out2 i/o es1 TS1 90.0E-09 in0 i/o es1 TS1 90.0E-09 in1 i/o es1 TS1 90.0E-09 in2 i/o es1 TS1 90.0E-09 clk1 i/o es1 TS1 90.0E-09 clk2 i/o es1 TS1 90.0E-09 SDI0 i/o es1 TS1 90.0E-09 SDI1 i/o es1 TS1 90.0E-09 SDO0 i/o es1 TS1 90.0E-09 SDO1 i/o es1 TS1 90.0E-09 ACK0 i/o es1 TS1 90.0E-09 BCK0 i/o es1 TS2 90.0E-09 out0 i/o es2 TS2 90.0E-09 out1 i/o es2 TS2 90.0E-09 out2 i/o es2 TS2 90.0E-09 in0 i/o es2 TS2 90.0E-09 in1 i/o es2 TS2 90.0E-09 in2 i/o es2 TS2 90.0E-09 clk1 i/o es2 TS2 90.0E-09 clk2 i/o es2 TS2 90.0E-09 SDI0 i/o es2 TS2 90.0E-09 SDI1 i/o es2 TS2 90.0E-09 SDO0 i/o es2 TS2 90.0E-09 SDO1 i/o es2 TS2 90.0E-09 ACK0 i/o es2 TS2 90.0E-09 BCK0 i/o es2 TS3 110.0E-09 out0 i/o es3 TS3 110.0E-09 out1 i/o es3 TS3 110.0E-09 out2 i/o es3 TS3 110.0E-09 in0 i/o es3 TS3 110.0E-09 in1 i/o es3 TS3 110.0E-09 in2 i/o es3 TS3 110.0E-09 clk1 i/o es3 TS3 110.0E-09 clk2 i/o es3 TS3 110.0E-09 SDI0 i/o es3 TS3 110.0E-09 SDI1 i/o es3 TS3 110.0E-09 SDO0 i/o es3 TS3 110.0E-09 SDO1 i/o es3 TS3 110.0E-09 ACK0 i/o es3 TS3 110.0E-09 BCK0 i/o es3 TS4 100.0E-09 out0 i/o es4 TS4 100.0E-09 out1 i/o es4 TS4 100.0E-09 out2 i/o es4 TS4 100.0E-09 in0 i/o es4 TS4 100.0E-09 in1 i/o es4 TS4 100.0E-09 in2 i/o es4 TS4 100.0E-09 clk1 i/o es4 TS4 100.0E-09 clk2 i/o es4 TS4 100.0E-09 SDI0 i/o es4 TS4 100.0E-09 SDI1 i/o es4 TS4 100.0E-09 SDO0 i/o es4 TS4 100.0E-09 SDO1 i/o es4 TS4 100.0E-09 ACK0 i/o es4 TS4 100.0E-09 BCK0 i/o es4 INTERFACES/TERADYNE/FLEXSTIL/cyc1.vtran000064400001440000012000000051221103104161000176740ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne FLEX # # translating to STIL. # # Translation: FLEX < to > STIL # # Original File: "cyc1.flex" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc1.stil " # # Command File: "cyc1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.flex"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format FLEX -cycle -expand_reps; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FLEX # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'FLEX'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/FLEXSTIL/cyc1.flex000064400001440000012000000051041103104161000175000ustar00jcosleystaff00000400000023// // Converted by vtran version: 7.6.1 // Date: Tue Sep 12 10:14:41 2006 // Source file: loopsRT.stil // Filetype: FLEX // digital_inst = hsd800; opcode_mode = single; import tset TS1, TS2, TS3, TS4 ; vm_vector ($tset (out0, out1, out2), (in0, in1, in2), (clk1, clk2), (SDI0, SDI1), (SDO0, SDO1), ACK0, BCK0 ) { > 4 XXX NNN 00 NN XX 0 0 ; // 0 > 4 XXX NNN 00 00 XX 1 1 ; // 100 > 4 XXX NNN 00 00 XX 1 1 ; // 200 > 4 XXX NNN 00 10 XX 1 1 ; // 300 > 4 XXX NNN 00 01 XX 1 1 ; // 400 > 4 XXX 010 00 11 XX 0 0 ; // 500 > 1 XXX 100 00 10 XX 0 0 ; // 600 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 690 > 4 XXX NNN 11 NN XX 0 0 ; // 1890 > 4 XXX NNN 01 NN XX 0 1 ; // 1990 > 1 XXX 100 00 10 XX 0 0 ; // 2090 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 2180 > 4 XXX NNN 01 NN XX 1 1 ; // 3380 > 1 XXX 100 00 10 XX 0 0 ; // 3480 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 3570 > 4 XXX NNN 01 NN XX 1 1 ; // 4770 > 4 XXX NNN 10 NN XX 0 1 ; // 4870 > 4 XXX NNN 01 NN XX 0 1 ; // 4970 > 1 XXX 100 00 10 XX 0 0 ; // 5070 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 5160 > 4 XXX NNN 01 NN XX 1 1 ; // 6360 > 1 XXX 100 00 10 XX 0 0 ; // 6460 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 6550 > 4 XXX NNN 01 NN XX 1 1 ; // 7750 > 4 XXX NNN 10 NN XX 0 1 ; // 7850 > 4 XXX NNN 01 NN XX 0 1 ; // 7950 > 1 XXX 100 00 10 XX 0 0 ; // 8050 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 8140 > 4 XXX NNN 01 NN XX 1 1 ; // 9340 > 1 XXX 100 00 10 XX 0 0 ; // 9440 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 9530 > 4 XXX NNN 01 NN XX 1 1 ; // 10730 > 4 XXX NNN 10 NN XX 0 1 ; // 10830 > 4 XXX NNN 01 NN XX 0 1 ; // 10930 > 1 XXX 100 00 10 XX 0 0 ; // 11030 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 11120 > 4 XXX NNN 01 NN XX 1 1 ; // 12320 > 1 XXX 100 00 10 XX 0 0 ; // 12420 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 12510 > 4 XXX NNN 01 NN XX 1 1 ; // 13710 > 4 XXX NNN 10 NN XX 0 1 ; // 13810 > 4 XXX NNN 01 NN XX 0 1 ; // 13910 > 1 XXX 100 00 10 XX 0 0 ; // 14010 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 14100 > 4 XXX NNN 01 NN XX 1 1 ; // 15300 > 1 XXX 100 00 10 XX 0 0 ; // 15400 repeat 12 > 4 XXX NNN 00 NN XX 0 1 ; // 15490 > 4 XXX NNN 01 NN XX 1 1 ; // 16690 > 4 XXX NNN 10 NN XX 0 1 ; // 16790 > 4 XXX NNN 01 NN XX 0 1 ; // 16890 > 4 XXX 100 00 00 XX 1 1 ; // 16990 > 4 XXX 100 00 00 XX 1 1 ; // 17090 > 4 XXX 100 00 00 HX 1 1 ; // 17190 > 4 XXX 100 00 00 LX 1 1 ; // 17290 > 4 XXX NNN 01 NN XX 1 1 ; // 17390 > 4 XXX NNN 01 NN XX 0 0 ; // 17490 } INTERFACES/TERADYNE/FLEXSTIL/cyc1.teratim_esets.txt000064400001440000012000000052001103104161000222250ustar00jcosleystaff00000400000023DFF 1.3 Edge Sets Timing Mode: Single Time Domain: Data Drive Compare Edge Resolution Pin/Group Edge Set Src Fmt On Data Return Off Mode Open Close Mode Comment out0 es1 PAT NR 0 0 0 Edge 10.0E-09 Auto out0 es2 PAT NR 0 0 0 Edge 10.0E-09 Auto out0 es3 PAT NR 0 0 0 Edge 10.0E-09 Auto out0 es4 PAT NR 0 0 0 Edge 10.0E-09 Auto out1 es1 PAT NR 0 0 0 Edge 10.0E-09 Auto out1 es2 PAT NR 0 0 0 Edge 10.0E-09 Auto out1 es3 PAT NR 0 0 0 Edge 10.0E-09 Auto out1 es4 PAT NR 0 0 0 Edge 10.0E-09 Auto out2 es1 PAT NR 0 0 0 Edge 10.0E-09 Auto out2 es2 PAT NR 0 0 0 Edge 10.0E-09 Auto out2 es3 PAT NR 0 0 0 Edge 10.0E-09 Auto out2 es4 PAT NR 0 0 0 Edge 10.0E-09 Auto in0 es1 PAT NR 0 0 Off Auto in0 es2 PAT NR 0 0 Off Auto in0 es3 PAT NR 0 0 Off Auto in0 es4 PAT NR 0 0 Off Auto in1 es1 PAT NR 0 0 Off Auto in1 es2 PAT NR 0 0 Off Auto in1 es3 PAT NR 0 0 Off Auto in1 es4 PAT NR 0 0 Off Auto in2 es1 PAT NR 0 0 Off Auto in2 es2 PAT NR 0 0 Off Auto in2 es3 PAT NR 0 0 Off Auto in2 es4 PAT NR 0 0 Off Auto clk1 es1 PAT RL 0 70.0E-09 80.0E-09 Off Auto clk1 es2 PAT RL 0 70.0E-09 80.0E-09 Off Auto clk1 es3 PAT RL 0 20.0E-09 30.0E-09 Off Auto clk1 es4 PAT RL 0 50.0E-09 80.0E-09 Off Auto clk2 es1 PAT RL 0 70.0E-09 80.0E-09 Off Auto clk2 es2 PAT RL 0 70.0E-09 80.0E-09 Off Auto clk2 es3 PAT RL 0 20.0E-09 30.0E-09 Off Auto clk2 es4 PAT RL 0 50.0E-09 80.0E-09 Off Auto SDI0 es1 PAT NR 0 0 Off Auto SDI0 es2 PAT NR 0 0 Off Auto SDI0 es3 PAT NR 0 0 Off Auto SDI0 es4 PAT NR 0 0 Off Auto SDI1 es1 PAT NR 0 0 Off Auto SDI1 es2 PAT NR 0 0 Off Auto SDI1 es3 PAT NR 0 0 Off Auto SDI1 es4 PAT NR 0 0 Off Auto SDO0 es1 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO0 es2 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO0 es3 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO0 es4 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO1 es1 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO1 es2 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO1 es3 PAT NR 0 0 0 Edge 10.0E-09 Auto SDO1 es4 PAT NR 0 0 0 Edge 10.0E-09 Auto ACK0 es1 PAT RL 0 20.0E-09 30.0E-09 Off Auto ACK0 es2 PAT RL 0 20.0E-09 30.0E-09 Off Auto ACK0 es3 PAT RL 0 20.0E-09 30.0E-09 Off Auto ACK0 es4 PAT RL 0 20.0E-09 30.0E-09 Off Auto BCK0 es1 PAT RL 0 60.0E-09 70.0E-09 Off Auto BCK0 es2 PAT RL 0 60.0E-09 70.0E-09 Off Auto BCK0 es3 PAT RL 0 60.0E-09 70.0E-09 Off Auto BCK0 es4 PAT RL 0 60.0E-09 70.0E-09 Off Auto INTERFACES/TERADYNE/FLEXSTIL/cyc2.vtran000064400001440000012000000047751103104161000177120ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne FLEX # # translating to STIL. # # Translation: FLEX < to > STIL # # Original File: "cyc1.flex" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc2.stil " # # Command File: "cyc2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.flex"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format FLEX -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FLEX # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'FLEX'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/FLEXSTIL/scan1.vtran000064400001440000012000000051421103104161000200440ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne FLEX # # translating to STIL. # # Translation: FLEX < to > STIL # # Original File: "scan1.flex" # # Auxilary File: "scan1.teratim" # # Target File: "scan1.stil " # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.flex"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.flex"; {#### AUX VECTOR FILE ####} tabular_format FLEX -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FLEX # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'FLEX'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "scan1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750PLUSSTIL/000075500001440000012000000000001103104161000163545ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/J750PLUSSTIL/cyc1.j750000064400001440000012000000024441103104161000176260ustar00jcosleystaff00000400000023/* ** Converted by vtran version: 8.0.1 ** Date: Mon Nov 5 13:37:50 2007 ** Source file: ../Data/Ref2.wgl ** Filetype: J750 */ import tset _launch_capture_WFT_, _launch_WFT_, _capture_WFT_, _default_WFT_ ; vector ($tset (out0, out1, out2), (in0, in1, in2), (clk1, clk2), (SDI0, SDI1), (SDO0, SDO1), ACK0, BCK0 ) { > _default_WFT_ XXX XXX 00 XX XX 0 0 ; /* 0 */ > _default_WFT_ XXX XXX 00 00 XX 1 1 ; /* 100 */ > _default_WFT_ XXX XXX 00 00 XX 1 1 ; /* 200 */ > _default_WFT_ XXX XXX 00 10 XX 1 1 ; /* 300 */ > _default_WFT_ XXX XXX 00 01 XX 1 1 ; /* 400 */ > _default_WFT_ XXX 010 00 11 XX 0 0 ; /* 500 */ > _launch_capture_WFT_ XXX 100 00 10 XX 0 0 ; /* 600 */ repeat 12 > _default_WFT_ XXX XXX 00 XX XX 0 1 ; /* 690 */ > _default_WFT_ XXX XXX 11 XX XX 0 0 ; /* 1890 */ LabelAA: loopA 5 > _default_WFT_ XXX XXX 01 XX XX 0 1 ; /* 1990 */ > _default_WFT_ XXX XXX 10 XX XX 0 1 ; /* 2090 */ end_loopA LabelAA > _default_WFT_ XXX XXX 01 XX XX 0 1 ; /* 2990 */ > _default_WFT_ XXX 100 00 00 XX 1 1 ; /* 3090 */ > _default_WFT_ XXX 100 00 00 XX 1 1 ; /* 3190 */ > _default_WFT_ XXX 100 00 00 HX 1 1 ; /* 3290 */ > _default_WFT_ XXX 100 00 00 LX 1 1 ; /* 3390 */ > _default_WFT_ XXX XXX 01 XX XX 1 1 ; /* 3490 */ > _default_WFT_ XXX XXX 01 XX XX 0 0 ; /* 3590 */ } INTERFACES/TERADYNE/J750PLUSSTIL/cyc1.vtran000064400001440000012000000051421103104161000202710ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750+ # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "cyc1.j750" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc1.stil " # # Command File: "cyc1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.j750"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format J750+ -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750+ # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750+'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750PLUSSTIL/cyc1.teratim_tsets.txt000064400001440000012000000046651103104161000226550ustar00jcosleystaff00000400000023DFF 1.1 Time Sets Timing Mode: Extended Cycle Pin Group Time Set Period CPP Name Setup Edge Set Comment _launch_capture_WFT_ 90.0E-09 out0 i/o es1 _launch_capture_WFT_ 90.0E-09 out1 i/o es1 _launch_capture_WFT_ 90.0E-09 out2 i/o es1 _launch_capture_WFT_ 90.0E-09 in0 i/o es1 _launch_capture_WFT_ 90.0E-09 in1 i/o es1 _launch_capture_WFT_ 90.0E-09 in2 i/o es1 _launch_capture_WFT_ 90.0E-09 clk1 i/o es1 _launch_capture_WFT_ 90.0E-09 clk2 i/o es1 _launch_capture_WFT_ 90.0E-09 SDI0 i/o es1 _launch_capture_WFT_ 90.0E-09 SDI1 i/o es1 _launch_capture_WFT_ 90.0E-09 SDO0 i/o es1 _launch_capture_WFT_ 90.0E-09 SDO1 i/o es1 _launch_capture_WFT_ 90.0E-09 ACK0 i/o es1 _launch_capture_WFT_ 90.0E-09 BCK0 i/o es1 _launch_WFT_ 90.0E-09 out0 i/o es2 _launch_WFT_ 90.0E-09 out1 i/o es2 _launch_WFT_ 90.0E-09 out2 i/o es2 _launch_WFT_ 90.0E-09 in0 i/o es2 _launch_WFT_ 90.0E-09 in1 i/o es2 _launch_WFT_ 90.0E-09 in2 i/o es2 _launch_WFT_ 90.0E-09 clk1 i/o es2 _launch_WFT_ 90.0E-09 clk2 i/o es2 _launch_WFT_ 90.0E-09 SDI0 i/o es2 _launch_WFT_ 90.0E-09 SDI1 i/o es2 _launch_WFT_ 90.0E-09 SDO0 i/o es2 _launch_WFT_ 90.0E-09 SDO1 i/o es2 _launch_WFT_ 90.0E-09 ACK0 i/o es2 _launch_WFT_ 90.0E-09 BCK0 i/o es2 _capture_WFT_ 110.0E-09 out0 i/o es3 _capture_WFT_ 110.0E-09 out1 i/o es3 _capture_WFT_ 110.0E-09 out2 i/o es3 _capture_WFT_ 110.0E-09 in0 i/o es3 _capture_WFT_ 110.0E-09 in1 i/o es3 _capture_WFT_ 110.0E-09 in2 i/o es3 _capture_WFT_ 110.0E-09 clk1 i/o es3 _capture_WFT_ 110.0E-09 clk2 i/o es3 _capture_WFT_ 110.0E-09 SDI0 i/o es3 _capture_WFT_ 110.0E-09 SDI1 i/o es3 _capture_WFT_ 110.0E-09 SDO0 i/o es3 _capture_WFT_ 110.0E-09 SDO1 i/o es3 _capture_WFT_ 110.0E-09 ACK0 i/o es3 _capture_WFT_ 110.0E-09 BCK0 i/o es3 _default_WFT_ 100.0E-09 out0 i/o es4 _default_WFT_ 100.0E-09 out1 i/o es4 _default_WFT_ 100.0E-09 out2 i/o es4 _default_WFT_ 100.0E-09 in0 i/o es4 _default_WFT_ 100.0E-09 in1 i/o es4 _default_WFT_ 100.0E-09 in2 i/o es4 _default_WFT_ 100.0E-09 clk1 i/o es4 _default_WFT_ 100.0E-09 clk2 i/o es4 _default_WFT_ 100.0E-09 SDI0 i/o es4 _default_WFT_ 100.0E-09 SDI1 i/o es4 _default_WFT_ 100.0E-09 SDO0 i/o es4 _default_WFT_ 100.0E-09 SDO1 i/o es4 _default_WFT_ 100.0E-09 ACK0 i/o es4 _default_WFT_ 100.0E-09 BCK0 i/o es4 es2 _launch_WFT_ 90.0E-09 in1 i/o es2 _launch_WFT_ 90.0E-09 in2 i/oINTERFACES/TERADYNE/J750PLUSSTIL/scan1.vtran000064400001440000012000000050061103104161000204360ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "scan1.tp" # # Auxilary File: "scan1.tim" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.j750"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.j750PLUS"; {#### AUX VECTOR FILE ####} tabular_format J750+ -cycle -scan ; {#### INPUT FORMAT ####} BIDIRECTS data_7, data_6, data_5, data_4, data_3, data_2, data_1, data_0; end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into STIL format # #======================================================================# } proc_block begin; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "scan1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750PLUSSTIL/cyc2.vtran000064400001440000012000000050001103104161000202630ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750+ # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "cyc1.j750" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc2.stil " # # Command File: "cyc2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.j750"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format J750+ -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750+ # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750+'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750PLUSSTIL/cyc1.teratim_esets.txt000064400001440000012000000044661103104161000226350ustar00jcosleystaff00000400000023DFF 1.1 Edge Sets Timing Mode: Extended Data Drive Compare Pin/Group Edge Set Src Fmt On Data Return Off Mode Open Close Comment out0 es1 PAT NR 0 0 0 Edge 10.0E-09 out0 es2 PAT NR 0 0 0 Edge 10.0E-09 out0 es3 PAT NR 0 0 0 Edge 10.0E-09 out0 es4 PAT NR 0 0 0 Edge 10.0E-09 out1 es1 PAT NR 0 0 0 Edge 10.0E-09 out1 es2 PAT NR 0 0 0 Edge 10.0E-09 out1 es3 PAT NR 0 0 0 Edge 10.0E-09 out1 es4 PAT NR 0 0 0 Edge 10.0E-09 out2 es1 PAT NR 0 0 0 Edge 10.0E-09 out2 es2 PAT NR 0 0 0 Edge 10.0E-09 out2 es3 PAT NR 0 0 0 Edge 10.0E-09 out2 es4 PAT NR 0 0 0 Edge 10.0E-09 in0 es1 PAT NR 0 0 Off in0 es2 PAT NR 0 0 Off in0 es3 PAT NR 0 0 Off in0 es4 PAT NR 0 0 Off in1 es1 PAT NR 0 0 Off in1 es2 PAT NR 0 0 Off in1 es3 PAT NR 0 0 Off in1 es4 PAT NR 0 0 Off in2 es1 PAT NR 0 0 Off in2 es2 PAT NR 0 0 Off in2 es3 PAT NR 0 0 Off in2 es4 PAT NR 0 0 Off clk1 es1 PAT RL 0 70.0E-09 80.0E-09 Off clk1 es2 PAT RL 0 70.0E-09 80.0E-09 Off clk1 es3 PAT RL 0 20.0E-09 30.0E-09 Off clk1 es4 PAT RL 0 50.0E-09 80.0E-09 Off clk2 es1 PAT RL 0 70.0E-09 80.0E-09 Off clk2 es2 PAT RL 0 70.0E-09 80.0E-09 Off clk2 es3 PAT RL 0 20.0E-09 30.0E-09 Off clk2 es4 PAT RL 0 50.0E-09 80.0E-09 Off SDI0 es1 PAT NR 0 0 Off SDI0 es2 PAT NR 0 0 Off SDI0 es3 PAT NR 0 0 Off SDI0 es4 PAT NR 0 0 Off SDI1 es1 PAT NR 0 0 Off SDI1 es2 PAT NR 0 0 Off SDI1 es3 PAT NR 0 0 Off SDI1 es4 PAT NR 0 0 Off SDO0 es1 PAT NR 0 0 0 Edge 10.0E-09 SDO0 es2 PAT NR 0 0 0 Edge 10.0E-09 SDO0 es3 PAT NR 0 0 0 Edge 10.0E-09 SDO0 es4 PAT NR 0 0 0 Edge 10.0E-09 SDO1 es1 PAT NR 0 0 0 Edge 10.0E-09 SDO1 es2 PAT NR 0 0 0 Edge 10.0E-09 SDO1 es3 PAT NR 0 0 0 Edge 10.0E-09 SDO1 es4 PAT NR 0 0 0 Edge 10.0E-09 ACK0 es1 PAT RL 0 20.0E-09 30.0E-09 Off ACK0 es2 PAT RL 0 20.0E-09 30.0E-09 Off ACK0 es3 PAT RL 0 20.0E-09 30.0E-09 Off ACK0 es4 PAT RL 0 20.0E-09 30.0E-09 Off BCK0 es1 PAT RL 0 60.0E-09 70.0E-09 Off BCK0 es2 PAT RL 0 60.0E-09 70.0E-09 Off BCK0 es3 PAT RL 0 60.0E-09 70.0E-09 Off BCK0 es4 PAT RL 0 60.0E-09 70.0E-09 Off -09 out0 es4 PAT NR 0 0 0 Edge 10.0E-09 out1 es1 PAT NR 0 0 0 Edge 10.0E-09 out1 es2 PAT NR 0 0 0 Edge 10.0E-09 out1 es3 PAT NR 0 0 0 Edge 10.0E-09 out1 es4 PAT NR 0 0 0 Edge 10INTERFACES/TERADYNE/J750STIL/000075500001440000012000000000001103104161000156505ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/J750STIL/cyc2.vtran000064400001440000012000000047761103104161000176020ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "cyc1.j750" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc2.stil " # # Command File: "cyc2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.j750"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format J750 -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil ; {#### OUTPUT FORMAT ####} target_file "cyc2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750STIL/cyc1.teratim000064400001440000012000000102471103104161000201020ustar00jcosleystaff00000400000023/* ** Generated by vtran version: 8.0.1 ** Date: Fri Oct 19 13:42:02 2007 ** Timing data for Vector file: Ref2dstLoops.j750 ** Filetype: J750 */ float driver_on = 0ns; float default_window = 1.000ns; float period1 = 90.000ns; float driver_off1 = 90.000ns; float period2 = 90.000ns; float driver_off2 = 90.000ns; float period3 = 110.000ns; float driver_off3 = 110.000ns; float period4 = 100.000ns; float driver_off4 = 100.000ns; /* TSET 1 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 1 d0 = driver_on d1 = mask d2 = mask d3 = driver_off1 r1 = 0.111 * period1 r2 = (0.111 * period1) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 1 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off1 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 1 d0 = driver_on d1 = 0.778 * period1 d2 = 0.889 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 1 d0 = driver_on d1 = 0.222 * period1 d2 = 0.333 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 1 d0 = driver_on d1 = 0.667 * period1 d2 = 0.778 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 2 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 2 d0 = driver_on d1 = mask d2 = mask d3 = driver_off2 r1 = 0.111 * period2 r2 = (0.111 * period2) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 2 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off2 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 2 d0 = driver_on d1 = 0.778 * period2 d2 = 0.889 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 2 d0 = driver_on d1 = 0.222 * period2 d2 = 0.333 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 2 d0 = driver_on d1 = 0.667 * period2 d2 = 0.778 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 3 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 3 d0 = driver_on d1 = mask d2 = mask d3 = driver_off3 r1 = 0.091 * period3 r2 = (0.091 * period3) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 3 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off3 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2, ACK0) hsd edge_set = 3 d0 = driver_on d1 = 0.182 * period3 d2 = 0.273 * period3 d3 = driver_off3 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 3 d0 = driver_on d1 = 0.545 * period3 d2 = 0.636 * period3 d3 = driver_off3 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 4 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 4 d0 = driver_on d1 = mask d2 = mask d3 = driver_off4 r1 = 0.100 * period4 r2 = (0.100 * period4) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 4 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off4 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 4 d0 = driver_on d1 = 0.500 * period4 d2 = 0.800 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 4 d0 = driver_on d1 = 0.200 * period4 d2 = 0.300 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 4 d0 = driver_on d1 = 0.600 * period4 d2 = 0.700 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* end of tset file */ INTERFACES/TERADYNE/J750STIL/scan1.vtran000064400001440000012000000050471103104161000177370ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "scan1.tp" # # Auxilary File: "scan1.tim" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.j750"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.j750_tim"; {#### AUX VECTOR FILE ####} tabular_format J750 -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; resolution = 0.1; { #### .1ns resolution for times #### } { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "scan1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750STIL/cyc1.vtran000064400001440000012000000051401103104161000175630ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "cyc1.j750" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc1.stil " # # Command File: "cyc1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.j750"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format J750 -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil ; {#### OUTPUT FORMAT ####} target_file "cyc1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750STIL/cyc1.j750000064400001440000012000000023231103104161000171160ustar00jcosleystaff00000400000023/* ** Converted by vtran version: 8.0.1 ** Date: Fri Oct 19 13:42:02 2007 ** Source file: ../Data/Ref2.wgl ** Filetype: J750 */ scan_pins = { SDI0:1, SDO0:2, SDI1:1, SDO1:2 } import tset _launch_capture_WFT_, _launch_WFT_, _capture_WFT_, _default_WFT_ ; vector ($tset (out0, out1, out2), (in0, in1, in2), (clk1, clk2), (SDI0, SDI1), (SDO0, SDO1), ACK0, BCK0 ) { > _default_WFT_ XXX XXX 00 XX XX 0 0 ; /* 0 */ scan_setup > _default_WFT_ XXX XXX 00 00 XX 1 1 ; /* 100 */ scan 4 (si SDI0 > 0010) (so SDO0 > XXXX) (si SDI1 > 0001) (so SDO1 > XXXX) ; > _default_WFT_ XXX 010 00 11 XX 0 0 ; /* 500 */ > _launch_capture_WFT_ XXX 100 00 10 XX 0 0 ; /* 600 */ repeat 12 > _default_WFT_ XXX XXX 00 XX XX 0 1 ; /* 690 */ > _default_WFT_ XXX XXX 11 XX XX 0 0 ; /* 1890 */ LabelAA: loopA 5 > _default_WFT_ XXX XXX 01 XX XX 0 1 ; /* 1990 */ > _default_WFT_ XXX XXX 10 XX XX 0 1 ; /* 2090 */ end_loopA LabelAA > _default_WFT_ XXX XXX 01 XX XX 0 1 ; /* 2990 */ scan_setup > _default_WFT_ XXX 100 00 00 XX 1 1 ; /* 3090 */ scan 4 (si SDI0 > 0000) (so SDO0 > XXHL) (si SDI1 > 0000) (so SDO1 > XXXX) ; > _default_WFT_ XXX XXX 01 XX XX 1 1 ; /* 3490 */ > _default_WFT_ XXX XXX 01 XX XX 0 0 ; /* 3590 */ } INTERFACES/TERADYNE/J750VERILOG/000075500001440000012000000000001103104161000162045ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/J750VERILOG/exp1.vtran000064400001440000012000000052561103104161000201450ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: J750 < to > STIL # # Original File: "scan1.tp" # # Auxilary File: "scan1.tim" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.j750"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.j750_tim"; {#### AUX VECTOR FILE ####} tabular_format J750 ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/FLEXVERILOG/000075500001440000012000000000001103104161000163155ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/FLEXVERILOG/exp1.vtran000064400001440000012000000052411103104161000202500ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne FLEX # # translating to Verilog testbench. # # Translation: FLEX < to > Verilog TEST BENCH # # Original File: "scan1.flex" # # Auxilary File: "scan1.flex" # # Target File: "scan1.stil " # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.flex"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.flex"; {#### AUX VECTOR FILE ####} tabular_format FLEX ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the FLEX # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'FLEX'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/J750PLUSVERILOG/000075500001440000012000000000001103104161000167105ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/J750PLUSVERILOG/exp1.vtran000064400001440000012000000053651103104161000206520ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to STIL. # # Translation: CATALYST < to > STIL # # Original File: "scan1.tp" # # Auxilary File: "scan1.tim" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.j750"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.j750PLUS"; {#### AUX VECTOR FILE ####} tabular_format J750+ ; {#### INPUT FORMAT ####} BIDIRECTS data_7, data_6, data_5, data_4, data_3, data_2, data_1, data_0; end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into STIL format # #======================================================================# } proc_block begin; { #### state character translations for 'J750+'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/CATALSTIL/000075500001440000012000000000001103104161000160475ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/CATALSTIL/cyc2.vtran000064400001440000012000000050011103104161000177570ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to verilog testbench. # # Translation: CATALYST < to > VERILOG TEST BENCH # # Original File: "cyc1.catl" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc2.stil " # # Command File: "cyc2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.catl"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format catalyst -cycle ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc2.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/CATALSTIL/cyc1.teratim000064400001440000012000000102251103104161000202750ustar00jcosleystaff00000400000023/* ** Generated by vtran version: 8.0.1 ** Date: Fri Oct 19 13:41:34 2007 ** Timing data for Vector file: Ref2dstLoops.catl */ float driver_on = 0ns; float default_window = 1.000ns; float period1 = 90.000ns; float driver_off1 = 90.000ns; float period2 = 90.000ns; float driver_off2 = 90.000ns; float period3 = 110.000ns; float driver_off3 = 110.000ns; float period4 = 100.000ns; float driver_off4 = 100.000ns; /* TSET 1 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 1 d0 = driver_on d1 = mask d2 = mask d3 = driver_off1 r1 = 0.111 * period1 r2 = (0.111 * period1) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 1 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off1 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 1 d0 = driver_on d1 = 0.778 * period1 d2 = 0.889 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 1 d0 = driver_on d1 = 0.222 * period1 d2 = 0.333 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 1 d0 = driver_on d1 = 0.667 * period1 d2 = 0.778 * period1 d3 = driver_off1 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 2 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 2 d0 = driver_on d1 = mask d2 = mask d3 = driver_off2 r1 = 0.111 * period2 r2 = (0.111 * period2) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 2 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off2 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 2 d0 = driver_on d1 = 0.778 * period2 d2 = 0.889 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 2 d0 = driver_on d1 = 0.222 * period2 d2 = 0.333 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 2 d0 = driver_on d1 = 0.667 * period2 d2 = 0.778 * period2 d3 = driver_off2 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 3 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 3 d0 = driver_on d1 = mask d2 = mask d3 = driver_off3 r1 = 0.091 * period3 r2 = (0.091 * period3) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 3 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off3 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2, ACK0) hsd edge_set = 3 d0 = driver_on d1 = 0.182 * period3 d2 = 0.273 * period3 d3 = driver_off3 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 3 d0 = driver_on d1 = 0.545 * period3 d2 = 0.636 * period3 d3 = driver_off3 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* TSET 4 */ set pin = (out0, out1, out2, SDO0, SDO1) hsd edge_set = 4 d0 = driver_on d1 = mask d2 = mask d3 = driver_off4 r1 = 0.100 * period4 r2 = (0.100 * period4) + default_window format_drv:nrz format_rcv:cmppat; set pin = (in0, in1, in2, SDI0, SDI1) hsd edge_set = 4 d0 = driver_on d1 = 0.000ns d2 = mask d3 = driver_off4 r1 = mask r2 = mask format_drv:nrz format_rcv:cmpmask; set pin = (clk1, clk2) hsd edge_set = 4 d0 = driver_on d1 = 0.500 * period4 d2 = 0.800 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (ACK0) hsd edge_set = 4 d0 = driver_on d1 = 0.200 * period4 d2 = 0.300 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; set pin = (BCK0) hsd edge_set = 4 d0 = driver_on d1 = 0.600 * period4 d2 = 0.700 * period4 d3 = driver_off4 r1 = mask r2 = mask format_drv:rz format_rcv:cmpmask; /* end of tset file */ INTERFACES/TERADYNE/CATALSTIL/scan1.vtran000064400001440000012000000050661103104161000201370ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne Catalyst # # translating to STIL. . # # Translation: CATALYST < to > STIL # # Original File: "scan1.tp" # # Auxilary File: "scan1.tim" # # Target File: "scan1.stil" # # Command File: "scan1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.catl"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.catl_tim"; {#### AUX VECTOR FILE ####} tabular_format catalyst -cycle -scan ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the CATALYST # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; disable_vector_filter; state_trans inputs 'X'->'N'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; resolution = 0.1; { #### .1ns resolution for times #### } { rename_bus_pins $bus_$vec; } simulator stil {#### OUTPUT FORMAT ####} scanin_condition = "0"; target_file "scan1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/CATALSTIL/cyc1.vtran000064400001440000012000000051431103104161000177650ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne J750 # # translating to verilog testbench. # # Translation: CATALYST < to > VERILOG TEST BENCH # # Original File: "cyc1.catl" # # Auxilary File: "cyc1.teratim" # # Target File: "cyc1.stil " # # Command File: "cyc1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "cyc1.catl"; {#### INPUT VECTOR FILE ####} aux_file "cyc1.teratim"; {#### AUX VECTOR FILE ####} tabular_format catalyst -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the J750 # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'J750'->'STIL'#### } { #### NEED THESE FOR CYCLE-BASED OUTPUT? #### } { #### state_trans outputs 'L'->'0', 'H'->'1'; #### } disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; { rename_bus_pins $bus_$vec; } simulator stil; {#### OUTPUT FORMAT ####} target_file "cyc1.stil"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TERADYNE/CATALSTIL/cyc1.catl000064400001440000012000000024661103104161000175630ustar00jcosleystaff00000400000023/* ** Converted by vtran version: 8.0.1 ** Date: Fri Oct 19 13:41:34 2007 ** Source file: ../Data/Ref2.wgl */ filetype = Catalyst; scan_chain IN0(4) = { GRP10 (0 to 3) } ; scan_chain IN1(4) = { GRP20 (0 to 3) } ; scan_pins = { SDI0, SDO0:bit_2, SDI1, SDO1:bit_2 } ; scan_template TMPL = { scan_in_pin SDI0 IN0, scan_out_pin SDO0 IN0, scan_in_pin SDI1 IN1, scan_out_pin SDO1 IN1 } ; vector ((out0, out1, out2), (in0, in1, in2), (clk1, clk2), (SDI0, SDI1), (SDO0, SDO1), ACK0, BCK0 ) { TSET 4 XXX XXX 00 XX XX 0 0 ; /* 0 */ SCAN_SETUP TSET 4 XXX XXX 00 00 XX 1 1 ; /* 100 */ SCAN TMPL (SDI0 > GRP10 = .s0010) (SDO0 < GRP10 = .sXXXX) (SDI1 > GRP20 = .s0001) (SDO1 < GRP20 = .sXXXX) ; TSET 4 XXX 010 00 11 XX 0 0 ; /* 500 */ TSET 1 XXX 100 00 10 XX 0 0 ; /* 600 */ REPEAT 12 TSET 4 XXX XXX 00 XX XX 0 1 ; /* 690 */ TSET 4 XXX XXX 11 XX XX 0 0 ; /* 1890 */ label0: LOOP 5 TSET 4 XXX XXX 01 XX XX 0 1 ; /* 1990 */ END_LOOP label0 TSET 4 XXX XXX 10 XX XX 0 1 ; /* 2090 */ TSET 4 XXX XXX 01 XX XX 0 1 ; /* 2990 */ SCAN_SETUP TSET 4 XXX 100 00 00 XX 1 1 ; /* 3090 */ SCAN TMPL (SDI0 > GRP10 = .s0000) (SDO0 < GRP10 = .sXXHL) (SDI1 > GRP20 = .s0000) (SDO1 < GRP20 = .sXXXX) ; TSET 4 XXX XXX 01 XX XX 1 1 ; /* 3490 */ TSET 4 XXX XXX 01 XX XX 0 0 ; /* 3590 */ }; INTERFACES/TERADYNE/CATALVERILOG/000075500001440000012000000000001103104161000164035ustar00jcosleystaff00000400000023INTERFACES/TERADYNE/CATALVERILOG/exp1.vtran000064400001440000012000000052571103104161000203450ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran file for reading-back Teradyne Catalyst # # translating to verilog testbench. # # Translation: CATALYST < to > VERILOG TEST BENCH # # Original File: "exp1.tp" # # Auxilary File: "exp1.tim" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin; orig_file "../../DATA/scan1.catl"; {#### INPUT VECTOR FILE ####} aux_file "../../DATA/scan1.catl_tim"; {#### AUX VECTOR FILE ####} tabular_format catalyst; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the CATALYST # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin; { #### state character translations for 'CATALYST'->'VERILOG TEST BENCH'#### } state_trans outputs 'L'->'0', 'H'->'1'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, TESTBENCH_MODULE = "scratch_ctl", COMPONENT_MODULE = "design", INSTANCE_NAME = "scratch", timescale = "100ps/100ps" ; target_file "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/TSTL2/000075500001440000012000000000001103104161000141645ustar00jcosleystaff00000400000023INTERFACES/TSTL2/WGLTSTL2/000075500001440000012000000000001103104161000154065ustar00jcosleystaff00000400000023INTERFACES/TSTL2/WGLTSTL2/exp2.vtran000064400001440000012000000046071103104161000173470ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TSTL2 # # Original File: "exp1.wgl" # # Target File: "exp2.tstl2 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl {#### INPUT FORMAT ####} -cycle ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TSTL2'#### } state_trans inputs 'X'->'0'; { map to 0 } state_trans outputs '-'->'X', '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp2.tstl2"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHIP", FUNCTEST = "FC22", ; end end; INTERFACES/TSTL2/WGLTSTL2/exp1.vtran000064400001440000012000000047551103104161000173520ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TSTL2 # # Original File: "exp1.wgl" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl {#### INPUT FORMAT ####} -cycle -expand_loops -expand_reps ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TSTL2'#### } state_trans inputs 'X'->'0'; { map to 0 } state_trans outputs '-'->'X', '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.tstl2"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHIP", FUNCTEST = "FC22", ; end end; INTERFACES/TSTL2/WGLTSTL2/exp1.wgl000064400001440000012000000134711103104161000170040ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.wgl" # # Original File: "exp1.wgl" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# waveform bidir_sc signal PORT3_3_ : input ; PORT3_2_ : input ; PORT3_1_ : input ; PORT3_0_ : input ; PORT1_[3..0] : bidir ; OE1_3_ : input ; OE1_2_ : input ; OE1_1_ : input ; OE1_0_ : input ; OE2_3_ : input ; OE2_2_ : input ; OE2_1_ : input ; OE2_0_ : input ; CLOCK : input ; PORT2_3_ : output ; PORT2_2_ : output ; PORT2_1_ : output ; PORT2_0_ : output ; test_se : input ; test_si : input ; TEI : input ; sin : input ; son : output ; end timeplate bidir_sc_tp period 1000NS PORT1_[3] := input[0PS:P, 100NS:S]; PORT1_[3] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[2] := input[0PS:P, 100NS:S]; PORT1_[2] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[1] := input[0PS:P, 100NS:S]; PORT1_[1] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[0] := input[0PS:P, 100NS:S]; PORT1_[0] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT3_3_ := input[0PS:P, 200NS:S]; PORT3_2_ := input[0PS:P, 200NS:S]; PORT3_1_ := input[0PS:P, 200NS:S]; PORT3_0_ := input[0PS:P, 200NS:S]; OE1_3_ := input[0PS:S]; OE1_2_ := input[0PS:S]; OE1_1_ := input[0PS:S]; OE1_0_ := input[0PS:S]; OE2_3_ := input[0PS:S]; OE2_2_ := input[0PS:S]; OE2_1_ := input[0PS:S]; OE2_0_ := input[0PS:S]; CLOCK := input[0PS:D, 400NS:S, 600NS:D]; PORT2_3_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_2_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_1_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_0_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; test_se := input[0PS:S]; test_si := input[0PS:S]; TEI := input[0PS:S]; sin := input[0PS:S]; son := output[0PS:X, 900NS:Q'edge, 999NS:X]; end timeplate scan_tp period 1000NS PORT1_[3] := input[0PS:P, 100NS:S]; PORT1_[3] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[2] := input[0PS:P, 100NS:S]; PORT1_[2] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[1] := input[0PS:P, 100NS:S]; PORT1_[1] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT1_[0] := input[0PS:P, 100NS:S]; PORT1_[0] := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT3_3_ := input[0PS:S]; PORT3_2_ := input[0PS:S]; PORT3_1_ := input[0PS:S]; PORT3_0_ := input[0PS:S]; OE1_3_ := input[0PS:S]; OE1_2_ := input[0PS:S]; OE1_1_ := input[0PS:S]; OE1_0_ := input[0PS:S]; OE2_3_ := input[0PS:S]; OE2_2_ := input[0PS:S]; OE2_1_ := input[0PS:S]; OE2_0_ := input[0PS:S]; CLOCK := input[0PS:D, 400NS:S, 600NS:D]; PORT2_3_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_2_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_1_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; PORT2_0_ := output[0PS:X, 900NS:Q'edge, 999NS:X]; test_se := input[0PS:S]; test_si := input[0PS:S]; TEI := input[0PS:S]; sin := input[0PS:S]; son := output[0PS:X, 900NS:Q'edge, 999NS:X]; end scancell FF0 ; FF1 ; FF2 ; FF3 ; FFa ; FFb ; FFc ; FFd ; FFe ; FFf ; SC0_G [FF0, FF1, FF2, FF3 ]; SC1_G [FFa, FFb, FFc, FFd, FFe, FFf ]; end scanchain SC0 [ test_si, FF0, FF1, FF2, !, FF3, PORT2_3_ ]; SC1 [ sin, FFa, FFb, FFc, FFd, FFe, FFf, son ]; end scanstate # Synopsys Test Compiler, v2.3-development (Nov 19, 1991) was used to generate this pattern set # INPUT VECTOR FILE = bidir_sc.vdb was the source file for this pattern set state1 := SC0_G(1000) SC1_G(100011); estate1 := SC0_G(0100) SC1_G(010011); state2 := SC0_G(0110) SC1_G(111111); estate2 := SC0_G(0010) SC1_G(000000); state3 := SC0_G(0001); estate3 := SC0_G(0010); state4 := SC0_G(0101) SC1_G(101010); estate4 := SC0_G(1010) SC1_G(010101); end pattern group_ALL (PORT1_:I, PORT1_:O, PORT3_3_, PORT3_2_, PORT3_1_, PORT3_0_, OE1_3_, OE1_2_, OE1_1_, OE1_0_, OE2_3_, OE2_2_, OE2_1_, OE2_0_, CLOCK, PORT2_3_, PORT2_2_, PORT2_1_, PORT2_0_, test_se, test_si, TEI, sin, son) vector(bidir_sc_tp) := [ ---- XXXX 1 0 1 0 0 1 0 0 0 0 0 0 1 X X X X 0 X 0 1 X ]; scan(scan_tp) := [ ---- XXXX 1 0 1 0 0 1 0 0 0 0 0 0 1 - X X X 1 - 1 - - ], input[SC0:state1], output[SC0:estate1], input[SC1:state1], output[SC1:estate1]; vector(bidir_sc_tp) := [ 1010 ---- 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 ]; vector(bidir_sc_tp) := [ ---- XXXX 1 0 1 0 0 1 0 0 0 0 0 0 1 X X X X 0 X 0 1 1 ]; scan(scan_tp) := [ ---- XXXX 0 1 0 0 0 0 0 1 0 0 1 0 1 - X X X 1 - 1 - - ], input[SC0:state2], output[SC0:estate2], input[SC1:state2], output[SC1:estate2]; vector(bidir_sc_tp) := [ ---- 0001 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 ]; vector(bidir_sc_tp) := [ ---- XXXX 0 1 0 0 0 0 0 1 0 0 1 0 1 X X X X 0 X 0 0 1 ]; scan(scan_tp) := [ ---- XXXX 1 0 1 1 1 0 0 0 0 0 0 0 1 - X X X 1 - 1 0 X ], input[SC0:state3], output[SC0:estate3]; vector(bidir_sc_tp) := [ 1101 ---- 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 ]; vector(bidir_sc_tp) := [ ---- XXXX 1 0 1 1 1 0 0 0 0 0 0 0 1 X X X X 0 X 0 1 1 ]; scan(scan_tp) := [ ---- XXXX 1 1 1 1 1 1 1 1 1 1 1 1 1 - X X X 1 - 1 - - ], input[SC0:state4], output[SC0:estate4], input[SC1:state4], output[SC1:estate4]; vector(bidir_sc_tp) := [ 1111 ---- 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 ]; vector(bidir_sc_tp) := [ ---- XXXX 1 0 1 1 1 0 0 0 0 0 0 0 1 X X X X 0 X 0 1 1 ]; end end INTERFACES/TSTL2/WGLTSTL2/exp3.vtran000064400001440000012000000046151103104161000173470ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > TSTL2 # # Original File: "exp1.wgl" # # Target File: "exp3.tstl2 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl {#### INPUT FORMAT ####} -cycle -scan ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TSTL2'#### } state_trans inputs 'X'->'0'; { map to 0 } state_trans outputs '-'->'X', '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp3.tstl2"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHIP", FUNCTEST = "FC22", ; end end; INTERFACES/TSTL2/VCDTSTL2/000075500001440000012000000000001103104161000153715ustar00jcosleystaff00000400000023INTERFACES/TSTL2/VCDTSTL2/exp2.vtran000064400001440000012000000135251103104161000173310ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > TSTL2 # # Original File: "exp1A.vcd" # # Target File: "exp2.tstl2 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into TSTL2 format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'TSTL2'#### } STATE_TRANS inputs 'x'->'0', 'z'->'Z', 'X'->'0' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'X', 'z'->'Z' ; { #### Separate bidir in from out data using control pins #### } BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { #### collapse to cycle-based data, #### } { #### since VCD file does not contain this info separately #### } Include "../../DATA/exp1A.tcyc" SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN merge_bidirects 10HLZX; simulator tstl2 {#### OUTPUT FORMAT ####} TITLE = "MEGACHIP", REPEAT_THRESHOLD = "5", FUNCTEST = "FC22", ; TARGET_FILE "exp2.tstl2"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/TSTL2/VCDTSTL2/exp1.vtran000064400001440000012000000143171103104161000173300ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > TSTL2 # # Original File: "exp1A.vcd" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "../../DATA/exp1A.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS C2_LBUSRDY , C1_RSFTEN , C2_CPUACKN ; OUTPUTS S2_EVTSET2 , S2_EVTSET1 , S2_EVTSET0 , S2_BCMD5 , S2_BCMD4 , S2_BCMD3 , S2_BCMD2 , S2_BCMD1 , S2_BCMD0 , S2_SRDSP , S2_SRMD , S2_ITLB , TC2_TLBREAD , S1_CEXEC6 , S1_CEXEC5 , S1_CEXEC4 , S1_CEXEC3 , S1_CEXEC2 , S1_CEXEC1 , S1_CEXEC0 , S2_CDI15 , S2_CDI14 , S2_CDI13 , S2_CDI12 , S2_CDI11 , S2_CDI10 , S2_CDI9 , S2_CDI8 , S2_CDI7 , S2_CDI6 , S2_CDI5 ; OUTPUTS S2_CDI4 , S2_CDI3 , S2_CDI2 , S2_CDI1 , S2_CDI0 , S2_CDIE , S1_CNOEXEC , S2_CSLSRS ; BIDIRECTS L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 , L2_LDB15 , L2_LDB14 , L2_LDB13 , L2_LDB12 , L2_LDB11 , L2_LDB10 , L2_LDB9 , L2_LDB8 , L2_LDB7 , L2_LDB6 , L2_LDB5 , L2_LDB4 , L2_LDB3 , L2_LDB2 , L2_LDB1 , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL , S2_SRIMASK3 , S2_SRIMASK2 , S2_SRIMASK1 , S2_SRIMASK0 , S1_ASLIRW , S1_ASLIRL , S2_ASPID2 , S2_ASPID1 , S2_ASPID0 , S2_CPUST15 , S2_CPUST14 , S2_CPUST13 , S2_CPUST12 , S2_CPUST11 , S2_CPUST10 , S2_CPUST9 , S2_CPUST8 , S2_CPUST7 , S2_CPUST6 , S2_CPUST5 , S2_CPUST4 , S2_CPUST3 , S2_CPUST2 , S2_CPUST1 , S2_CPUST0 ; BIDIRECTS SA_CPUDMY17 , SA_CPUDMY16 , SA_CPUDMY15 , SA_CPUDMY14 , SA_CPUDMY13 , SA_CPUDMY12 , SA_CPUDMY11 , SA_CPUDMY10 , SA_CPUDMY9 , SA_CPUDMY8 , SA_CPUDMY7 , SA_CPUDMY6 , SA_CPUDMY5 , SA_CPUDMY4 , SA_CPUDMY3 , SA_CPUDMY2 , SA_CPUDMY1 , SA_CPUDMY0 ; OUTPUTS S2_LAB31 , S2_LAB30 , S2_LAB29 , S2_LAB28 , S2_LAB27 , S2_LAB26 , S2_LAB25 , S2_LAB24 , S2_LAB23 , S2_LAB22 , S2_LAB21 , S2_LAB20 , S2_LAB19 , S2_LAB18 , S2_LAB17 , S2_LAB16 , S2_LAB15 , S2_LAB14 , S2_LAB13 , S2_LAB12 , S2_LAB11 , S2_LAB10 , S2_LAB9 , S2_LAB8 , S2_LAB7 , S2_LAB6 , S2_LAB5 , S2_LAB4 , S2_LAB3 , S2_LAB2 , S2_LAB1 , S2_LAB0 , S2_XAB15 , S2_XAB14 , S2_XAB13 , S2_XAB12 , S2_XAB11 , S2_XAB10 , S2_XAB9 , S2_XAB8 , S2_XAB7 , S2_XAB6 , S2_XAB5 , S2_XAB4 , S2_XAB3 , S2_XAB2 , S2_XAB1 , S2_YAB15 , S2_YAB14 , S2_YAB13 , S2_YAB12 , S2_YAB11 , S2_YAB10 , S2_YAB9 , S2_YAB8 , S2_YAB7 , S2_YAB6 , S2_YAB5 , S2_YAB4 , S2_YAB3 , S2_YAB2 , S2_YAB1 ; INPUTS TC1_TLBREAD1 , TC1_TLBREAD0 ; OUTPUTS EMWHHP , EMWBHP , EMWLHP , EMWBLP ; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into TSTL2 format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'TSTL2'#### } STATE_TRANS inputs 'x'->'0', 'z'->'Z', 'X'->'0' ; STATE_TRANS outputs '1'->'H', '0'->'L', 'x'->'X', 'z'->'Z' ; { #### Separate bidir in from out data using control pins #### } BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 , L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 , L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 , L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1; BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1; BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3 L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1; { #### collapse to cycle-based data, strobe all pins at 49 in cycle #### } CYCLE = 50; ALIGN_TO_STEP 50 49; { #### since VCD file does not contain this info separately #### } ADD_PIN HECS_CLK = 1; { #### add clock pin - not necessary if already in data #### } PINTYPE NRZ * @ 5; { #### drive all inputs at 5 #### } PINTYPE STB * @ 45; { #### strobe all outputs at 45 #### } PINTYPE RZ HECS_CLK @ 20, 30; { #### clock pin behavior #### } SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN merge_bidirects 10HLZX; simulator tstl2 {#### OUTPUT FORMAT ####} TITLE = "MEGACHIP", REPEAT_THRESHOLD = "5", FUNCTEST = "FC22", ; TARGET_FILE "exp1.tstl2"; {#### OUTPUT VECTOR FILE ####} END; , L2_LDB0 ; INPUTS T2_TLBMIS , T2_TLBERR , Y1_CMCPU , YA_ASM , YA_TM2 , E2_INTREQ2 , E2_INTREQ1 , E2_INTREQ0 , U2_ASRTBMK , U2_BRKTYP0 , U2_BRKTYP1 , Y1_STPCPU , YA_HSTBY , E2_RSTAJ , E2_CPURST ; OUTPUTS S1_SSLEP , S1_INTACK , S2_IVECRDN , S1_IVECWRN , S2_SRBL INTERFACES/TSTL2/STILTSTL2/000075500001440000012000000000001103104161000155305ustar00jcosleystaff00000400000023INTERFACES/TSTL2/STILTSTL2/exp2.vtran000064400001440000012000000050371103104161000174670ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TSTL2 # # Original File: "exp1.stil" # # Target File: "exp2.tstl2 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TSTL2 format # #======================================================================# } { #### state character translations for 'STIL'->'TSTL2'#### } proc_block begin { #### state character translations for 'STIL'->'TSTL2'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'Z', 'x'->'X', '1'->'H', '0'->'L', 'l'->'L', 'h'->'H', 't'->'Z', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHOP", FUNCTEST = "FC24", ; target_file = "exp2.tstl2"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TSTL2/STILTSTL2/exp1.vtran000064400001440000012000000050711103104161000174640ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TSTL2 # # Original File: "exp1.stil" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TSTL2 format # #======================================================================# } { #### state character translations for 'STIL'->'TSTL2'#### } proc_block begin { #### state character translations for 'STIL'->'TSTL2'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'Z', 'x'->'X', '1'->'H', '0'->'L', 'l'->'L', 'h'->'H', 't'->'Z', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHOP", FUNCTEST = "FC24", ; target_file = "exp1.tstl2"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TSTL2/STILTSTL2/exp3.vtran000064400001440000012000000050451103104161000174670ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > TSTL2 # # Original File: "exp1.stil" # # Target File: "exp3.tstl2 " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into TSTL2 format # #======================================================================# } { #### state character translations for 'STIL'->'TSTL2'#### } proc_block begin { #### state character translations for 'STIL'->'TSTL2'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'0'; state_trans outputs 'T'->'Z', 'x'->'X', '1'->'H', '0'->'L', 'l'->'L', 'h'->'H', 't'->'Z', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHOP", FUNCTEST = "FC24", ; target_file = "exp3.tstl2"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TSTL2/EVCDTSTL2/000075500001440000012000000000001103104161000154765ustar00jcosleystaff00000400000023INTERFACES/TSTL2/EVCDTSTL2/exp1.vtran000064400001440000012000000100201103104161000174200ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > TSTL2 # # Original File: "exp1.evcd" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'TSTL2' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block delete_pins vddo vsso pllvdd pllvss regvdd regvss; merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHOP", FUNCTEST = "FC24", ; target_file = "exp1.tstl2"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TSTL2/EVCDTSTL2/exp2.vtran000064400001440000012000000074251103104161000174400ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > TSTL2 # # Original File: "exp1.evcd" # # Target File: "exp2.tstl2 " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'TSTL2' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block delete_pins vddo vsso pllvdd pllvss regvdd regvss; merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHOP", FUNCTEST = "FC24", ; target_file = "exp2.tstl2"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/TSTL2/README000064400001440000012000000117311103104161000150470ustar00jcosleystaff00000400000023TSTL2 -------- The main directory is "TSTL2" and the sub-directories are -> WGLTSTL2 -> VCDTSTL2 -> STILTSTL2 -> EVCDTSTL2 The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLTSTL2" contains the translation of WGL file to TSTL2 output format. Sub-directory -> "EVCDTSTL2" contains the translation of EVCD file to TSTL2 output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... The TSTL2 output format is invokde in the TVF_BLOCK with the following command - optional parameters are shown in []: simulator TSTL2 [, -AUTO_GROUP] { causes pin grouping by algorithm } [, TITLE = "string"] [, FUNCTEST = "string"] { default FUNC1 } [, MAX_LINE_LENGTH = "nn"] { defines max length of line in tvf } { defaults to 72 characters } [, REPEAT_THRESHOLD = "nn"] { sets # of repeat vectors that } { triggers repeat - don't use with } { WGL or STIL input format } [, TIME_STAMPS = "ON" | "OFF"] { enables/disables timestamps in file } { default is ON } [, SCANIN_DEFAULT="X"] { sets scan-in padding state } ; When using the WGL or STIL reader it should be invoked in the OVF_BLOCK with: tabular_format WGL -cycle, -scan; or tabular_format STIL -cycle, -scan; The -cycle flag prevents the readers from flattening-out timing when the file is being read. The -scan flag tells the readers to maintain the scan data separately, i.e. do not flatten it out. Since the TSTL2 format supports a scan data structure, we do not want the readers to flatten it out. When dealing with scan data, however, since TSTL2 does not provide for a setup vector prior to scan in which to set the states of non-scan pins, the interface does a first pass over the vector data to determine the constant data during scan operations. It then uses the CONST assignment in the SCAN block to set these pins to their appropriate states before doing a second pass to process the vectors. Multiple timesets are supported with this TSTL2 output interface. Note that for STIL translations, the STIL file needs to have the optional "ScanStructures" block defined if there is to be scan data translated. This version also supports bus notation in the TSTL2 vector file. In order to flatten or bit-blast busses, use the RENAME_BUS_PINS command. An example command file for an WGL -> TSTL2 translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > TSTL2 # # Original File: "exp1.wgl" # # Target File: "exp1.tstl2 " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "exp1.wgl"; {#### INPUT VECTOR FILE ####} tabular_format wgl {#### INPUT FORMAT ####} -cycle -scan ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into TSTL2 format # #======================================================================# } proc_block begin disable_vector_filter; { #### state character translations for 'WGL'->'TSTL2'#### } state_trans inputs 'X'->'0'; { map to 0 } state_trans outputs '-'->'X', '0'->'L', '1'->'H'; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp1.tstl2"; {#### OUTPUT VECTOR FILE ####} merge_bidirects 10HLZX; rename_bus_pins $bus$vec; simulator tstl2 {#### OUTPUT FORMAT ####} -AUTO_GROUP TITLE = "MEGACHIP", FUNCTEST = "FC22", ; end end; ################################################################################ INTERFACES/VERILOG_TB/000075500001440000012000000000001103104161000150105ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/WGLVERILOG/000075500001440000012000000000001116472070000165045ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/WGLVERILOG/exp1.vtran000064400001440000012000000050171140376047200204460ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > VERILOG # # Original File: "exp1.wgl" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK { input file spec } begin ORIG_FILE = "exp1.wgl"; {#### INPUT VECTOR FILE ####} TABULAR_FORMAT wgl; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } PROC_BLOCK begin state_trans outputs '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK begin target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} SIMULATOR verilog_tb_readmem {#### OUTPUT FORMAT ####} -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", DATAFILES = "two.dat", {##### used by readmem only #### } INPUT_GROUP = "CLK, SDI0, SDI1, SCAN0, SCAN0_PI" { #### used by readmem only #### } ; end; INTERFACES/VERILOG_TB/WGLVERILOG/exp1.wgl000064400001440000012000002543441103104161000200750ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.wgl" # # Original File: "exp1.wgl" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# #*****************************************************************************# # TESTBENCH 4.1.8 WGL VECTOR FILE # #*****************************************************************************# # # # ENTITY....................TESTARRAY # # VARIATION................. # # ITERATION................. # # # # TESTMODE..................gsd_static_negclk # # # # TDR.......................nstar_tdr # # # # TEST PERIOD...............16 STROBE OFFSET.............15 # # PULSE WIDTH...............2 STROBE TYPE...............window # # TIME UNITS................ns SCAN OVERLAP..............yes # # # # EXPERIMENT................1 # # # # TEST SECTION..............2 TEST SECTION TYPE.........logic # # TESTER TERMINATION........0 TERMINATION DOMINATION....tester # # # #*****************************************************************************# waveform "testarray2.ts2" signal "AADR<0>" : input; "AADR<1>" : input; "AADR<2>" : input; "AADR<3>" : input; "AADR<4>" : input; "AADR<5>" : input; "ABIST" : input; # -TI "ABIST_PI" : input; # -SG "BADR<0>" : input; "BADR<1>" : input; "BADR<2>" : input; "BADR<3>" : input; "BADR<4>" : input; "BADR<5>" : input; "CLK" : input; # -ES "DIN<0>" : input; "DIN<1>" : input; "DIN<2>" : input; "DIN<3>" : input; "DIN<4>" : input; "DIN<5>" : input; "DIN<6>" : input; "DIN<7>" : input; "DIN<8>" : input; "DIN<9>" : input; "DIN<10>" : input; "DIN<11>" : input; "DIN<12>" : input; "DIN<13>" : input; "DIN<14>" : input; "DIN<15>" : input; "DIN<16>" : input; "DIN<17>" : input; "DIN<18>" : input; "DIN<19>" : input; "DIN<20>" : input; "DIN<21>" : input; "DIN<22>" : input; "DIN<23>" : input; "DIN<24>" : input; "DIN<25>" : input; "DIN<26>" : input; "DIN<27>" : input; "DIN<28>" : input; "DIN<29>" : input; "DIN<30>" : input; "DIN<31>" : input; "DIN<32>" : input; "DIN<33>" : input; "DIN<34>" : input; "DIN<35>" : input; "DIN<36>" : input; "DIN<37>" : input; "DIN<38>" : input; "DIN<39>" : input; "DIN<40>" : input; "DIN<41>" : input; "DIN<42>" : input; "DIN<43>" : input; "DIN<44>" : input; "DIN<45>" : input; "DIN<46>" : input; "DIN<47>" : input; "DIN<48>" : input; "DIN<49>" : input; "DIN<50>" : input; "DIN<51>" : input; "DIN<52>" : input; "DIN<53>" : input; "DIN<54>" : input; "DIN<55>" : input; "DIN<56>" : input; "DIN<57>" : input; "DIN<58>" : input; "DIN<59>" : input; "DIN<60>" : input; "DIN<61>" : input; "DIN<62>" : input; "DIN<63>" : input; "DIN<64>" : input; "DIN<65>" : input; "ENABLE" : input; # -TI "ENABLE_PI" : input; # -SG "HOLD" : input; # -TI "HOLD_PI" : input; # -SG "RW0" : input; "RW1" : input; "SCAN0" : input; # -TI "SCAN0_PI" : input; # +SG "SDI0" : input; # SI "SDI1" : input; # SI "SEL" : input; "DOUT<0>" : output; "DOUT<1>" : output; "DOUT<2>" : output; "DOUT<3>" : output; "DOUT<4>" : output; "DOUT<5>" : output; "DOUT<6>" : output; "DOUT<7>" : output; "DOUT<8>" : output; "DOUT<9>" : output; "DOUT<10>" : output; "DOUT<11>" : output; "DOUT<12>" : output; "DOUT<13>" : output; "DOUT<14>" : output; "DOUT<15>" : output; "DOUT<16>" : output; "DOUT<17>" : output; "DOUT<18>" : output; "DOUT<19>" : output; "DOUT<20>" : output; "DOUT<21>" : output; "DOUT<22>" : output; "DOUT<23>" : output; "DOUT<24>" : output; "DOUT<25>" : output; "DOUT<26>" : output; "DOUT<27>" : output; "DOUT<28>" : output; "DOUT<29>" : output; "DOUT<30>" : output; "DOUT<31>" : output; "DOUT<32>" : output; "DOUT<33>" : output; "DOUT<34>" : output; "DOUT<35>" : output; "DOUT<36>" : output; "DOUT<37>" : output; "DOUT<38>" : output; "DOUT<39>" : output; "DOUT<40>" : output; "DOUT<41>" : output; "DOUT<42>" : output; "DOUT<43>" : output; "DOUT<44>" : output; "DOUT<45>" : output; "DOUT<46>" : output; "DOUT<47>" : output; "DOUT<48>" : output; "DOUT<49>" : output; "DOUT<50>" : output; "DOUT<51>" : output; "DOUT<52>" : output; "DOUT<53>" : output; "DOUT<54>" : output; "DOUT<55>" : output; "DOUT<56>" : output; "DOUT<57>" : output; "DOUT<58>" : output; "DOUT<59>" : output; "DOUT<60>" : output; "DOUT<61>" : output; "DOUT<62>" : output; "DOUT<63>" : output; "DOUT<64>" : output; "DOUT<65>" : output; "SDO0" : output; # SO "SDO1" : output; # SO end scancell "d0_out.R0"; "d10_out.R0"; "d11_out.R0"; "d12_out.R0"; "d13_out.R0"; "d14_out.R0"; "d15_out.R0"; "d16_out.R0"; "d17_out.R0"; "d18_out.R0"; "d19_out.R0"; "d1_out.R0"; "d20_out.R0"; "d21_out.R0"; "d22_out.R0"; "d23_out.R0"; "d24_out.R0"; "d25_out.R0"; "d26_out.R0"; "d27_out.R0"; "d28_out.R0"; "d29_out.R0"; "d2_out.R0"; "d30_out.R0"; "d31_out.R0"; "d32_out.R0"; "d33_out.R0"; "d34_out.R0"; "d35_out.R0"; "d36_out.R0"; "d37_out.R0"; "d38_out.R0"; "d39_out.R0"; "d3_out.R0"; "d40_out.R0"; "d41_out.R0"; "d42_out.R0"; "d43_out.R0"; "d44_out.R0"; "d45_out.R0"; "d46_out.R0"; "d47_out.R0"; "d48_out.R0"; "d49_out.R0"; "d4_out.R0"; "d50_out.R0"; "d51_out.R0"; "d52_out.R0"; "d53_out.R0"; "d54_out.R0"; "d55_out.R0"; "d56_out.R0"; "d57_out.R0"; "d58_out.R0"; "d59_out.R0"; "d5_out.R0"; "d60_out.R0"; "d61_out.R0"; "d62_out.R0"; "d63_out.R0"; "d64_out.R0"; "d65_out.R0"; "d6_out.R0"; "d7_out.R0"; "d8_out.R0"; "d9_out.R0"; "onoff_lat.R0"; "oob_lat.R0"; "ra0_lat.R0"; "ra1_lat.R0"; "ra2_lat.R0"; "ra3_lat.R0"; "ra4_lat.R0"; "ra5_lat.R0"; "rdum0_lat.R0"; "rdum1_lat.R0"; "rdum2_lat.R0"; "rdum3_lat.R0"; "rdum4_lat.R0"; "rrw_lat.R0"; "time0_lat.R0"; "time1_lat.R0"; "wa0_lat.R0"; "wa1_lat.R0"; "wa2_lat.R0"; "wa3_lat.R0"; "wa4_lat.R0"; "wa5_lat.R0"; "wd0_lat.R0"; "wd10_lat.R0"; "wd11_lat.R0"; "wd12_lat.R0"; "wd13_lat.R0"; "wd14_lat.R0"; "wd15_lat.R0"; "wd16_lat.R0"; "wd17_lat.R0"; "wd18_lat.R0"; "wd19_lat.R0"; "wd1_lat.R0"; "wd20_lat.R0"; "wd21_lat.R0"; "wd22_lat.R0"; "wd23_lat.R0"; "wd24_lat.R0"; "wd25_lat.R0"; "wd26_lat.R0"; "wd27_lat.R0"; "wd28_lat.R0"; "wd29_lat.R0"; "wd2_lat.R0"; "wd30_lat.R0"; "wd31_lat.R0"; "wd32_lat.R0"; "wd33_lat.R0"; "wd34_lat.R0"; "wd35_lat.R0"; "wd36_lat.R0"; "wd37_lat.R0"; "wd38_lat.R0"; "wd39_lat.R0"; "wd3_lat.R0"; "wd40_lat.R0"; "wd41_lat.R0"; "wd42_lat.R0"; "wd43_lat.R0"; "wd44_lat.R0"; "wd45_lat.R0"; "wd46_lat.R0"; "wd47_lat.R0"; "wd48_lat.R0"; "wd49_lat.R0"; "wd4_lat.R0"; "wd50_lat.R0"; "wd51_lat.R0"; "wd52_lat.R0"; "wd53_lat.R0"; "wd54_lat.R0"; "wd55_lat.R0"; "wd56_lat.R0"; "wd57_lat.R0"; "wd58_lat.R0"; "wd59_lat.R0"; "wd5_lat.R0"; "wd60_lat.R0"; "wd61_lat.R0"; "wd62_lat.R0"; "wd63_lat.R0"; "wd64_lat.R0"; "wd65_lat.R0"; "wd6_lat.R0"; "wd7_lat.R0"; "wd8_lat.R0"; "wd9_lat.R0"; "wdum0_lat.R0"; "wdum1_lat.R0"; "wdum2_lat.R0"; "wdum3_lat.R0"; "wdum4_lat.R0"; "wrw_lat.R0"; end scanchain "MREG_1_gsd_static_negclk" [ "SDI0", "rrw_lat.R0", "wrw_lat.R0", "rdum0_lat.R0", "rdum1_lat.R0", "rdum2_lat.R0", "ra0_lat.R0", "ra1_lat.R0", "ra2_lat.R0", "ra3_lat.R0", "ra4_lat.R0", "rdum3_lat.R0", "rdum4_lat.R0", "ra5_lat.R0", "wdum0_lat.R0", "wdum1_lat.R0", "wdum2_lat.R0", "wa0_lat.R0", "wa1_lat.R0", "wa2_lat.R0", "wa3_lat.R0", "wa4_lat.R0", "wdum3_lat.R0", "wdum4_lat.R0", "wa5_lat.R0", "wd0_lat.R0", "wd1_lat.R0", "wd2_lat.R0", "wd3_lat.R0", "wd4_lat.R0", "wd5_lat.R0", "wd6_lat.R0", "wd7_lat.R0", "wd8_lat.R0", "wd9_lat.R0", "wd10_lat.R0", "wd11_lat.R0", "wd12_lat.R0", "wd13_lat.R0", "wd14_lat.R0", "wd15_lat.R0", "wd16_lat.R0", "wd17_lat.R0", "wd18_lat.R0", "wd19_lat.R0", "wd20_lat.R0", "wd21_lat.R0", "wd22_lat.R0", "wd23_lat.R0", "wd24_lat.R0", "wd25_lat.R0", "wd26_lat.R0", "wd27_lat.R0", "wd28_lat.R0", "wd29_lat.R0", "wd30_lat.R0", "wd31_lat.R0", "wd32_lat.R0", "wd33_lat.R0", "wd34_lat.R0", "wd35_lat.R0", "wd36_lat.R0", "wd37_lat.R0", "wd38_lat.R0", "wd39_lat.R0", "wd40_lat.R0", "wd41_lat.R0", "wd42_lat.R0", "wd43_lat.R0", "wd44_lat.R0", "wd45_lat.R0", "wd46_lat.R0", "wd47_lat.R0", "wd48_lat.R0", "wd49_lat.R0", "wd50_lat.R0", "wd51_lat.R0", "wd52_lat.R0", "wd53_lat.R0", "wd54_lat.R0", "wd55_lat.R0", "wd56_lat.R0", "wd57_lat.R0", "wd58_lat.R0", "wd59_lat.R0", "wd60_lat.R0", "wd61_lat.R0", "wd62_lat.R0", "wd63_lat.R0", "wd64_lat.R0", "wd65_lat.R0", "SDO0" ]; "MREG_2_gsd_static_negclk" [ "SDI1", "onoff_lat.R0", "time0_lat.R0", "time1_lat.R0", "d0_out.R0", "d1_out.R0", "d2_out.R0", "d3_out.R0", "d4_out.R0", "d5_out.R0", "d6_out.R0", "d7_out.R0", "d8_out.R0", "d9_out.R0", "d10_out.R0", "d11_out.R0", "d12_out.R0", "d13_out.R0", "d14_out.R0", "d15_out.R0", "d16_out.R0", "d17_out.R0", "d18_out.R0", "d19_out.R0", "d20_out.R0", "d21_out.R0", "d22_out.R0", "d23_out.R0", "d24_out.R0", "d25_out.R0", "d26_out.R0", "d27_out.R0", "d28_out.R0", "d29_out.R0", "d30_out.R0", "d31_out.R0", "d32_out.R0", "d33_out.R0", "d34_out.R0", "d35_out.R0", "d36_out.R0", "d37_out.R0", "d38_out.R0", "d39_out.R0", "d40_out.R0", "d41_out.R0", "d42_out.R0", "d43_out.R0", "d44_out.R0", "d45_out.R0", "d46_out.R0", "d47_out.R0", "d48_out.R0", "d49_out.R0", "d50_out.R0", "d51_out.R0", "d52_out.R0", "d53_out.R0", "d54_out.R0", "d55_out.R0", "d56_out.R0", "d57_out.R0", "d58_out.R0", "d59_out.R0", "d60_out.R0", "d61_out.R0", "d62_out.R0", "d63_out.R0", "d64_out.R0", "d65_out.R0", "oob_lat.R0", "SDO1" ]; end timeplate "PULSECLK_gsd_static_negclk" period 16 ns "AADR<0>" := input[ 0ns:S ]; "AADR<1>" := input[ 0ns:S ]; "AADR<2>" := input[ 0ns:S ]; "AADR<3>" := input[ 0ns:S ]; "AADR<4>" := input[ 0ns:S ]; "AADR<5>" := input[ 0ns:S ]; "ABIST" := input[ 0ns:S ]; "ABIST_PI" := input[ 0ns:S ]; "BADR<0>" := input[ 0ns:S ]; "BADR<1>" := input[ 0ns:S ]; "BADR<2>" := input[ 0ns:S ]; "BADR<3>" := input[ 0ns:S ]; "BADR<4>" := input[ 0ns:S ]; "BADR<5>" := input[ 0ns:S ]; "CLK" := input[ 0ns:D, 2ns:S, 4ns:D ]; "DIN<0>" := input[ 0ns:S ]; "DIN<1>" := input[ 0ns:S ]; "DIN<2>" := input[ 0ns:S ]; "DIN<3>" := input[ 0ns:S ]; "DIN<4>" := input[ 0ns:S ]; "DIN<5>" := input[ 0ns:S ]; "DIN<6>" := input[ 0ns:S ]; "DIN<7>" := input[ 0ns:S ]; "DIN<8>" := input[ 0ns:S ]; "DIN<9>" := input[ 0ns:S ]; "DIN<10>" := input[ 0ns:S ]; "DIN<11>" := input[ 0ns:S ]; "DIN<12>" := input[ 0ns:S ]; "DIN<13>" := input[ 0ns:S ]; "DIN<14>" := input[ 0ns:S ]; "DIN<15>" := input[ 0ns:S ]; "DIN<16>" := input[ 0ns:S ]; "DIN<17>" := input[ 0ns:S ]; "DIN<18>" := input[ 0ns:S ]; "DIN<19>" := input[ 0ns:S ]; "DIN<20>" := input[ 0ns:S ]; "DIN<21>" := input[ 0ns:S ]; "DIN<22>" := input[ 0ns:S ]; "DIN<23>" := input[ 0ns:S ]; "DIN<24>" := input[ 0ns:S ]; "DIN<25>" := input[ 0ns:S ]; "DIN<26>" := input[ 0ns:S ]; "DIN<27>" := input[ 0ns:S ]; "DIN<28>" := input[ 0ns:S ]; "DIN<29>" := input[ 0ns:S ]; "DIN<30>" := input[ 0ns:S ]; "DIN<31>" := input[ 0ns:S ]; "DIN<32>" := input[ 0ns:S ]; "DIN<33>" := input[ 0ns:S ]; "DIN<34>" := input[ 0ns:S ]; "DIN<35>" := input[ 0ns:S ]; "DIN<36>" := input[ 0ns:S ]; "DIN<37>" := input[ 0ns:S ]; "DIN<38>" := input[ 0ns:S ]; "DIN<39>" := input[ 0ns:S ]; "DIN<40>" := input[ 0ns:S ]; "DIN<41>" := input[ 0ns:S ]; "DIN<42>" := input[ 0ns:S ]; "DIN<43>" := input[ 0ns:S ]; "DIN<44>" := input[ 0ns:S ]; "DIN<45>" := input[ 0ns:S ]; "DIN<46>" := input[ 0ns:S ]; "DIN<47>" := input[ 0ns:S ]; "DIN<48>" := input[ 0ns:S ]; "DIN<49>" := input[ 0ns:S ]; "DIN<50>" := input[ 0ns:S ]; "DIN<51>" := input[ 0ns:S ]; "DIN<52>" := input[ 0ns:S ]; "DIN<53>" := input[ 0ns:S ]; "DIN<54>" := input[ 0ns:S ]; "DIN<55>" := input[ 0ns:S ]; "DIN<56>" := input[ 0ns:S ]; "DIN<57>" := input[ 0ns:S ]; "DIN<58>" := input[ 0ns:S ]; "DIN<59>" := input[ 0ns:S ]; "DIN<60>" := input[ 0ns:S ]; "DIN<61>" := input[ 0ns:S ]; "DIN<62>" := input[ 0ns:S ]; "DIN<63>" := input[ 0ns:S ]; "DIN<64>" := input[ 0ns:S ]; "DIN<65>" := input[ 0ns:S ]; "ENABLE" := input[ 0ns:S ]; "ENABLE_PI" := input[ 0ns:S ]; "HOLD" := input[ 0ns:S ]; "HOLD_PI" := input[ 0ns:S ]; "RW0" := input[ 0ns:S ]; "RW1" := input[ 0ns:S ]; "SCAN0" := input[ 0ns:S ]; "SCAN0_PI" := input[ 0ns:S ]; "SDI0" := input[ 0ns:S ]; "SDI1" := input[ 0ns:S ]; "SEL" := input[ 0ns:S ]; "DOUT<0>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<1>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<2>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<3>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<4>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<5>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<6>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<7>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<8>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<9>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<10>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<11>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<12>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<13>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<14>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<15>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<16>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<17>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<18>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<19>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<20>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<21>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<22>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<23>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<24>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<25>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<26>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<27>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<28>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<29>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<30>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<31>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<32>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<33>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<34>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<35>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<36>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<37>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<38>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<39>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<40>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<41>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<42>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<43>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<44>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<45>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<46>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<47>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<48>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<49>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<50>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<51>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<52>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<53>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<54>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<55>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<56>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<57>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<58>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<59>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<60>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<61>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<62>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<63>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<64>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<65>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO0" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO1" := output[ 0ns:X, 15ns:Q, 16ns:X ]; end timeplate "STIMCLOCK" period 16 ns "AADR<0>" := input[ 0ns:S ]; "AADR<1>" := input[ 0ns:S ]; "AADR<2>" := input[ 0ns:S ]; "AADR<3>" := input[ 0ns:S ]; "AADR<4>" := input[ 0ns:S ]; "AADR<5>" := input[ 0ns:S ]; "ABIST" := input[ 0ns:S ]; "ABIST_PI" := input[ 0ns:S ]; "BADR<0>" := input[ 0ns:S ]; "BADR<1>" := input[ 0ns:S ]; "BADR<2>" := input[ 0ns:S ]; "BADR<3>" := input[ 0ns:S ]; "BADR<4>" := input[ 0ns:S ]; "BADR<5>" := input[ 0ns:S ]; "CLK" := input[ 0ns:S ]; "DIN<0>" := input[ 0ns:S ]; "DIN<1>" := input[ 0ns:S ]; "DIN<2>" := input[ 0ns:S ]; "DIN<3>" := input[ 0ns:S ]; "DIN<4>" := input[ 0ns:S ]; "DIN<5>" := input[ 0ns:S ]; "DIN<6>" := input[ 0ns:S ]; "DIN<7>" := input[ 0ns:S ]; "DIN<8>" := input[ 0ns:S ]; "DIN<9>" := input[ 0ns:S ]; "DIN<10>" := input[ 0ns:S ]; "DIN<11>" := input[ 0ns:S ]; "DIN<12>" := input[ 0ns:S ]; "DIN<13>" := input[ 0ns:S ]; "DIN<14>" := input[ 0ns:S ]; "DIN<15>" := input[ 0ns:S ]; "DIN<16>" := input[ 0ns:S ]; "DIN<17>" := input[ 0ns:S ]; "DIN<18>" := input[ 0ns:S ]; "DIN<19>" := input[ 0ns:S ]; "DIN<20>" := input[ 0ns:S ]; "DIN<21>" := input[ 0ns:S ]; "DIN<22>" := input[ 0ns:S ]; "DIN<23>" := input[ 0ns:S ]; "DIN<24>" := input[ 0ns:S ]; "DIN<25>" := input[ 0ns:S ]; "DIN<26>" := input[ 0ns:S ]; "DIN<27>" := input[ 0ns:S ]; "DIN<28>" := input[ 0ns:S ]; "DIN<29>" := input[ 0ns:S ]; "DIN<30>" := input[ 0ns:S ]; "DIN<31>" := input[ 0ns:S ]; "DIN<32>" := input[ 0ns:S ]; "DIN<33>" := input[ 0ns:S ]; "DIN<34>" := input[ 0ns:S ]; "DIN<35>" := input[ 0ns:S ]; "DIN<36>" := input[ 0ns:S ]; "DIN<37>" := input[ 0ns:S ]; "DIN<38>" := input[ 0ns:S ]; "DIN<39>" := input[ 0ns:S ]; "DIN<40>" := input[ 0ns:S ]; "DIN<41>" := input[ 0ns:S ]; "DIN<42>" := input[ 0ns:S ]; "DIN<43>" := input[ 0ns:S ]; "DIN<44>" := input[ 0ns:S ]; "DIN<45>" := input[ 0ns:S ]; "DIN<46>" := input[ 0ns:S ]; "DIN<47>" := input[ 0ns:S ]; "DIN<48>" := input[ 0ns:S ]; "DIN<49>" := input[ 0ns:S ]; "DIN<50>" := input[ 0ns:S ]; "DIN<51>" := input[ 0ns:S ]; "DIN<52>" := input[ 0ns:S ]; "DIN<53>" := input[ 0ns:S ]; "DIN<54>" := input[ 0ns:S ]; "DIN<55>" := input[ 0ns:S ]; "DIN<56>" := input[ 0ns:S ]; "DIN<57>" := input[ 0ns:S ]; "DIN<58>" := input[ 0ns:S ]; "DIN<59>" := input[ 0ns:S ]; "DIN<60>" := input[ 0ns:S ]; "DIN<61>" := input[ 0ns:S ]; "DIN<62>" := input[ 0ns:S ]; "DIN<63>" := input[ 0ns:S ]; "DIN<64>" := input[ 0ns:S ]; "DIN<65>" := input[ 0ns:S ]; "ENABLE" := input[ 0ns:S ]; "ENABLE_PI" := input[ 0ns:S ]; "HOLD" := input[ 0ns:S ]; "HOLD_PI" := input[ 0ns:S ]; "RW0" := input[ 0ns:S ]; "RW1" := input[ 0ns:S ]; "SCAN0" := input[ 0ns:S ]; "SCAN0_PI" := input[ 0ns:S ]; "SDI0" := input[ 0ns:S ]; "SDI1" := input[ 0ns:S ]; "SEL" := input[ 0ns:S ]; "DOUT<0>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<1>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<2>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<3>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<4>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<5>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<6>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<7>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<8>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<9>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<10>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<11>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<12>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<13>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<14>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<15>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<16>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<17>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<18>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<19>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<20>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<21>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<22>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<23>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<24>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<25>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<26>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<27>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<28>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<29>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<30>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<31>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<32>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<33>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<34>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<35>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<36>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<37>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<38>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<39>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<40>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<41>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<42>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<43>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<44>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<45>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<46>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<47>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<48>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<49>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<50>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<51>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<52>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<53>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<54>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<55>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<56>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<57>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<58>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<59>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<60>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<61>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<62>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<63>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<64>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<65>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO0" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO1" := output[ 0ns:X, 15ns:Q, 16ns:X ]; end #*****************************************************************************# # DEFINE SCAN STATES # #*****************************************************************************# scanstate "SS.1.2.1.2.1.1.1" := "MREG_1_gsd_static_negclk" (101010101110100011010000000000001100111000101100110111111001001110001110001100110110011000) "MREG_2_gsd_static_negclk" (1001000100101000001101011100000000000000000110010111010100110100111000); "SS.1.2.1.2.1.4.1" := "MREG_1_gsd_static_negclk" (X11101010111011010101110100000000110011100010110011011111100100111000111000110011011001100) "MREG_2_gsd_static_negclk" (X100100010010100000110101110000000000000000011001011101010011010011100); "SS.1.2.1.2.2.1.1" := "MREG_1_gsd_static_negclk" (100011100011110100000010110110101100001011100100101011011000111101110111011001111011011001) "MREG_2_gsd_static_negclk" (0000101010110001000110111010111011110010010011010011111011100011101010); "SS.1.2.1.2.2.4.1" := "MREG_1_gsd_static_negclk" (X10001110001111010000001011011010110000101110010010101101100011110111011101100111101101100) "MREG_2_gsd_static_negclk" (X000010101011000100011011101011101111001001001101001111101110001110101); "SS.1.2.1.2.3.1.1" := "MREG_1_gsd_static_negclk" (010110010111010000011011010001101010010101110001000010001001110101011100000111010111100100) "MREG_2_gsd_static_negclk" (1011010011101001111001110100101100111101010111100110110010110101010010); "SS.1.2.1.2.3.4.1" := "MREG_1_gsd_static_negclk" (X10011100011100110010111010100010110110111001111111100010111100011111101110110011100001100) "MREG_2_gsd_static_negclk" (X101101001110100111100111010010110011110101011110011011001011010101001); "SS.1.2.1.2.4.1.1" := "MREG_1_gsd_static_negclk" (010000101111011011111000111110010110011110010100010001000101100001101010110010100110100010) "MREG_2_gsd_static_negclk" (1101011101111111001011001111010111000010111100101100011101011110001010); "SS.1.2.1.2.4.4.1" := "MREG_1_gsd_static_negclk" (X10100001011110110111110001111100101100111100101000100010001011000011010101100101001101000) "MREG_2_gsd_static_negclk" (X110110111011111110010110011110101110000101111001011000111010111100010); "SS.1.2.1.2.5.1.1" := "MREG_1_gsd_static_negclk" (011110001001110110011011001010011001001100110101001100001100111011001010100010000100100100) "MREG_2_gsd_static_negclk" (1011001010100010110101010001100011110100101010101100100101010001110101); "SS.1.2.1.2.5.4.1" := "MREG_1_gsd_static_negclk" (X01111000100111011001101100101001100100110011010100110000110011101100101010001000010010010) "MREG_2_gsd_static_negclk" (X101100101010001011010101000110001111010010101010110010010101000111010); "SS.1.2.1.2.6.1.1" := "MREG_1_gsd_static_negclk" (101100011111100001000001101001110101111100110110101001011010011001001011000010100110100111) "MREG_2_gsd_static_negclk" (0001010010010000000011100101010000001110010000001110001010100010001110); "SS.1.2.1.2.6.4.1" := "MREG_1_gsd_static_negclk" (X11110001111111100011111110100111010111110011011010100101101001100100101100001010011010011) "MREG_2_gsd_static_negclk" (X000101001001000000001110010101000000111001000000111000101010001000111); "SS.1.2.1.2.7.1.1" := "MREG_1_gsd_static_negclk" (011111010100111100011100111110000101001000011001010111000101100110110001111101101111000011) "MREG_2_gsd_static_negclk" (0010000010000000001110010101000100111001000000111000110100010001100100); "SS.1.2.1.2.7.4.1" := "MREG_1_gsd_static_negclk" (X00111101010011111010100111111000010100100001100101011100010110011011000111110110111100001) "MREG_2_gsd_static_negclk" (X001000001000000000111001010100010011100100000011100011010001000110010); "SS.1.2.1.2.8.1.1" := "MREG_1_gsd_static_negclk" (110110011110100111111110100100101110111111000100111111101100111101101111110000100011011111) "MREG_2_gsd_static_negclk" (0101100101000111101011010111100001100111010111101011011111011011011111); "SS.1.2.1.2.8.4.1" := "MREG_1_gsd_static_negclk" (X11011001111010011111111010010010111011111100010011111110110011110110111111000010001101111) "MREG_2_gsd_static_negclk" (X010110010100011110101101011110000110011101011110101101111101101101111); "SS.1.2.1.2.9.1.1" := "MREG_1_gsd_static_negclk" (001001111000011110110010011000110101001001001100000111010000110000001110110000100000010100) "MREG_2_gsd_static_negclk" (0110111000110110001111000000111010001000101000111101000011101100100010); "SS.1.2.1.2.9.4.1" := "MREG_1_gsd_static_negclk" (X10100001010011001111000000010100101011010111110001110010101100101111000000110011000011100) "MREG_2_gsd_static_negclk" (X011011100011011000111100000011101000100010100011110100001110110010001); "SS.1.2.1.2.10.1.1" := "MREG_1_gsd_static_negclk" (000110110110110110111001011100010010100011110100011100010100111011010100000100110000010010) "MREG_2_gsd_static_negclk" (0101000111101001010001110111101000101000010101000100101010111100000110); "SS.1.2.1.2.10.4.1" := "MREG_1_gsd_static_negclk" (X00011000011000110110110110111011100100101010001110001110010001110000111111101101101000010) "MREG_2_gsd_static_negclk" (X010100011110100101000111011110100010100001010100010010101011110000011); "SS.1.2.1.2.11.1.1" := "MREG_1_gsd_static_negclk" (000110101100001110110001000001001010011101100101100110101011010101110110000101001000001111) "MREG_2_gsd_static_negclk" (0101011111011011000101101100101010101001110100010110010010101100100110); "SS.1.2.1.2.11.4.1" := "MREG_1_gsd_static_negclk" (X10011111100010110101100010001011011100100001000011110011111000011000110001000100110111111) "MREG_2_gsd_static_negclk" (X010101111101101100010110110010101010100111010001011001001010110010011); "SS.1.2.1.2.12.1.1" := "MREG_1_gsd_static_negclk" (101100010010011001010000111101001101101110111101000100110100111010100001111000000000110000) "MREG_2_gsd_static_negclk" (0001110011110101111011100000110101111100111111101111000011010101000111); "SS.1.2.1.2.12.4.1" := "MREG_1_gsd_static_negclk" (X01110110101001100010010001000100000011100000011100011100101111100010000011100011011110101) "MREG_2_gsd_static_negclk" (X000111001111010111101110000011010111110011111110111100001101010100011); "SS.1.2.1.3.1.1.1" := "MREG_1_gsd_static_negclk" (011011111001000010001001010001000101111100110010001110110100100011110110011001011010000000) "MREG_2_gsd_static_negclk" (1110011110011111100010001100011010101110101110001000010001101100011101); "SS.1.2.1.3.1.3.1" := "MREG_1_gsd_static_negclk" (X01101111100100001000100101000100010111110011001000111011010010001111011001100101101000000) "MREG_2_gsd_static_negclk" (X111001111001111110001000110001101010111010111000100001000110110001110); "SS.1.2.1.4.1.1.1" := "MREG_1_gsd_static_negclk" (000111110011101011100110000000000000101101100000111111011110000010110110000011011010111111) "MREG_2_gsd_static_negclk" (1010111100111011110010100100101011001100000111001001000110110010010110); "SS.1.2.1.4.1.4.1" := "MREG_1_gsd_static_negclk" (101101000110100001110010000000010000000001011001011100100000000100000101010101110001000000) "MREG_2_gsd_static_negclk" (0100100010101100100011101011001110100110101010001111010110011100100110); "SS.1.2.1.4.1.7.1" := "MREG_1_gsd_static_negclk" (X11110100011011101000110100000001000000000101100101110010000000010000010101010111000100000) "MREG_2_gsd_static_negclk" (X010010001010110010001110101100111010011010101000111101011001110010011); "SS.1.2.1.5.1.1.1" := "MREG_1_gsd_static_negclk" (111000010110000100010000001110100000000001000000011000100100100100110101011000111001010100) "MREG_2_gsd_static_negclk" (0110000000100100000010110010111001000000001000001010101011100010000000); "SS.1.2.1.5.1.4.1" := "MREG_1_gsd_static_negclk" (X11100001011001000010110000111010000000000100000001100010010010010011010101100011100101010) "MREG_2_gsd_static_negclk" (X011000000010010000001011001011100100000000100000101010101110001000000); "SS.1.2.1.5.2.1.1" := "MREG_1_gsd_static_negclk" (010111101010001000010000100101111011001000101011001110110001001100100010011100111001000100) "MREG_2_gsd_static_negclk" (0110011010000110111101000000101011101110001011010010100010110101110101); "SS.1.2.1.5.2.4.1" := "MREG_1_gsd_static_negclk" (X01011110101000100001000010010111101100100010101100111011000100110010001001110011100100010) "MREG_2_gsd_static_negclk" (X011001101000011011110100000010101110111000101101001010001011010111010); "SS.1.2.1.5.3.1.1" := "MREG_1_gsd_static_negclk" (000010000001000010111011100100000011110011101010000110000000101000101010111000000000110110) "MREG_2_gsd_static_negclk" (1100001100101111111010111111001111111000110110100111110010111010110010); "SS.1.2.1.5.3.4.1" := "MREG_1_gsd_static_negclk" (X00001000000100010000001010010000001111001110101000011000000010100010101011100000000011011) "MREG_2_gsd_static_negclk" (X110000110010111111101011111100111111100011011010011111001011101011001); "SS.1.2.1.5.4.1.1" := "MREG_1_gsd_static_negclk" (000000110111010000000001001111001010000110000100001100000001000000001100011001011011001100) "MREG_2_gsd_static_negclk" (0110000010100100001101000110110000100011001000110100011011000000001100); "SS.1.2.1.5.4.4.1" := "MREG_1_gsd_static_negclk" (X00000011011100000110111000111100101000011000010000110000000100000000110001100101101100110) "MREG_2_gsd_static_negclk" (X011000001010010000110100011011000010001100100011010001101100000000110); "SS.1.2.1.5.5.1.1" := "MREG_1_gsd_static_negclk" (000111111101101011000000100111011111010101101100011110110111000110101011001001111001011100) "MREG_2_gsd_static_negclk" (1001001111011111011010001001100111010010001111110010011010011001101010); "SS.1.2.1.5.5.4.1" := "MREG_1_gsd_static_negclk" (X00011111110110111111101110011101111101010110110001111011011100011010101100100111100101110) "MREG_2_gsd_static_negclk" (X100100111101111101101000100110011101001000111111001001101001100110101); "SS.1.2.1.5.6.1.1" := "MREG_1_gsd_static_negclk" (110110011101110111111001000111000000000010111101011110000100001100010001100111011111001110) "MREG_2_gsd_static_negclk" (0000000000101111000011100011110100110100101010001111111110100001001001); "SS.1.2.1.5.6.4.1" := "MREG_1_gsd_static_negclk" (X11011000000100110011101100110111001111011000001010011000001111001001111011000000101001010) "MREG_2_gsd_static_negclk" (X000000000010111100001110001111010011010010101000111111111010000100100); "SS.1.2.1.5.7.1.1" := "MREG_1_gsd_static_negclk" (110110011010010100110101000100111100110010000011000110101001011111011011011111111011100101) "MREG_2_gsd_static_negclk" (0111010000100111001111010110110110100100001100000100110110011010011000); "SS.1.2.1.5.7.4.1" := "MREG_1_gsd_static_negclk" (X01101100110100101001101010001001111001100100000110001101010010111110110110111111110111001) "MREG_2_gsd_static_negclk" (X011010100001001110011110101101101101001000011000001001101100110100110); "SS.1.2.1.5.8.1.1" := "MREG_1_gsd_static_negclk" (011100101011000010000100100111100011011101001010010001011000000101010000010101001000000001) "MREG_2_gsd_static_negclk" (1100100111010100110111001110100110101101000010101100000000010110110110); "SS.1.2.1.5.8.4.1" := "MREG_1_gsd_static_negclk" (X00110010101101100101011010011110001101110100101001000101100000010101000001010100100000000) "MREG_2_gsd_static_negclk" (X110010011101010011011100111010011010110100001010110000000001011011011); "SS.1.2.1.5.9.1.1" := "MREG_1_gsd_static_negclk" (100000100011011110001001100101000101000000001011100000001111001110100001111100001000010000) "MREG_2_gsd_static_negclk" (0100101110000110111010000111100011111101000000111000111110010001101001); "SS.1.2.1.5.9.4.1" := "MREG_1_gsd_static_negclk" (X11000010001110000100011001010111000001110110000000011001000111000100110111000000011101000) "MREG_2_gsd_static_negclk" (X010010111000011011101000011110001111110100000011100011111001000110100); "SS.1.2.1.5.10.1.1" := "MREG_1_gsd_static_negclk" (111111111011100000011000110110110111001011100010111001111011011011110111101011001001010110) "MREG_2_gsd_static_negclk" (1110110101100101010010110000011100000001001001111111111001010011000011); "SS.1.2.1.5.10.4.1" := "MREG_1_gsd_static_negclk" (X11111111101111111111011111011011011100101110001011100111101101101111011110101100100101011) "MREG_2_gsd_static_negclk" (X111011010110010101001011000001110000000100100111111111100101001100001); "SS.1.2.1.5.11.1.1" := "MREG_1_gsd_static_negclk" (011000110010001010101000111001000001010110101010100101100111000110100000100110011101100001) "MREG_2_gsd_static_negclk" (1100011000011111111011011101100011011011111011000101000011110111101111); "SS.1.2.1.5.11.4.1" := "MREG_1_gsd_static_negclk" (X01100011001000101010100011100100000101011010101010010110011100011010000010011001110110000) "MREG_2_gsd_static_negclk" (X110001100001111111101101110110001101101111101100010100001111011110111); "SS.1.2.1.5.12.1.1" := "MREG_1_gsd_static_negclk" (110001101110011000000010000011111011101110111010110011000110001000001110111010111010111101) "MREG_2_gsd_static_negclk" (0001111010011010100101010011101100110101110010010101101110110101010110); "SS.1.2.1.5.12.4.1" := "MREG_1_gsd_static_negclk" (X11000111101000001101110001000101011010101000010110110100100011111101111010101000000111001) "MREG_2_gsd_static_negclk" (X000111101001101010010101001110110011010111001001010110111011010101011); end #*****************************************************************************# # TEST VECTORS # #*****************************************************************************# pattern MAIN ( ALLINPUT, ALLOUTPUT ) vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; #*****************************************************************************# # TESTER LOOP...............1 PROCEDURES HAVE MEMORY....no # # TEST PROCEDURE............1 TYPE......................init # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # TEST SEQUENCE.............1 TYPE......................init # #*****************************************************************************# # processed EVENT: 1.2.1.1.1.1.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.2.1 vector ( +, "STIMCLOCK" ) := [ XXXXXX0XXXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.4.1 vector ( +, "STIMCLOCK" ) := [ XXXXXX0XXXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.5.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; #*****************************************************************************# # TEST PROCEDURE............2 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............2507 PERCENT STATIC FAULTS.....87.084335 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.1.1.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX00XXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000XX01XXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX00XXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000XX01--X XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX], input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.1.1.1" ]; # processed EVENT: 1.2.1.2.1.2.1 # processed EVENT: 1.2.1.2.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100101011111010110010011010010010000000000110110100000111110001000100000000000100001000111 10001001010000011010111000000000000000001100101110101001101001110000]; # processed EVENT: 1.2.1.2.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100101011111110110010011010010010000000000110110100000111110001000100000000000100001000111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111010110010011010010010000000000110110100000111110001000100000000000100001001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111010110010011010010010000000000110110100000111110001000100000000000100001001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111110110010011010010010000000000110110100000111110001000100000000000100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.1.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.1.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............2 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.2.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.2.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.2.1.1" ]; # processed EVENT: 1.2.1.2.2.2.1 # processed EVENT: 1.2.1.2.2.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110101011111011100110110111010101111010111111010101111000001000100111010001101000011100010 01010101100010001101110101110111100100100110100111110111000111010110]; # processed EVENT: 1.2.1.2.2.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110101011111111100110110111010101111010111111010101111000001000100111010001101000011100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.2.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111011100110110111010101111010111111010101111000001000100111010001101000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111011100110110111010101111010111111010101111000001000100111010001101000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111111100110110111010101111010111111010101111000001000100111010001101000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.2.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.2.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............3 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.3.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.3.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.3.1.1" ]; # processed EVENT: 1.2.1.2.3.2.1 # processed EVENT: 1.2.1.2.3.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001000011 10100111010011110011101001011001111010101111001101100101101010100100]; # processed EVENT: 1.2.1.2.3.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111110100010110110111001111111100010111100011111101110110011100001100100001000011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.3.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111110100010110110111001111111100010111100011111101110110011100001100100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.3.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.3.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............4 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.4.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.4.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.4.1.1" ]; # processed EVENT: 1.2.1.2.4.2.1 # processed EVENT: 1.2.1.2.4.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100001110101011010001001011100011010001101011101000100101110001101000110101110000000001100 10111011111110010110011110101110000101111001011000111010111100010100]; # processed EVENT: 1.2.1.2.4.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100001110101111010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.4.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101011010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101011010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101111010001001011100011010001101011101000100101110001101000110101110000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.4.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.4.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............5 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.5.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.5.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.5.1.1" ]; # processed EVENT: 1.2.1.2.5.2.1 # processed EVENT: 1.2.1.2.5.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001001101000010001110010000000111000101010001000111001000000011100010101000100000011100100 10010101000101101010100011000111101001010101011001001010100011101001]; # processed EVENT: 1.2.1.2.5.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001001101000110001110010000000111000101010001000111001000000011100010101000100000011100100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.5.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000010001110010000000111000101010001000111001000000011100010101000100000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000010001110010000000111000101010001000111001000000011100010101000100000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000110001110010000000111000101010001000111001000000011100010101000100000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.5.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.5.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............6 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.6.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.6.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.6.1.1" ]; # processed EVENT: 1.2.1.2.6.2.1 # processed EVENT: 1.2.1.2.6.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010001011100010000000000000000001011000000000001001000100000000000010000001001000001000010 10100100100000000111001010100000011100100000011100010101000100011110]; # processed EVENT: 1.2.1.2.6.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010001011100110000000000000000001011000000000001001000100000000000010000001001000001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.6.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100010000000000000000001011000000000001001000100000000000010000001001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100010000000000000000001011000000000001001000100000000000010000001001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100110000000000000000001011000000000001001000100000000000010000001001000001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.6.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.6.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............7 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.7.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.7.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.7.1.1" ]; # processed EVENT: 1.2.1.2.7.2.1 # processed EVENT: 1.2.1.2.7.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100001100100011100000110000010000110001000000000100001010100100110000010001111100001000110 00000100000000011100101010001001110010000001110001101000100011001010]; # processed EVENT: 1.2.1.2.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100001100100111100000110000010000110001000000000100001010100100110000010001111100001000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.7.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100011100000110000010000110001000000000100001010100100110000010001111100001001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100011100000110000010000110001000000000100001010100100110000010001111100001001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100111100000110000010000110001000000000100001010100100110000010001111100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.7.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.7.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............8 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.8.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.8.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.8.1.1" ]; # processed EVENT: 1.2.1.2.8.2.1 # processed EVENT: 1.2.1.2.8.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011001111110000010011111101101111101101111100000000010110001111010000011101100000011000001 11001010001111010110101111000011001110101111010110111110110110111111]; # processed EVENT: 1.2.1.2.8.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011001111110100010011111101101111101101111100000000010110001111010000011101100000011000001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.8.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110000010011111101101111101101111100000000010110001111010000011101100000001001001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110000010011111101101111101101111100000000010110001111010000011101100000001001001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110100010011111101101111101101111100000000010110001111010000011101100000001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.8.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.8.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............9 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.9.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.9.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.9.1.1" ]; # processed EVENT: 1.2.1.2.9.2.1 # processed EVENT: 1.2.1.2.9.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001000000 01110001101100011110000001110100010001010001111010000111011001000100]; # processed EVENT: 1.2.1.2.9.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011100010100101011010111110001110010101100101111000000110011000011100100001000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.9.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011100010100101011010111110001110010101100101111000000110011000011100100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.9.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.9.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............10 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.10.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.10.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.10.1.1" ]; # processed EVENT: 1.2.1.2.10.2.1 # processed EVENT: 1.2.1.2.10.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001100111 10001111010010100011101111010001010000101010001001010101111000001100]; # processed EVENT: 1.2.1.2.10.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101110111011100100101010001110001110010001110000111111101101101000010000001100111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.10.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001101111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001101111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101110111011100100101010001110001110010001110000111111101101101000010000001101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.10.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.10.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............11 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.11.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.11.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.11.1.1" ]; # processed EVENT: 1.2.1.2.11.2.1 # processed EVENT: 1.2.1.2.11.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000100011 10111110110110001011011001010101010011101000101100100101011001001110]; # processed EVENT: 1.2.1.2.11.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000110001011011100100001000011110011111000011000110001000100110111111000000100011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.11.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000101011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000101011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000110001011011100100001000011110011111000011000110001000100110111111000000101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.11.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.11.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............12 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.12.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.12.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.12.1.1" ]; # processed EVENT: 1.2.1.2.12.2.1 # processed EVENT: 1.2.1.2.12.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001100010 11100111101011110111000001101011111001111111011110000110101010001101]; # processed EVENT: 1.2.1.2.12.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100101000100000011100000011100011100101111100010000011100011011110101100001100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.12.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100101000100000011100000011100011100101111100010000011100011011110101100001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.12.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.12.4.1" ], #*****************************************************************************# # TEST PROCEDURE............3 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............1 PERCENT STATIC FAULTS.....87.096382 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.3.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.3.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.3.1.1.1" ]; # processed EVENT: 1.2.1.3.1.2.1 # processed EVENT: 1.2.1.3.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011101100100010100111010011010110011111000100010100101101011111010000111010010000010100010 00111100111111000100011000110101011101011100010000100011011000111001]; # processed EVENT: 1.2.1.3.1.3.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100010100111010011010110011111000100010100101101011111010000111010010000000101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100010100111010011010110011111000100010100101101011111010000111010010000000101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100110100111010011010110011111000100010100101101011111010000111010010000000101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.3.1.3.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.3.1.3.1" ], #*****************************************************************************# # TEST PROCEDURE............4 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............28 PERCENT STATIC FAULTS.....87.433739 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.4.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.1.1" ]; # processed EVENT: 1.2.1.4.1.2.1 # processed EVENT: 1.2.1.4.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011101110110001001110010001100001001000101100010011010100100011110101100111001000010100101 01111001110111100101001001010110011000001110010010001101100100101110]; # processed EVENT: 1.2.1.4.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011101110110101001110010001100001001000101100010011010100100011110101100111001000010100101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.4.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011100110110001001110010001100001001000101100010011010100100011110101100111001000000101101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011100110110101001110010001100001001000101100010011010100100011110101100111001000000101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX], input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.4.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.4.1" ]; # processed EVENT: 1.2.1.4.1.5.1 # processed EVENT: 1.2.1.4.1.5.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100101011100001000000001000000101010010111000100000000100000010101001011100010000000000000 01000101011001000111010110011101001101010100011110101100111001001100]; # processed EVENT: 1.2.1.4.1.6.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100101011100101000000001000000101010010111000100000000100000010101001011100010000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.4.1.7.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100001000000001000000101010010111000100000000100000010101001011100010000000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100001000000001000000101010010111000100000000100000010101001011100010000000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100101000000001000000101010010111000100000000100000010101001011100010000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.7.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.7.1" ], #*****************************************************************************# # TEST PROCEDURE............5 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............164 PERCENT STATIC FAULTS.....89.409637 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.1.1.1" ]; # processed EVENT: 1.2.1.5.1.2.1 # processed EVENT: 1.2.1.5.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011001101011010001101011011111000111101111101000110110101011010000000101011111000001100100 00000001001000000101100101110010000000010000010101010111000100000000]; # processed EVENT: 1.2.1.5.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011001101011110001101011011111000111101111101000110110101011010000000101011111000001100100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011010001101011011111000111101111101000110110101011010000000101011111000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011010001101011011111000111101111101000110110101011010000000101011111000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011110001101011011111000111101111101000110110101011010000000101011111000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.1.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.1.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............2 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.2.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.2.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.2.1.1" ]; # processed EVENT: 1.2.1.5.2.2.1 # processed EVENT: 1.2.1.5.2.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101101001110001100010011100100010010110001111100000111111011100001100000111000100010001000 00110100001101111010000001010111011100010110100101000101101011101001]; # processed EVENT: 1.2.1.5.2.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101101001110101100010011100100010010110001111100000111111011100001100000111000100010001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.2.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110001100010011100100010010110001111100000111111011100001100000111000100000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110001100010011100100010010110001111100000111111011100001100000111000100000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110101100010011100100010010110001111100000111111011100001100000111000100000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.2.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.2.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............3 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.3.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.3.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.3.1.1" ]; # processed EVENT: 1.2.1.5.3.2.1 # processed EVENT: 1.2.1.5.3.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001101001000001101100001101100000100111011010110000111101010100111011111000001000000000110 00011001011111110101111110011111110001101101001111100101110101100100]; # processed EVENT: 1.2.1.5.3.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001101001000101101100001101100000100111011010110000111101010100111011111000001000000000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.3.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000001101100001101100000100111011010110000111101010100111011111000001000000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000001101100001101100000100111011010110000111101010100111011111000001000000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000101101100001101100000100111011010110000111101010100111011111000001000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.3.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.3.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............4 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.4.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.4.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.4.1.1" ]; # processed EVENT: 1.2.1.5.4.2.1 # processed EVENT: 1.2.1.5.4.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110001000111011110110100100100111110111101000011111110110101010011001101111001000000000111 00000101001000011010001101100001000110010001101000110110000000011000]; # processed EVENT: 1.2.1.5.4.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110001000111111110110100100100111110111101000011111110110101010011001101111001000000000111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.4.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111011110110100100100111110111101000011111110110101010011001101111001000000001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111011110110100100100111110111101000011111110110101010011001101111001000000001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111111110110100100100111110111101000011111110110101010011001101111001000000001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.4.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.4.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............5 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.5.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.5.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.5.1.1" ]; # processed EVENT: 1.2.1.5.5.2.1 # processed EVENT: 1.2.1.5.5.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101001100011110011011100011101011011001100111100110111000111010101100110011100001000011 10011110111110110100010011001110100100011111100100110100110011010100]; # processed EVENT: 1.2.1.5.5.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101001100111110011011100011101011011001100111100110111000111010101100110011100001000011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.5.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100011110011011100011101011011001100111100110111000111010101100110011100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100011110011011100011101011011001100111100110111000111010101100110011100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100111110011011100011101011011001100111100110111000111010101100110011100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.5.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.5.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............6 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.6.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.6.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.6.1.1" ]; # processed EVENT: 1.2.1.5.6.2.1 # processed EVENT: 1.2.1.5.6.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000000010 00000001011110000111000111101001101001010100011111111101000010010001]; # processed EVENT: 1.2.1.5.6.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000100110111001111011000001010011000001111001001111011000000101001010000000000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.6.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000100110111001111011000001010011000001111001001111011000000101001010000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.6.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.6.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............7 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.7.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.7.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.7.1.1" ]; # processed EVENT: 1.2.1.5.7.2.1 # processed EVENT: 1.2.1.5.7.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110010011111111000011111100011100001011111111100001111110001110000101000001101001 10100001001110011110101101101101001000011000001001101100110100110010]; # processed EVENT: 1.2.1.5.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110110011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.7.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110010011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110010011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110110011111111000011111100011100001011111111100001111110001110000101000001101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.7.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.7.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............8 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.8.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.8.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.8.1.1" ]; # processed EVENT: 1.2.1.5.8.2.1 # processed EVENT: 1.2.1.5.8.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111101100000001110111011111101101111011111101111111110100101010111111101111111100000000110 01001110101001101110011101001101011010000101011000000000101101101110]; # processed EVENT: 1.2.1.5.8.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111101100000101110111011111101101111011111101111111110100101010111111101111111100000000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.8.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000001110111011111101101111011111101111111110100101010111111101111111100000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000001110111011111101101111011111101111111110100101010111111101111111100000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000101110111011111101101111011111101111111110100101010111111101111111100000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.8.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.8.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............9 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.9.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.9.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.9.1.1" ]; # processed EVENT: 1.2.1.5.9.2.1 # processed EVENT: 1.2.1.5.9.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000000101 01011100001101110100001111000111111010000001110001111100100011010001]; # processed EVENT: 1.2.1.5.9.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011101010111000001110110000000011001000111000100110111000000011101000000000000101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.9.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000001101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000001101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011101010111000001110110000000011001000111000100110111000000011101000000000001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.9.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.9.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............10 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.10.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.10.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.10.1.1" ]; # processed EVENT: 1.2.1.5.10.2.1 # processed EVENT: 1.2.1.5.10.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001101000001000111111110010100011010101110001000010111001100110011101100011110100001000010 01101011001010100101100000111000000010010011111111110010100110000101]; # processed EVENT: 1.2.1.5.10.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001101000001100111111110010100011010101110001000010111001100110011101100011110100001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.10.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001000111111110010100011010101110001000010111001100110011101100011110100001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001000111111110010100011010101110001000010111001100110011101100011110100001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001100111111110010100011010101110001000010111001100110011101100011110100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.10.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.10.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............11 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.11.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.11.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.11.1.1" ]; # processed EVENT: 1.2.1.5.11.2.1 # processed EVENT: 1.2.1.5.11.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111101011000011111111000010000011111110110001111110101100000110111011101100100000011100010 00110000111111110110111011000110110111110110001010000111101111011111]; # processed EVENT: 1.2.1.5.11.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111101011000111111111000010000011111110110001111110101100000110111011101100100000011100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.11.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000011111111000010000011111110110001111110101100000110111011101100100000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000011111111000010000011111110110001111110101100000110111011101100100000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000111111111000010000011111110110001111110101100000110111011101100100000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.11.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.11.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............12 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.12.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.12.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.12.1.1" ]; # processed EVENT: 1.2.1.5.12.2.1 # processed EVENT: 1.2.1.5.12.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001000010 11110100110101001010100111011001101011100100101011011101101010101110]; # processed EVENT: 1.2.1.5.12.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100101000101011010101000010110110100100011111101111010101000000111001000001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.12.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100101000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.12.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.12.4.1" ]; end end 2.1.5.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110110011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.7.4.1 # inserted SEQUENCEINTERFACES/VERILOG_TB/WGLVERILOG/exp2.vtran000064400001440000012000000045331140376053500204510ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > VERILOG # # Original File: "exp1.wgl" # # Target File: "exp2.ver " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK { input file spec } begin ORIG_FILE = "exp1.wgl"; {#### INPUT VECTOR FILE ####} TABULAR_FORMAT wgl; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } PROC_BLOCK begin state_trans outputs '-'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK begin target_file = "exp2.ver"; {#### OUTPUT VECTOR FILE ####} SIMULATOR verilog_tb {#### OUTPUT FORMAT ####} -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", ; end; INTERFACES/VERILOG_TB/WGLVERILOG/insertstmt.vtran000064400001440000012000000054241103104161000217660ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > Verilog TestBench # # Original File: "exp4.wgl" # # Target File: "exp4.ver " # # Command File: "insertstmt.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format wgl ; {#### INPUT FORMAT ####} orig_file "../../DATA/exp4.wgl"; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into Verilog TestBench format # #======================================================================# } proc_block begin INSERT_STATEMENT "/* This is first addition */" @ CONDITION in0 = 0; INSERT_STATEMENT "/* This is second addition */" @ TRANSITION in1 0N ; INSERT_STATEMENT "/* This is third addition */" @ TRANSITION ACK0 0-1 ; INSERT_STATEMENT "/* This is fourth addition */" @ TRANSITION -count 3 BCK0 1->0 ; INSERT_STATEMENT "/* This is fifth addition */" @ TIME -after 1080; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin target_file "exp4.ver"; {#### OUTPUT VECTOR FILE ####} SIMULATOR verilog_tb {#### OUTPUT FORMAT ####} -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", ; end; end; INTERFACES/VERILOG_TB/VCDVERILOG/000075500001440000012000000000001103104161000164545ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/VCDVERILOG/exp3.vtran000064400001440000012000000165261103104161000204210ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > VERILOG TEST # # Original File: "exp3.vcd" # # Target File: "exp3.ver " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN ORIG_FILE = "../../DATA/exp3.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS { ##### memory interface input-only pads ##### } p_mrdy_, { MRDY* pin } p_mintr_, { MINTR* pin } { ##### LXT901 interface input-only pads ##### } p_tclk, { #### TCLK pin #### } p_rxd[3:0], { #### RXD pins #### } p_rclk, { #### RCLK pins ####} p_crs, { #### CRS pin #### } p_rx_dv, { #### RX_DV pin ####} p_rx_er, { #### RX_ER pin ####} p_col, { #### COL pin #### } { ##### PCI bus input-only pads ##### } p_pci_clk, { #### PCI bus CLK pin #### } p_rst_, { #### PCI bus RST* pin #### } p_gnt_, { #### GNT* pin #### } p_idsel, { #### IDSEL* pin #### } p_tst_, { #### TST* pin #### } { #### clock input-only pads ##### } p_sysclk; { #### 50 MHz system clock (SYSCLK) pin #### } BIDIRECTS { #### memory interface bidirectional pads #### } p_mdata[31:0], { #### MDATA[31:0] pins #### } { #### PCI bus bidirectional pads #### } p_ad[31:0], { #### A/D pins #### } p_cbe_[3:0], { #### C/BE pins #### } p_par, { #### PAR pin #### } p_frame_, { #### FRAME* pin #### } p_irdy_, { #### IRDY* pin #### } p_trdy_, { #### TRDY* pin #### } p_stop_, { #### STOP* pin #### } p_devsel_, { #### DEVSEL* pin #### } p_perr_, { #### PERR* pin #### } p_mdio; { #### MDIO pin #### } OUTPUTS { #### memory interface output-only pads #### } p_maddr[17:0], { #### MADDR* pin ####} p_mcs_[3:0], { #### MCS* pin #### } p_ras_, { #### RAS* pin #### } p_mrd_, { #### MRD* pin #### } p_mwe_[3:0], { #### MWE* pin #### } p_mgwe_, { #### MGWE #### } p_mclk, { #### MCLK pin #### } { #### LXT901 interface output-only pads #### } p_txd[3:0], { #### TXD pins #### } p_tx_en, { #### TX_EN pin ####} p_lbk, { #### LBK pin #### } p_mdc, { #### MDC pin #### } { #### PCI bus output-only pads #### } p_req_, { #### REQ* pin ####} p_serr_, { #### SERR* pin #### } p_int_, { #### INT* pin #### } { #### clock generator output-only pads #### } p_clk25, { #### CLK25 pin #### } { #### ERST_ pin #### } p_erst_, { #### ERST_ pin #### } { #### Debug pin #### } p_dbg[2:0], { ####DBG pin #### } { #### Enables #### } mdata_oe, oe_ad, oe_cbe, oe_par, oe_frame, oe_irdy, oe_slave, oe_serr, oe_perr; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } PROC_BLOCK BEGIN { ******* Bi-directional control specifications ******** } { ------------------------------------------------------ } BIDIRECT_CONTROL p_mdata = output when mdata_oe = 1; BIDIRECT_CONTROL p_ad = output when oe_ad = 1; BIDIRECT_CONTROL p_cbe_ = output when oe_cbe = 1; BIDIRECT_CONTROL p_par = output when oe_par = 1; BIDIRECT_CONTROL p_frame_ = output when oe_frame = 1; BIDIRECT_CONTROL p_irdy_ = output when oe_irdy = 1; BIDIRECT_CONTROL p_trdy_ = output when oe_slave = 1; BIDIRECT_CONTROL p_stop_ = output when oe_slave = 1; BIDIRECT_CONTROL p_devsel_ = output when oe_slave = 1; BIDIRECT_CONTROL p_perr_ = output when oe_perr = 1; BIDIRECT_CONTROL p_serr_ = output when oe_serr = 1; { ******* Set a 20 ns cycle (20ns clock period) ******** } { ------------------------------------------------------ } CYCLE = 20; EDGE_ALIGN p_sysclk @ 0,10; { clean edges up on this } { ******* Don't care is an 'X' ******** } { ------------------------------------------------------ } DONT_CARE = 'X'; { ******* Output strobing windows ******** } { ------------------------------------------------------ } CHECK_WINDOW { ##### memory interface bidirectional pads ##### } p_mdata[31:0], { ##### MDATA[31:0] pins ##### } { ##### PCI bus bidirectional pads ##### } p_ad[31:0], { ##### A/D pins #####} p_cbe_[3:0], { ##### C/BE pins #####} p_par, { ##### PAR pin #####} p_frame_, { ##### FRAME* pin ##### } p_irdy_, { ##### IRDY* pin ##### } p_trdy_, { ##### TRDY* pin #####} p_stop_, { ##### STOP* pin #####} p_devsel_, { ##### DEVSEL* pin ##### } p_perr_, { ##### PERR* pin #####} p_mdio, { ##### MDIO pin ##### } { ##### memory interface output-only pads ##### } p_maddr[17:0], { ##### MADDR* pin #####} p_mcs_[3:0], { ##### MCS* pin ##### } p_ras_, { ##### RAS* pin ##### } p_mrd_, { ##### MRD* pin ##### } p_mwe_[3:0], { ##### MWE* pin ##### } p_mgwe_, { ##### MGWE ##### } p_mclk, { ##### MCLK pin ##### } { ##### LXT901 interface output-only pads ##### } p_txd[3:0], { ##### TXD pins ##### } p_tx_en, { ##### TX_EN pin ##### } p_lbk, { ##### LBK pin ##### } p_mdc, { ##### MDC pin ##### } { ##### PCI bus output-only pads ##### } p_req_, { ##### REQ* pin ##### } p_serr_, { ##### SERR* pin ##### } p_int_, { ##### INT* pin ##### } { ##### clock generator output-only pads #####} p_clk25, { ##### CLK25 pin #####} { ##### ERST_ pin ##### } p_erst_, { ##### ERST_ pin ##### } { ##### Debug pin ##### } p_dbg[2:0], { ##### DBG pin ##### } @ 18,19; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN resolution 0.001; target_file = "exp3.ver"; {#### OUTPUT VECTOR FILE ####} SIMULATOR verilog_tb_readmem {#### OUTPUT FORMAT ####} MODULE="test_fed" OUTPUT_GROUP = "p_dbg[2:0]" OUTPUT_GROUP = "p_clk25, p_erst_" INPUT_GROUP = "p_pci_clk, p_rst_, p_gnt_, p_idsel" ; { ##### Internal Enables ##### } DELETE_PINS mdata_oe, oe_ad, oe_cbe, oe_par, oe_frame, oe_irdy, oe_slave, oe_serr, oe_perr; END; END; INTERFACES/VERILOG_TB/VCDVERILOG/exp1.vtran000064400001440000012000000100551103104161000204060ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > VERILOG TEST # # Original File: "exp1.vcd" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ##### INPUT/OUTPUT PIN DESCRIPTION #### } INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; PROC_BLOCK { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and too do state translations. * } { * * } { ************************************************************ } BEGIN cycle 250; {4 MHz cycle} BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; check_window * @ 195, 200; { strobe all outs at 195 } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK { ************************************************************ } { * * } { * Define simulation configurations here. Currently * } { * configured for VHDL * } { * * } { ************************************************************ } BEGIN target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} { You can use these lines if you wish to use readmem } { SIMULATOR verilog_tb_readmem } { You can use this line if you wish to use in-line code } SIMULATOR verilog_tb -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", { DATAFILES = "one.dat", } { used by readmem only } { INPUT_GROUP = "xclk, qavd, qavs" } { used by readmem only } ; { IF you wish to exclude pins, like enables, add the following: } DELETE_PINS fake_oe, cx24[3:0]; END; ============================# # This is vtran command file. # # Translation: VCD < to > VERILOG TEST # # Original File: "exp1.vcd" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" #INTERFACES/VERILOG_TB/STILVERILOG/000075500001440000012000000000001103104161000166135ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/STILVERILOG/exp1.vtran000064400001440000012000000051061103104161000205460ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > VERILOG TESTBENCH # # Original File: "exp1.stil" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'VERILOG TEST BENCH'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block SIMULATOR verilog_tb {#### OUTPUT FORMAT ####} -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", ; target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/VERILOG_TB/PCFVERILOG/000075500001440000012000000000001103104161000164505ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/PCFVERILOG/exp1.pcf000064400001440000012000000247701103104161000200310ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.pcf" # # Original File: "exp1.pcf" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# !!!! 6 0 1 919712330 V79b1 ! Hewlett-Packard Boundary-Scan Software [980415] ! VCL created from BSDL (Version 0.0) file: 74bct8374 ! Date: Mon Feb 22 12:38:52 1999 ! IEEE Std 1149.1-1990 !! Writing code for HP-3070 family. ! Parameters for Entity TTL74BCT8374: ! Instruction Length 8 ! Boundary Register Length 18 ! Device Inputs 10 ! Device Outputs 8 ! Device Bidirectionals 0 sequential family TTL !! Warning, Defaulted family ! default device "u1" ! Library compile default, change for executable ! The following assignments are derived from Pin-Mapping DW_PACKAGE. assign CLK to pins "1" assign D__01 to pins "23" assign D__02 to pins "22" assign D__03 to pins "21" assign D__04 to pins "20" assign D__05 to pins "19" assign D__06 to pins "17" assign D__07 to pins "16" assign D__08 to pins "15" assign GND to pins "6" assign OC_NEG to pins "24" assign Q__01 to pins "2" assign Q__02 to pins "3" assign Q__03 to pins "4" assign Q__04 to pins "5" assign Q__05 to pins "7" assign Q__06 to pins "8" assign Q__07 to pins "9" assign Q__08 to pins "10" assign TCK to pins "13" assign TDI to pins "14" assign TDO to pins "11" assign TMS to pins "12" assign VCC to pins "18" power GND, VCC inputs CLK, D__01, D__02, D__03, D__04 inputs D__05, D__06, D__07, D__08, OC_NEG inputs TCK, TDI, TMS outputs Q__01, Q__02, Q__03, Q__04, Q__05 outputs Q__06, Q__07, Q__08, TDO ! vector cycle 500n receive delay 400n pcf order default Parallel is TCK, TMS, TDI, TDO pcf order default Parallel is CLK, D__01, D__02, D__03, D__04 pcf order default Parallel is D__05, D__06, D__07, D__08, OC_NEG pcf order default Parallel is Q__01, Q__02, Q__03, Q__04, Q__05 pcf order default Parallel is Q__06, Q__07, Q__08 ! pcf order Scan is TCK, TMS, TDI, TDO !Column-to-signal Map, signals 1 to 22 !TTTTCDDDDDDDDOQQQQQQQQ! !CMDDL________C________! !KSIOK_________________! ! 00000000N00000000! ! 12345678E12345678! ! G ! ! ! !! unit "Init_Parallel_Toggle" ! Vector 1 pcf use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX"! Test-Logic-Reset ! Current instruction BYPASS (11111111), target register BYPASS[1]. "00ZX" "10ZX"! Run-Test/Idle use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Select-DR-Scan "01ZX" "11ZX"! Select-IR-Scan "00ZX" "10ZX"! Capture-IR ! Instruction register loaded with 10000001 (BYPASS) "00ZX" "10ZX"! Shift-IR end pcf message "1149.1 Instruction Register Failure." pcf use pcf order Scan "000H"! 0 "100X" ! Vector 25 "001L"! 1 "101X" "000L"! 2 "100X" "000L"! 3 "100X" "000L"! 4 "100X" "000L"! 5 "100X" "000L"! 6 "100X" "010H"! 7 "110X"! Exit1-IR end pcf message "" pcf use pcf order Scan "01ZX" "11ZX"! Update-IR "01ZX" ! Current instruction SAMPLE (00000010), target register BOUNDARY[18]. "11ZX"! Select-DR-Scan use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "10ZX"! Capture-DR use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" "10ZXZZZZZZZZZZXXXXXXXX"! Shift-DR ! Target BOUNDARY[18] = XXXXXXXXXXXXXXXXXX "00ZXZZZZZZZZZZXXXXXXXX"! 0 use pcf order Scan "10ZX" "00ZX"! 1 ! Vector 50 "10ZX" "00ZX"! 2 "10ZX" "00ZX"! 3 "10ZX" "00ZX"! 4 "10ZX" "00ZX"! 5 "10ZX" "00ZX"! 6 "10ZX" "00ZX"! 7 "10ZX" "00ZX"! 8 "10ZX" "00ZX"! 9 "10ZX" "00ZX"! 10 "10ZX" "00ZX"! 11 "10ZX" "00ZX"! 12 "10ZX" "00ZX"! 13 "10ZX" ! Vector 75 "00ZX"! 14 "10ZX" "00ZX"! 15 "10ZX" "001X"! 16 "101X" "01ZX"! 17 "11ZX"! Exit1-DR ! Target BOUNDARY[18] = X1XXXXXXXXXXXXXXXX use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Update-DR "01ZX" "11ZX"! Select-DR-Scan "01ZX" "11ZX"! Select-IR-Scan "00ZX" "10ZX"! Capture-IR ! Instruction register loaded with 10000001 (BYPASS) "00ZX" "10ZX"! Shift-IR end pcf message "1149.1 Instruction Register Failure." pcf use pcf order Scan "000H"! 0 "100X" "000L"! 1 "100X" "000L"! 2 "100X" "000L"! 3 ! Vector 100 "100X" "000L"! 4 "100X" "000L"! 5 "100X" "000L"! 6 "100X" "010H"! 7 "110X"! Exit1-IR end pcf message "" pcf use pcf order Scan "01ZX" "11ZX"! Update-IR use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" ! Current instruction EXTEST (00000000), target register BOUNDARY[18]. "11ZXZZZZZZZZZZXXXXXXXX"! Select-DR-Scan end pcf end unit ! Init_Parallel_Toggle Vector 112 ! unit "Inputs_0_1" ! Vector 113 pcf use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "10ZX"! Capture-DR use pcf order Parallel "00ZX0101010101XXXXXXXX" "10ZX0101010101XXXXXXXX"! Shift-DR ! Target BOUNDARY[18] = 0110101010XXXXXXXX "00ZXZZZZZZZZZZXXXXXXXX"! 0 use pcf order Scan "10ZX" "00ZX"! 1 "10ZX" "00ZX"! 2 "10ZX" "00ZX"! 3 "10ZX" ! Vector 125 "00ZX"! 4 "10ZX" "00ZX"! 5 "10ZX" "00ZX"! 6 "10ZX" "00ZX"! 7 "10ZX" end pcf message "Pin 15 failed high." pcf use pcf order Scan "00ZL"! 8 "10ZX" end pcf message "Pin 16 failed low." pcf use pcf order Scan "00ZH"! 9 "10ZX" end pcf message "Pin 17 failed high." pcf use pcf order Scan "00ZL"! 10 "10ZX" end pcf message "Pin 19 failed low." pcf use pcf order Scan "00ZH"! 11 "10ZX" end pcf message "Pin 20 failed high." pcf use pcf order Scan "00ZL"! 12 "10ZX" end pcf message "Pin 21 failed low." pcf use pcf order Scan "00ZH"! 13 "10ZX" end pcf message "Pin 22 failed high." pcf use pcf order Scan "00ZL"! 14 "10ZX" end pcf message "Pin 23 failed low." pcf use pcf order Scan "00ZH"! 15 "10ZX" end pcf message "Pin 24 failed low." pcf use pcf order Scan "001H"! 16 ! Vector 150 "101X" end pcf message "Pin 1 failed high." pcf use pcf order Scan "01ZL"! 17 "11ZX"! Exit1-DR ! Target BOUNDARY[18] = X1XXXXXXXXXXXXXXXX end pcf message "" pcf use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Update-DR use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" "11ZXZZZZZZZZZZXXXXXXXX"! Select-DR-Scan end pcf end unit ! Inputs_0_1 Vector 156 ! unit "Inputs_1_0" ! Vector 157 pcf use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "10ZX"! Capture-DR use pcf order Parallel "00ZX1010101010XXXXXXXX" "10ZX1010101010XXXXXXXX"! Shift-DR ! Target BOUNDARY[18] = 1001010101XXXXXXXX "00ZXZZZZZZZZZZXXXXXXXX"! 0 use pcf order Scan "10ZX" "00ZX"! 1 "10ZX" "00ZX"! 2 "10ZX" "00ZX"! 3 "10ZX" "00ZX"! 4 "10ZX" "00ZX"! 5 "10ZX" "00ZX"! 6 "10ZX" ! Vector 175 "00ZX"! 7 "10ZX" end pcf message "Pin 15 failed low." pcf use pcf order Scan "00ZH"! 8 "10ZX" end pcf message "Pin 16 failed high." pcf use pcf order Scan "00ZL"! 9 "10ZX" end pcf message "Pin 17 failed low." pcf use pcf order Scan "00ZH"! 10 "10ZX" end pcf message "Pin 19 failed high." pcf use pcf order Scan "00ZL"! 11 "10ZX" end pcf message "Pin 20 failed low." pcf use pcf order Scan "00ZH"! 12 "10ZX" end pcf message "Pin 21 failed high." pcf use pcf order Scan "00ZL"! 13 "10ZX" end pcf message "Pin 22 failed low." pcf use pcf order Scan "00ZH"! 14 "10ZX" end pcf message "Pin 23 failed high." pcf use pcf order Scan "00ZL"! 15 "10ZX" end pcf message "Pin 24 failed high." pcf use pcf order Scan "001L"! 16 "101X" end pcf message "Pin 1 failed low." pcf use pcf order Scan "01ZH"! 17 "11ZX"! Exit1-DR ! Target BOUNDARY[18] = X1XXXXXXXXXXXXXXXX end pcf message "" pcf use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Update-DR use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" ! Vector 200 "11ZXZZZZZZZZZZXXXXXXXX"! Select-DR-Scan end pcf end unit ! Inputs_1_0 Vector 200 ! unit "Outputs_High_Low" ! Vector 201 pcf use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "10ZX"! Capture-DR use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" "10ZXZZZZZZZZZZXXXXXXXX"! Shift-DR ! Target BOUNDARY[18] = XXXXXXXXXXXXXXXXXX "001XZZZZZZZZZZXXXXXXXX"! 0 use pcf order Scan "101X" "000X"! 1 "100X" "001X"! 2 "101X" "000X"! 3 "100X" "001X"! 4 "101X" "000X"! 5 "100X" "001X"! 6 "101X" "000X"! 7 "100X" "00ZX"! 8 "10ZX" "00ZX"! 9 "10ZX" ! Vector 225 "00ZX"! 10 "10ZX" "00ZX"! 11 "10ZX" "00ZX"! 12 "10ZX" "00ZX"! 13 "10ZX" "00ZX"! 14 "10ZX" "00ZX"! 15 "10ZX" "000X"! 16 "100X" "01ZX"! 17 "11ZX"! Exit1-DR ! Target BOUNDARY[18] = X0XXXXXXXX01010101 use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Update-DR use pcf order Parallel "01ZXZZZZZZZZZZLHLHLHLH" "11ZXZZZZZZZZZZXXXXXXXX"! Select-DR-Scan end pcf end unit ! Outputs_High_Low Vector 244 ! unit "Outputs_Low_High" ! Vector 245 pcf use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "10ZX"! Capture-DR use pcf order Parallel "00ZXZZZZZZZZZZXXXXXXXX" "10ZXZZZZZZZZZZXXXXXXXX"! Shift-DR ! Target BOUNDARY[18] = XXXXXXXXXXXXXXXXXX "000XZZZZZZZZZZXXXXXXXX"! 0 ! Vector 250 use pcf order Scan "100X" "001X"! 1 "101X" "000X"! 2 "100X" "001X"! 3 "101X" "000X"! 4 "100X" "001X"! 5 "101X" "000X"! 6 "100X" "001X"! 7 "101X" "00ZX"! 8 "10ZX" "00ZX"! 9 "10ZX" "00ZX"! 10 "10ZX" "00ZX"! 11 "10ZX" "00ZX"! 12 "10ZX" ! Vector 275 "00ZX"! 13 "10ZX" "00ZX"! 14 "10ZX" "00ZX"! 15 "10ZX" "000X"! 16 "100X" "01ZX"! 17 "11ZX"! Exit1-DR ! Target BOUNDARY[18] = X0XXXXXXXX10101010 use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX"! Update-DR use pcf order Parallel "01ZXZZZZZZZZZZHLHLHLHL" "11ZXZZZZZZZZZZXXXXXXXX"! Select-DR-Scan end pcf end unit ! Outputs_Low_High Vector 288 ! unit "Reset_Parallel_Toggle" ! Vector 289 pcf use pcf order Parallel "01ZXZZZZZZZZZZXXXXXXXX" use pcf order Scan "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" ! Vector 300 "11ZX"! Test-Logic-Reset ! Current instruction BYPASS (11111111), target register BYPASS[1]. "01ZX" "11ZX"! Test-Logic-Reset end pcf end unit ! Reset_Parallel_Toggle Vector 302 ! Vectors with TDI High: 24, (1.2e-05 sec) ! Vectors with TDI Low: 50, (2.5e-05 sec) ! Total time for test: (1.5e-04 sec) INTERFACES/VERILOG_TB/PCFVERILOG/exp1.vtran000064400001440000012000000045661103104161000204140ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: PCF < to > VERILOG TEST BENCH # # Original File: "exp1.pcf" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "exp1.pcf"; {#### INPUT VECTOR FILE ####} tabular_format pcf; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the PCF # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin { #### state character translations for 'PCF'->'VERILOG TEST BENCH'#### } state_trans outputs 'H'->'1', 'L'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 500; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, testbench_module = "PentiumIV_tb", component_module = "PentiumIV" ; target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/VERILOG_TB/EVCDVERILOG/000075500001440000012000000000001103104161000165615ustar00jcosleystaff00000400000023INTERFACES/VERILOG_TB/EVCDVERILOG/exp1.vtran000064400001440000012000000100161107520210200205130ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > VERILOG TEST BENCH # # Original File: "exp1.evcd" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'VERILOG TEST BENCH' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; header 500; simulator verilog_tb {#### OUTPUT FORMAT ####} -verbose, testbench_module = "PentiumIV_tb", component_module = "PentiumIV" ; target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} end; INTERFACES/VERILOG_TB/README000064400001440000012000000220631103104161000156730ustar00jcosleystaff00000400000023VERILOG TEST BENCH ------------------ The main directory is "VERILOG_TB" and the sub-directories are -> WGLVERILOG -> STILVERILOG -> VCDVERILOG -> EVCDVERILOG -> PCFVERILOG The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLVERILOG" contains the translation of WGL file to VERILOG output format. Sub-directory -> "EVCDVERILOG" contains the translation of EVCD file to VERILOG output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... This directory contains some examples of translating Verilog VCD vectors created during simulation, WGL and STIL vectors generated by ATPG tools, to Verilog testbench modules, which includes checking of expected output state data for re-simulation verification. There are two options for the Verilog testbench format. The Verilog testbench can be generated with straight in-line assignments and checking of signal states, or in a format which uses $readmem to get state data from a separate external file. The first format gives a longer compile time (since all data in is a single file) but would likely run faster during simulation, whereas the second format would have a much shorter compile time, but perhaps slightly slower run time (since state data is being read from an external file). For the first format (verilog_tb), the optional parameters are: SIMULATOR verilog_tb, -VERBOSE, -INHIBIT_CHECKING, -VERIFAULT, TESTBENCH_MODULE = "Top_of_generic", COMPONENT_MODULE = "Component_of_generic", INSTANCE_NAME = "Instance_of_generic", TIMESCALE = "1ns/100ps", OUTPUT_GROUP = "pin3, pin4, .. " PSEUDO_SIGNAL = "pinname", TERMINATE_RUN = "$finish", MAX_MISMATCHES = "nn" ; The -INHIBIT_CHECKING flag tells vtran not to include expected output state checking in the Verilog testbench. The -VERBOSE results in a more detailed error report when expected output data does not match simulation data. The -VERIFAULT flag will produce a verilog testbench file which can be run on Verifault. The PSEUDO_SIGNAL parameter provides for a way to identify signals in the OVF file which are not to be included in the instantiation of the component within the testbench. These signals would only be part of the testbench-level circuit, not the design component. Multiple PSEUDO_SIGNAL parameters can be used. The default TIMESCALE for time stamps is (1) Nanosecond, which matches the default for vtran time stamps. If more resolution is desired use the TIMESCALE parameter - all timestamps in the output file will be scaled automatically to match the timeunits. For example: simulator Verilog_tb, TIMESCALE = "100ps/1ps"; If the TIMESCALE parameter is missing, no timescale will be placed in the file. Vtran will place a $stop statement at the end of the testbench by default. This can be changed to $finish (or anything else desired) by using the TERMINATE_RUN parameter. If the states in the original vector file are not compatible with the Verilog states being used, the STATE_TRANS command should be used to map them as desired. When reading print-on-change (event driven) files, all outputs should have their strobe (check) timing specified with the CHECK_WINDOW command. For OVF files read using one of the canned readers (WGL, STIL, ..) where the output strobe times are specified in the file, this is not necessary. Pin strobe timing defined with the CHECK_WINDOW command also defines the output pin groups for verification. The OUTPUT_GROUP parameter provides another way to control the grouping of output signals to optimize the size of output file being generated. Vtran creates processes for output state checking which are invoked whenever at least one of the output pins is a non-DONT_CARE state at the specified CHECK_WINDOW time. The default DONT_CARE state is 'X', but this can also be changed with the DONT_CARE command. When specifying strobe timing for outputs with the CHECK_WINDOW command, it is also necessary to specify the CYCLE time (since the output check time is relative to the CYCLE). The TESTBENCH_MODULE, COMPONENT_MODULE and INSTANCE_NAME parameters allow the user to control some of the naming in the testbench. Again, OUTPUT_GROUP provides a way for the user to control the output pin groups, which in turn controls the size of output data file. The default grouping is determined by the CHECK_WINDOW commands in the command file if they are used. The MAX_MISMATCHES parameter, if present, will cause vtran to place code in the verilog testbench that monitors the number of output state mismatches which are found by the checking procedures, and terminate program execution if the number reaches this specified maximum. For the second format (verilog_tb_readmem), the optional parameters are: SIMULATOR verilog_tb_readmem, -VERBOSE, -INHIBIT_CHECKING, TESTBENCH_MODULE = "Top_of_generic", COMPONENT_MODULE = "Component_of_generic", INSTANCE_NAME = "Instance_of_generic", TIMESCALE = "1ns/100ps", INPUT_GROUP = "pin1, pin2, .. " OUTPUT_GROUP = "pin3, pin4, .. " PSEUDO_SIGNAL = "pinname", DATAFILES = "datafilename", TERMINATE_RUN = "$stop", MAX_MISMATCHES = "nn" ; Many of the parameters for this format are the same as for the verilog_tb format, and they perform identical functions. Additional parameters are: The DATAFILE parameter can be used to control the names of the data files that vtran generates. For a DATAFILES name of "datafilename", vtran will create state data files named datafilename0, datafilename1, datafilename2, . . . The ...0 data file contains delta times (times between events) and flags indicating which of the data files to read state data from for each event time. The ...1 file will contain state data for pure input pins, ...2 for bidir input pins and ...3 and up contain output signal expected data, grouped by their specified strobe times (CHECK_WINDOW) OUTPUT_GROUP's. In addition to these groupings, a user can also force specific input signals to be placed in a separate group (and hence separate data file) using the INPUT_GROUP parameter. This may be useful to help reduce overall data file sizes. For example, if the majority of event times in a set of vectors is associated with transitions of just a few clock pins, then defining these as an INPUT_GROUP would greatly reduce the size of the ...1 file (all the other input pins). Multiple INPUT_GROUP parameters can be specified. See the VTRAN User's Guide and the README7.x file for more information on these interfaces and the optional parameters available. An example command file for an WGL -> VERILOG TEST BENCH translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > VERILOG # # Original File: "exp1.wgl" # # Target File: "exp1.ver " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK { input file spec } begin ORIG_FILE = "exp1.wgl"; {#### INPUT VECTOR FILE ####} TABULAR_FORMAT wgl; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into VERILOG TEST BENCH format # #======================================================================# } PROC_BLOCK begin end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK begin target_file = "exp1.ver"; {#### OUTPUT VECTOR FILE ####} SIMULATOR verilog_tb_readmem {#### OUTPUT FORMAT ####} -VERBOSE, TESTBENCH_MODULE = "Top_Gun", COMPONENT_MODULE = "Comp_of_Gun", INSTANCE_NAME = "UUU21", TIMESCALE = "1ns/100ps", DATAFILES = "two.dat", {##### used by readmem only ####} INPUT_GROUP = "CLK, SDI0, SDI1, SCAN0, SCAN0_PI" { #### used by readmem only #### } ; end; ################################################################################ ODULE, COMPONENT_MODULE and INSTANCE_NAME parameters allow the user to control some of the naming in the testbench. Again, OUTPUT_GROUP provides a way for the user to control the output pin groups, which in turn controls the size of output data file. The default grouping is determined by the CHECK_WINDOW commands in the command file if they are used. The MAX_MISMATCHES parameter, if present, will cause vtran to place code in the verilog testbench thatINTERFACES/VHDL/000075500001440000012000000000001103104161000140515ustar00jcosleystaff00000400000023INTERFACES/VHDL/WGLVHDL/000075500001440000012000000000001103104161000151605ustar00jcosleystaff00000400000023INTERFACES/VHDL/WGLVHDL/exp1.vtran000064400001440000012000000052751103104161000171220ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: WGL < to > VHDL TEST BENCH # # Original File: "exp1.wgl" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK begin ORIG_FILE = "../../DATA/exp1.wgl"; {#### INPUT VECTOR FILE ####} TABULAR_FORMAT wgl; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } PROC_BLOCK begin end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK begin target_file = "exp1.vhd"; {#### OUTPUT VECTOR FILE ####} { #### You can use this lines if you wish to use TEXTIO ##### } { SIMULATOR vhdl_tb_tio } SIMULATOR vhdl_tb , {#### OUTPUT FORMAT ####} LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", OUTPUT_GROUP = "SDO0, SDO1", { #### group scan-out pins to reduce file size #### } LIST_ERRORS = "BY_PIN", { #### Can make this BY_GROUP #### } MAXLINES="10000"; TITLE "marylou"; end; INTERFACES/VHDL/WGLVHDL/exp1.wgl000064400001440000012000002543451103104161000165650ustar00jcosleystaff00000400000023#======================================================================# # This is the Original vector file "exp1.wgl" # # Original File: "exp1.wgl" # # Target File: "exp1. " vhd # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# #*****************************************************************************# # TESTBENCH 4.1.8 WGL VECTOR FILE # #*****************************************************************************# # # # ENTITY....................TESTARRAY # # VARIATION................. # # ITERATION................. # # # # TESTMODE..................gsd_static_negclk # # # # TDR.......................nstar_tdr # # # # TEST PERIOD...............16 STROBE OFFSET.............15 # # PULSE WIDTH...............2 STROBE TYPE...............window # # TIME UNITS................ns SCAN OVERLAP..............yes # # # # EXPERIMENT................1 # # # # TEST SECTION..............2 TEST SECTION TYPE.........logic # # TESTER TERMINATION........0 TERMINATION DOMINATION....tester # # # #*****************************************************************************# waveform "testarray2.ts2" signal "AADR<0>" : input; "AADR<1>" : input; "AADR<2>" : input; "AADR<3>" : input; "AADR<4>" : input; "AADR<5>" : input; "ABIST" : input; # -TI "ABIST_PI" : input; # -SG "BADR<0>" : input; "BADR<1>" : input; "BADR<2>" : input; "BADR<3>" : input; "BADR<4>" : input; "BADR<5>" : input; "CLK" : input; # -ES "DIN<0>" : input; "DIN<1>" : input; "DIN<2>" : input; "DIN<3>" : input; "DIN<4>" : input; "DIN<5>" : input; "DIN<6>" : input; "DIN<7>" : input; "DIN<8>" : input; "DIN<9>" : input; "DIN<10>" : input; "DIN<11>" : input; "DIN<12>" : input; "DIN<13>" : input; "DIN<14>" : input; "DIN<15>" : input; "DIN<16>" : input; "DIN<17>" : input; "DIN<18>" : input; "DIN<19>" : input; "DIN<20>" : input; "DIN<21>" : input; "DIN<22>" : input; "DIN<23>" : input; "DIN<24>" : input; "DIN<25>" : input; "DIN<26>" : input; "DIN<27>" : input; "DIN<28>" : input; "DIN<29>" : input; "DIN<30>" : input; "DIN<31>" : input; "DIN<32>" : input; "DIN<33>" : input; "DIN<34>" : input; "DIN<35>" : input; "DIN<36>" : input; "DIN<37>" : input; "DIN<38>" : input; "DIN<39>" : input; "DIN<40>" : input; "DIN<41>" : input; "DIN<42>" : input; "DIN<43>" : input; "DIN<44>" : input; "DIN<45>" : input; "DIN<46>" : input; "DIN<47>" : input; "DIN<48>" : input; "DIN<49>" : input; "DIN<50>" : input; "DIN<51>" : input; "DIN<52>" : input; "DIN<53>" : input; "DIN<54>" : input; "DIN<55>" : input; "DIN<56>" : input; "DIN<57>" : input; "DIN<58>" : input; "DIN<59>" : input; "DIN<60>" : input; "DIN<61>" : input; "DIN<62>" : input; "DIN<63>" : input; "DIN<64>" : input; "DIN<65>" : input; "ENABLE" : input; # -TI "ENABLE_PI" : input; # -SG "HOLD" : input; # -TI "HOLD_PI" : input; # -SG "RW0" : input; "RW1" : input; "SCAN0" : input; # -TI "SCAN0_PI" : input; # +SG "SDI0" : input; # SI "SDI1" : input; # SI "SEL" : input; "DOUT<0>" : output; "DOUT<1>" : output; "DOUT<2>" : output; "DOUT<3>" : output; "DOUT<4>" : output; "DOUT<5>" : output; "DOUT<6>" : output; "DOUT<7>" : output; "DOUT<8>" : output; "DOUT<9>" : output; "DOUT<10>" : output; "DOUT<11>" : output; "DOUT<12>" : output; "DOUT<13>" : output; "DOUT<14>" : output; "DOUT<15>" : output; "DOUT<16>" : output; "DOUT<17>" : output; "DOUT<18>" : output; "DOUT<19>" : output; "DOUT<20>" : output; "DOUT<21>" : output; "DOUT<22>" : output; "DOUT<23>" : output; "DOUT<24>" : output; "DOUT<25>" : output; "DOUT<26>" : output; "DOUT<27>" : output; "DOUT<28>" : output; "DOUT<29>" : output; "DOUT<30>" : output; "DOUT<31>" : output; "DOUT<32>" : output; "DOUT<33>" : output; "DOUT<34>" : output; "DOUT<35>" : output; "DOUT<36>" : output; "DOUT<37>" : output; "DOUT<38>" : output; "DOUT<39>" : output; "DOUT<40>" : output; "DOUT<41>" : output; "DOUT<42>" : output; "DOUT<43>" : output; "DOUT<44>" : output; "DOUT<45>" : output; "DOUT<46>" : output; "DOUT<47>" : output; "DOUT<48>" : output; "DOUT<49>" : output; "DOUT<50>" : output; "DOUT<51>" : output; "DOUT<52>" : output; "DOUT<53>" : output; "DOUT<54>" : output; "DOUT<55>" : output; "DOUT<56>" : output; "DOUT<57>" : output; "DOUT<58>" : output; "DOUT<59>" : output; "DOUT<60>" : output; "DOUT<61>" : output; "DOUT<62>" : output; "DOUT<63>" : output; "DOUT<64>" : output; "DOUT<65>" : output; "SDO0" : output; # SO "SDO1" : output; # SO end scancell "d0_out.R0"; "d10_out.R0"; "d11_out.R0"; "d12_out.R0"; "d13_out.R0"; "d14_out.R0"; "d15_out.R0"; "d16_out.R0"; "d17_out.R0"; "d18_out.R0"; "d19_out.R0"; "d1_out.R0"; "d20_out.R0"; "d21_out.R0"; "d22_out.R0"; "d23_out.R0"; "d24_out.R0"; "d25_out.R0"; "d26_out.R0"; "d27_out.R0"; "d28_out.R0"; "d29_out.R0"; "d2_out.R0"; "d30_out.R0"; "d31_out.R0"; "d32_out.R0"; "d33_out.R0"; "d34_out.R0"; "d35_out.R0"; "d36_out.R0"; "d37_out.R0"; "d38_out.R0"; "d39_out.R0"; "d3_out.R0"; "d40_out.R0"; "d41_out.R0"; "d42_out.R0"; "d43_out.R0"; "d44_out.R0"; "d45_out.R0"; "d46_out.R0"; "d47_out.R0"; "d48_out.R0"; "d49_out.R0"; "d4_out.R0"; "d50_out.R0"; "d51_out.R0"; "d52_out.R0"; "d53_out.R0"; "d54_out.R0"; "d55_out.R0"; "d56_out.R0"; "d57_out.R0"; "d58_out.R0"; "d59_out.R0"; "d5_out.R0"; "d60_out.R0"; "d61_out.R0"; "d62_out.R0"; "d63_out.R0"; "d64_out.R0"; "d65_out.R0"; "d6_out.R0"; "d7_out.R0"; "d8_out.R0"; "d9_out.R0"; "onoff_lat.R0"; "oob_lat.R0"; "ra0_lat.R0"; "ra1_lat.R0"; "ra2_lat.R0"; "ra3_lat.R0"; "ra4_lat.R0"; "ra5_lat.R0"; "rdum0_lat.R0"; "rdum1_lat.R0"; "rdum2_lat.R0"; "rdum3_lat.R0"; "rdum4_lat.R0"; "rrw_lat.R0"; "time0_lat.R0"; "time1_lat.R0"; "wa0_lat.R0"; "wa1_lat.R0"; "wa2_lat.R0"; "wa3_lat.R0"; "wa4_lat.R0"; "wa5_lat.R0"; "wd0_lat.R0"; "wd10_lat.R0"; "wd11_lat.R0"; "wd12_lat.R0"; "wd13_lat.R0"; "wd14_lat.R0"; "wd15_lat.R0"; "wd16_lat.R0"; "wd17_lat.R0"; "wd18_lat.R0"; "wd19_lat.R0"; "wd1_lat.R0"; "wd20_lat.R0"; "wd21_lat.R0"; "wd22_lat.R0"; "wd23_lat.R0"; "wd24_lat.R0"; "wd25_lat.R0"; "wd26_lat.R0"; "wd27_lat.R0"; "wd28_lat.R0"; "wd29_lat.R0"; "wd2_lat.R0"; "wd30_lat.R0"; "wd31_lat.R0"; "wd32_lat.R0"; "wd33_lat.R0"; "wd34_lat.R0"; "wd35_lat.R0"; "wd36_lat.R0"; "wd37_lat.R0"; "wd38_lat.R0"; "wd39_lat.R0"; "wd3_lat.R0"; "wd40_lat.R0"; "wd41_lat.R0"; "wd42_lat.R0"; "wd43_lat.R0"; "wd44_lat.R0"; "wd45_lat.R0"; "wd46_lat.R0"; "wd47_lat.R0"; "wd48_lat.R0"; "wd49_lat.R0"; "wd4_lat.R0"; "wd50_lat.R0"; "wd51_lat.R0"; "wd52_lat.R0"; "wd53_lat.R0"; "wd54_lat.R0"; "wd55_lat.R0"; "wd56_lat.R0"; "wd57_lat.R0"; "wd58_lat.R0"; "wd59_lat.R0"; "wd5_lat.R0"; "wd60_lat.R0"; "wd61_lat.R0"; "wd62_lat.R0"; "wd63_lat.R0"; "wd64_lat.R0"; "wd65_lat.R0"; "wd6_lat.R0"; "wd7_lat.R0"; "wd8_lat.R0"; "wd9_lat.R0"; "wdum0_lat.R0"; "wdum1_lat.R0"; "wdum2_lat.R0"; "wdum3_lat.R0"; "wdum4_lat.R0"; "wrw_lat.R0"; end scanchain "MREG_1_gsd_static_negclk" [ "SDI0", "rrw_lat.R0", "wrw_lat.R0", "rdum0_lat.R0", "rdum1_lat.R0", "rdum2_lat.R0", "ra0_lat.R0", "ra1_lat.R0", "ra2_lat.R0", "ra3_lat.R0", "ra4_lat.R0", "rdum3_lat.R0", "rdum4_lat.R0", "ra5_lat.R0", "wdum0_lat.R0", "wdum1_lat.R0", "wdum2_lat.R0", "wa0_lat.R0", "wa1_lat.R0", "wa2_lat.R0", "wa3_lat.R0", "wa4_lat.R0", "wdum3_lat.R0", "wdum4_lat.R0", "wa5_lat.R0", "wd0_lat.R0", "wd1_lat.R0", "wd2_lat.R0", "wd3_lat.R0", "wd4_lat.R0", "wd5_lat.R0", "wd6_lat.R0", "wd7_lat.R0", "wd8_lat.R0", "wd9_lat.R0", "wd10_lat.R0", "wd11_lat.R0", "wd12_lat.R0", "wd13_lat.R0", "wd14_lat.R0", "wd15_lat.R0", "wd16_lat.R0", "wd17_lat.R0", "wd18_lat.R0", "wd19_lat.R0", "wd20_lat.R0", "wd21_lat.R0", "wd22_lat.R0", "wd23_lat.R0", "wd24_lat.R0", "wd25_lat.R0", "wd26_lat.R0", "wd27_lat.R0", "wd28_lat.R0", "wd29_lat.R0", "wd30_lat.R0", "wd31_lat.R0", "wd32_lat.R0", "wd33_lat.R0", "wd34_lat.R0", "wd35_lat.R0", "wd36_lat.R0", "wd37_lat.R0", "wd38_lat.R0", "wd39_lat.R0", "wd40_lat.R0", "wd41_lat.R0", "wd42_lat.R0", "wd43_lat.R0", "wd44_lat.R0", "wd45_lat.R0", "wd46_lat.R0", "wd47_lat.R0", "wd48_lat.R0", "wd49_lat.R0", "wd50_lat.R0", "wd51_lat.R0", "wd52_lat.R0", "wd53_lat.R0", "wd54_lat.R0", "wd55_lat.R0", "wd56_lat.R0", "wd57_lat.R0", "wd58_lat.R0", "wd59_lat.R0", "wd60_lat.R0", "wd61_lat.R0", "wd62_lat.R0", "wd63_lat.R0", "wd64_lat.R0", "wd65_lat.R0", "SDO0" ]; "MREG_2_gsd_static_negclk" [ "SDI1", "onoff_lat.R0", "time0_lat.R0", "time1_lat.R0", "d0_out.R0", "d1_out.R0", "d2_out.R0", "d3_out.R0", "d4_out.R0", "d5_out.R0", "d6_out.R0", "d7_out.R0", "d8_out.R0", "d9_out.R0", "d10_out.R0", "d11_out.R0", "d12_out.R0", "d13_out.R0", "d14_out.R0", "d15_out.R0", "d16_out.R0", "d17_out.R0", "d18_out.R0", "d19_out.R0", "d20_out.R0", "d21_out.R0", "d22_out.R0", "d23_out.R0", "d24_out.R0", "d25_out.R0", "d26_out.R0", "d27_out.R0", "d28_out.R0", "d29_out.R0", "d30_out.R0", "d31_out.R0", "d32_out.R0", "d33_out.R0", "d34_out.R0", "d35_out.R0", "d36_out.R0", "d37_out.R0", "d38_out.R0", "d39_out.R0", "d40_out.R0", "d41_out.R0", "d42_out.R0", "d43_out.R0", "d44_out.R0", "d45_out.R0", "d46_out.R0", "d47_out.R0", "d48_out.R0", "d49_out.R0", "d50_out.R0", "d51_out.R0", "d52_out.R0", "d53_out.R0", "d54_out.R0", "d55_out.R0", "d56_out.R0", "d57_out.R0", "d58_out.R0", "d59_out.R0", "d60_out.R0", "d61_out.R0", "d62_out.R0", "d63_out.R0", "d64_out.R0", "d65_out.R0", "oob_lat.R0", "SDO1" ]; end timeplate "PULSECLK_gsd_static_negclk" period 16 ns "AADR<0>" := input[ 0ns:S ]; "AADR<1>" := input[ 0ns:S ]; "AADR<2>" := input[ 0ns:S ]; "AADR<3>" := input[ 0ns:S ]; "AADR<4>" := input[ 0ns:S ]; "AADR<5>" := input[ 0ns:S ]; "ABIST" := input[ 0ns:S ]; "ABIST_PI" := input[ 0ns:S ]; "BADR<0>" := input[ 0ns:S ]; "BADR<1>" := input[ 0ns:S ]; "BADR<2>" := input[ 0ns:S ]; "BADR<3>" := input[ 0ns:S ]; "BADR<4>" := input[ 0ns:S ]; "BADR<5>" := input[ 0ns:S ]; "CLK" := input[ 0ns:D, 2ns:S, 4ns:D ]; "DIN<0>" := input[ 0ns:S ]; "DIN<1>" := input[ 0ns:S ]; "DIN<2>" := input[ 0ns:S ]; "DIN<3>" := input[ 0ns:S ]; "DIN<4>" := input[ 0ns:S ]; "DIN<5>" := input[ 0ns:S ]; "DIN<6>" := input[ 0ns:S ]; "DIN<7>" := input[ 0ns:S ]; "DIN<8>" := input[ 0ns:S ]; "DIN<9>" := input[ 0ns:S ]; "DIN<10>" := input[ 0ns:S ]; "DIN<11>" := input[ 0ns:S ]; "DIN<12>" := input[ 0ns:S ]; "DIN<13>" := input[ 0ns:S ]; "DIN<14>" := input[ 0ns:S ]; "DIN<15>" := input[ 0ns:S ]; "DIN<16>" := input[ 0ns:S ]; "DIN<17>" := input[ 0ns:S ]; "DIN<18>" := input[ 0ns:S ]; "DIN<19>" := input[ 0ns:S ]; "DIN<20>" := input[ 0ns:S ]; "DIN<21>" := input[ 0ns:S ]; "DIN<22>" := input[ 0ns:S ]; "DIN<23>" := input[ 0ns:S ]; "DIN<24>" := input[ 0ns:S ]; "DIN<25>" := input[ 0ns:S ]; "DIN<26>" := input[ 0ns:S ]; "DIN<27>" := input[ 0ns:S ]; "DIN<28>" := input[ 0ns:S ]; "DIN<29>" := input[ 0ns:S ]; "DIN<30>" := input[ 0ns:S ]; "DIN<31>" := input[ 0ns:S ]; "DIN<32>" := input[ 0ns:S ]; "DIN<33>" := input[ 0ns:S ]; "DIN<34>" := input[ 0ns:S ]; "DIN<35>" := input[ 0ns:S ]; "DIN<36>" := input[ 0ns:S ]; "DIN<37>" := input[ 0ns:S ]; "DIN<38>" := input[ 0ns:S ]; "DIN<39>" := input[ 0ns:S ]; "DIN<40>" := input[ 0ns:S ]; "DIN<41>" := input[ 0ns:S ]; "DIN<42>" := input[ 0ns:S ]; "DIN<43>" := input[ 0ns:S ]; "DIN<44>" := input[ 0ns:S ]; "DIN<45>" := input[ 0ns:S ]; "DIN<46>" := input[ 0ns:S ]; "DIN<47>" := input[ 0ns:S ]; "DIN<48>" := input[ 0ns:S ]; "DIN<49>" := input[ 0ns:S ]; "DIN<50>" := input[ 0ns:S ]; "DIN<51>" := input[ 0ns:S ]; "DIN<52>" := input[ 0ns:S ]; "DIN<53>" := input[ 0ns:S ]; "DIN<54>" := input[ 0ns:S ]; "DIN<55>" := input[ 0ns:S ]; "DIN<56>" := input[ 0ns:S ]; "DIN<57>" := input[ 0ns:S ]; "DIN<58>" := input[ 0ns:S ]; "DIN<59>" := input[ 0ns:S ]; "DIN<60>" := input[ 0ns:S ]; "DIN<61>" := input[ 0ns:S ]; "DIN<62>" := input[ 0ns:S ]; "DIN<63>" := input[ 0ns:S ]; "DIN<64>" := input[ 0ns:S ]; "DIN<65>" := input[ 0ns:S ]; "ENABLE" := input[ 0ns:S ]; "ENABLE_PI" := input[ 0ns:S ]; "HOLD" := input[ 0ns:S ]; "HOLD_PI" := input[ 0ns:S ]; "RW0" := input[ 0ns:S ]; "RW1" := input[ 0ns:S ]; "SCAN0" := input[ 0ns:S ]; "SCAN0_PI" := input[ 0ns:S ]; "SDI0" := input[ 0ns:S ]; "SDI1" := input[ 0ns:S ]; "SEL" := input[ 0ns:S ]; "DOUT<0>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<1>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<2>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<3>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<4>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<5>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<6>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<7>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<8>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<9>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<10>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<11>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<12>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<13>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<14>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<15>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<16>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<17>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<18>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<19>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<20>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<21>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<22>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<23>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<24>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<25>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<26>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<27>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<28>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<29>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<30>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<31>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<32>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<33>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<34>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<35>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<36>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<37>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<38>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<39>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<40>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<41>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<42>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<43>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<44>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<45>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<46>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<47>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<48>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<49>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<50>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<51>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<52>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<53>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<54>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<55>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<56>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<57>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<58>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<59>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<60>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<61>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<62>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<63>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<64>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<65>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO0" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO1" := output[ 0ns:X, 15ns:Q, 16ns:X ]; end timeplate "STIMCLOCK" period 16 ns "AADR<0>" := input[ 0ns:S ]; "AADR<1>" := input[ 0ns:S ]; "AADR<2>" := input[ 0ns:S ]; "AADR<3>" := input[ 0ns:S ]; "AADR<4>" := input[ 0ns:S ]; "AADR<5>" := input[ 0ns:S ]; "ABIST" := input[ 0ns:S ]; "ABIST_PI" := input[ 0ns:S ]; "BADR<0>" := input[ 0ns:S ]; "BADR<1>" := input[ 0ns:S ]; "BADR<2>" := input[ 0ns:S ]; "BADR<3>" := input[ 0ns:S ]; "BADR<4>" := input[ 0ns:S ]; "BADR<5>" := input[ 0ns:S ]; "CLK" := input[ 0ns:S ]; "DIN<0>" := input[ 0ns:S ]; "DIN<1>" := input[ 0ns:S ]; "DIN<2>" := input[ 0ns:S ]; "DIN<3>" := input[ 0ns:S ]; "DIN<4>" := input[ 0ns:S ]; "DIN<5>" := input[ 0ns:S ]; "DIN<6>" := input[ 0ns:S ]; "DIN<7>" := input[ 0ns:S ]; "DIN<8>" := input[ 0ns:S ]; "DIN<9>" := input[ 0ns:S ]; "DIN<10>" := input[ 0ns:S ]; "DIN<11>" := input[ 0ns:S ]; "DIN<12>" := input[ 0ns:S ]; "DIN<13>" := input[ 0ns:S ]; "DIN<14>" := input[ 0ns:S ]; "DIN<15>" := input[ 0ns:S ]; "DIN<16>" := input[ 0ns:S ]; "DIN<17>" := input[ 0ns:S ]; "DIN<18>" := input[ 0ns:S ]; "DIN<19>" := input[ 0ns:S ]; "DIN<20>" := input[ 0ns:S ]; "DIN<21>" := input[ 0ns:S ]; "DIN<22>" := input[ 0ns:S ]; "DIN<23>" := input[ 0ns:S ]; "DIN<24>" := input[ 0ns:S ]; "DIN<25>" := input[ 0ns:S ]; "DIN<26>" := input[ 0ns:S ]; "DIN<27>" := input[ 0ns:S ]; "DIN<28>" := input[ 0ns:S ]; "DIN<29>" := input[ 0ns:S ]; "DIN<30>" := input[ 0ns:S ]; "DIN<31>" := input[ 0ns:S ]; "DIN<32>" := input[ 0ns:S ]; "DIN<33>" := input[ 0ns:S ]; "DIN<34>" := input[ 0ns:S ]; "DIN<35>" := input[ 0ns:S ]; "DIN<36>" := input[ 0ns:S ]; "DIN<37>" := input[ 0ns:S ]; "DIN<38>" := input[ 0ns:S ]; "DIN<39>" := input[ 0ns:S ]; "DIN<40>" := input[ 0ns:S ]; "DIN<41>" := input[ 0ns:S ]; "DIN<42>" := input[ 0ns:S ]; "DIN<43>" := input[ 0ns:S ]; "DIN<44>" := input[ 0ns:S ]; "DIN<45>" := input[ 0ns:S ]; "DIN<46>" := input[ 0ns:S ]; "DIN<47>" := input[ 0ns:S ]; "DIN<48>" := input[ 0ns:S ]; "DIN<49>" := input[ 0ns:S ]; "DIN<50>" := input[ 0ns:S ]; "DIN<51>" := input[ 0ns:S ]; "DIN<52>" := input[ 0ns:S ]; "DIN<53>" := input[ 0ns:S ]; "DIN<54>" := input[ 0ns:S ]; "DIN<55>" := input[ 0ns:S ]; "DIN<56>" := input[ 0ns:S ]; "DIN<57>" := input[ 0ns:S ]; "DIN<58>" := input[ 0ns:S ]; "DIN<59>" := input[ 0ns:S ]; "DIN<60>" := input[ 0ns:S ]; "DIN<61>" := input[ 0ns:S ]; "DIN<62>" := input[ 0ns:S ]; "DIN<63>" := input[ 0ns:S ]; "DIN<64>" := input[ 0ns:S ]; "DIN<65>" := input[ 0ns:S ]; "ENABLE" := input[ 0ns:S ]; "ENABLE_PI" := input[ 0ns:S ]; "HOLD" := input[ 0ns:S ]; "HOLD_PI" := input[ 0ns:S ]; "RW0" := input[ 0ns:S ]; "RW1" := input[ 0ns:S ]; "SCAN0" := input[ 0ns:S ]; "SCAN0_PI" := input[ 0ns:S ]; "SDI0" := input[ 0ns:S ]; "SDI1" := input[ 0ns:S ]; "SEL" := input[ 0ns:S ]; "DOUT<0>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<1>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<2>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<3>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<4>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<5>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<6>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<7>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<8>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<9>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<10>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<11>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<12>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<13>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<14>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<15>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<16>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<17>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<18>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<19>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<20>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<21>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<22>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<23>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<24>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<25>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<26>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<27>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<28>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<29>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<30>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<31>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<32>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<33>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<34>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<35>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<36>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<37>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<38>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<39>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<40>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<41>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<42>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<43>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<44>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<45>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<46>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<47>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<48>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<49>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<50>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<51>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<52>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<53>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<54>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<55>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<56>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<57>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<58>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<59>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<60>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<61>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<62>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<63>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<64>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "DOUT<65>" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO0" := output[ 0ns:X, 15ns:Q, 16ns:X ]; "SDO1" := output[ 0ns:X, 15ns:Q, 16ns:X ]; end #*****************************************************************************# # DEFINE SCAN STATES # #*****************************************************************************# scanstate "SS.1.2.1.2.1.1.1" := "MREG_1_gsd_static_negclk" (101010101110100011010000000000001100111000101100110111111001001110001110001100110110011000) "MREG_2_gsd_static_negclk" (1001000100101000001101011100000000000000000110010111010100110100111000); "SS.1.2.1.2.1.4.1" := "MREG_1_gsd_static_negclk" (X11101010111011010101110100000000110011100010110011011111100100111000111000110011011001100) "MREG_2_gsd_static_negclk" (X100100010010100000110101110000000000000000011001011101010011010011100); "SS.1.2.1.2.2.1.1" := "MREG_1_gsd_static_negclk" (100011100011110100000010110110101100001011100100101011011000111101110111011001111011011001) "MREG_2_gsd_static_negclk" (0000101010110001000110111010111011110010010011010011111011100011101010); "SS.1.2.1.2.2.4.1" := "MREG_1_gsd_static_negclk" (X10001110001111010000001011011010110000101110010010101101100011110111011101100111101101100) "MREG_2_gsd_static_negclk" (X000010101011000100011011101011101111001001001101001111101110001110101); "SS.1.2.1.2.3.1.1" := "MREG_1_gsd_static_negclk" (010110010111010000011011010001101010010101110001000010001001110101011100000111010111100100) "MREG_2_gsd_static_negclk" (1011010011101001111001110100101100111101010111100110110010110101010010); "SS.1.2.1.2.3.4.1" := "MREG_1_gsd_static_negclk" (X10011100011100110010111010100010110110111001111111100010111100011111101110110011100001100) "MREG_2_gsd_static_negclk" (X101101001110100111100111010010110011110101011110011011001011010101001); "SS.1.2.1.2.4.1.1" := "MREG_1_gsd_static_negclk" (010000101111011011111000111110010110011110010100010001000101100001101010110010100110100010) "MREG_2_gsd_static_negclk" (1101011101111111001011001111010111000010111100101100011101011110001010); "SS.1.2.1.2.4.4.1" := "MREG_1_gsd_static_negclk" (X10100001011110110111110001111100101100111100101000100010001011000011010101100101001101000) "MREG_2_gsd_static_negclk" (X110110111011111110010110011110101110000101111001011000111010111100010); "SS.1.2.1.2.5.1.1" := "MREG_1_gsd_static_negclk" (011110001001110110011011001010011001001100110101001100001100111011001010100010000100100100) "MREG_2_gsd_static_negclk" (1011001010100010110101010001100011110100101010101100100101010001110101); "SS.1.2.1.2.5.4.1" := "MREG_1_gsd_static_negclk" (X01111000100111011001101100101001100100110011010100110000110011101100101010001000010010010) "MREG_2_gsd_static_negclk" (X101100101010001011010101000110001111010010101010110010010101000111010); "SS.1.2.1.2.6.1.1" := "MREG_1_gsd_static_negclk" (101100011111100001000001101001110101111100110110101001011010011001001011000010100110100111) "MREG_2_gsd_static_negclk" (0001010010010000000011100101010000001110010000001110001010100010001110); "SS.1.2.1.2.6.4.1" := "MREG_1_gsd_static_negclk" (X11110001111111100011111110100111010111110011011010100101101001100100101100001010011010011) "MREG_2_gsd_static_negclk" (X000101001001000000001110010101000000111001000000111000101010001000111); "SS.1.2.1.2.7.1.1" := "MREG_1_gsd_static_negclk" (011111010100111100011100111110000101001000011001010111000101100110110001111101101111000011) "MREG_2_gsd_static_negclk" (0010000010000000001110010101000100111001000000111000110100010001100100); "SS.1.2.1.2.7.4.1" := "MREG_1_gsd_static_negclk" (X00111101010011111010100111111000010100100001100101011100010110011011000111110110111100001) "MREG_2_gsd_static_negclk" (X001000001000000000111001010100010011100100000011100011010001000110010); "SS.1.2.1.2.8.1.1" := "MREG_1_gsd_static_negclk" (110110011110100111111110100100101110111111000100111111101100111101101111110000100011011111) "MREG_2_gsd_static_negclk" (0101100101000111101011010111100001100111010111101011011111011011011111); "SS.1.2.1.2.8.4.1" := "MREG_1_gsd_static_negclk" (X11011001111010011111111010010010111011111100010011111110110011110110111111000010001101111) "MREG_2_gsd_static_negclk" (X010110010100011110101101011110000110011101011110101101111101101101111); "SS.1.2.1.2.9.1.1" := "MREG_1_gsd_static_negclk" (001001111000011110110010011000110101001001001100000111010000110000001110110000100000010100) "MREG_2_gsd_static_negclk" (0110111000110110001111000000111010001000101000111101000011101100100010); "SS.1.2.1.2.9.4.1" := "MREG_1_gsd_static_negclk" (X10100001010011001111000000010100101011010111110001110010101100101111000000110011000011100) "MREG_2_gsd_static_negclk" (X011011100011011000111100000011101000100010100011110100001110110010001); "SS.1.2.1.2.10.1.1" := "MREG_1_gsd_static_negclk" (000110110110110110111001011100010010100011110100011100010100111011010100000100110000010010) "MREG_2_gsd_static_negclk" (0101000111101001010001110111101000101000010101000100101010111100000110); "SS.1.2.1.2.10.4.1" := "MREG_1_gsd_static_negclk" (X00011000011000110110110110111011100100101010001110001110010001110000111111101101101000010) "MREG_2_gsd_static_negclk" (X010100011110100101000111011110100010100001010100010010101011110000011); "SS.1.2.1.2.11.1.1" := "MREG_1_gsd_static_negclk" (000110101100001110110001000001001010011101100101100110101011010101110110000101001000001111) "MREG_2_gsd_static_negclk" (0101011111011011000101101100101010101001110100010110010010101100100110); "SS.1.2.1.2.11.4.1" := "MREG_1_gsd_static_negclk" (X10011111100010110101100010001011011100100001000011110011111000011000110001000100110111111) "MREG_2_gsd_static_negclk" (X010101111101101100010110110010101010100111010001011001001010110010011); "SS.1.2.1.2.12.1.1" := "MREG_1_gsd_static_negclk" (101100010010011001010000111101001101101110111101000100110100111010100001111000000000110000) "MREG_2_gsd_static_negclk" (0001110011110101111011100000110101111100111111101111000011010101000111); "SS.1.2.1.2.12.4.1" := "MREG_1_gsd_static_negclk" (X01110110101001100010010001000100000011100000011100011100101111100010000011100011011110101) "MREG_2_gsd_static_negclk" (X000111001111010111101110000011010111110011111110111100001101010100011); "SS.1.2.1.3.1.1.1" := "MREG_1_gsd_static_negclk" (011011111001000010001001010001000101111100110010001110110100100011110110011001011010000000) "MREG_2_gsd_static_negclk" (1110011110011111100010001100011010101110101110001000010001101100011101); "SS.1.2.1.3.1.3.1" := "MREG_1_gsd_static_negclk" (X01101111100100001000100101000100010111110011001000111011010010001111011001100101101000000) "MREG_2_gsd_static_negclk" (X111001111001111110001000110001101010111010111000100001000110110001110); "SS.1.2.1.4.1.1.1" := "MREG_1_gsd_static_negclk" (000111110011101011100110000000000000101101100000111111011110000010110110000011011010111111) "MREG_2_gsd_static_negclk" (1010111100111011110010100100101011001100000111001001000110110010010110); "SS.1.2.1.4.1.4.1" := "MREG_1_gsd_static_negclk" (101101000110100001110010000000010000000001011001011100100000000100000101010101110001000000) "MREG_2_gsd_static_negclk" (0100100010101100100011101011001110100110101010001111010110011100100110); "SS.1.2.1.4.1.7.1" := "MREG_1_gsd_static_negclk" (X11110100011011101000110100000001000000000101100101110010000000010000010101010111000100000) "MREG_2_gsd_static_negclk" (X010010001010110010001110101100111010011010101000111101011001110010011); "SS.1.2.1.5.1.1.1" := "MREG_1_gsd_static_negclk" (111000010110000100010000001110100000000001000000011000100100100100110101011000111001010100) "MREG_2_gsd_static_negclk" (0110000000100100000010110010111001000000001000001010101011100010000000); "SS.1.2.1.5.1.4.1" := "MREG_1_gsd_static_negclk" (X11100001011001000010110000111010000000000100000001100010010010010011010101100011100101010) "MREG_2_gsd_static_negclk" (X011000000010010000001011001011100100000000100000101010101110001000000); "SS.1.2.1.5.2.1.1" := "MREG_1_gsd_static_negclk" (010111101010001000010000100101111011001000101011001110110001001100100010011100111001000100) "MREG_2_gsd_static_negclk" (0110011010000110111101000000101011101110001011010010100010110101110101); "SS.1.2.1.5.2.4.1" := "MREG_1_gsd_static_negclk" (X01011110101000100001000010010111101100100010101100111011000100110010001001110011100100010) "MREG_2_gsd_static_negclk" (X011001101000011011110100000010101110111000101101001010001011010111010); "SS.1.2.1.5.3.1.1" := "MREG_1_gsd_static_negclk" (000010000001000010111011100100000011110011101010000110000000101000101010111000000000110110) "MREG_2_gsd_static_negclk" (1100001100101111111010111111001111111000110110100111110010111010110010); "SS.1.2.1.5.3.4.1" := "MREG_1_gsd_static_negclk" (X00001000000100010000001010010000001111001110101000011000000010100010101011100000000011011) "MREG_2_gsd_static_negclk" (X110000110010111111101011111100111111100011011010011111001011101011001); "SS.1.2.1.5.4.1.1" := "MREG_1_gsd_static_negclk" (000000110111010000000001001111001010000110000100001100000001000000001100011001011011001100) "MREG_2_gsd_static_negclk" (0110000010100100001101000110110000100011001000110100011011000000001100); "SS.1.2.1.5.4.4.1" := "MREG_1_gsd_static_negclk" (X00000011011100000110111000111100101000011000010000110000000100000000110001100101101100110) "MREG_2_gsd_static_negclk" (X011000001010010000110100011011000010001100100011010001101100000000110); "SS.1.2.1.5.5.1.1" := "MREG_1_gsd_static_negclk" (000111111101101011000000100111011111010101101100011110110111000110101011001001111001011100) "MREG_2_gsd_static_negclk" (1001001111011111011010001001100111010010001111110010011010011001101010); "SS.1.2.1.5.5.4.1" := "MREG_1_gsd_static_negclk" (X00011111110110111111101110011101111101010110110001111011011100011010101100100111100101110) "MREG_2_gsd_static_negclk" (X100100111101111101101000100110011101001000111111001001101001100110101); "SS.1.2.1.5.6.1.1" := "MREG_1_gsd_static_negclk" (110110011101110111111001000111000000000010111101011110000100001100010001100111011111001110) "MREG_2_gsd_static_negclk" (0000000000101111000011100011110100110100101010001111111110100001001001); "SS.1.2.1.5.6.4.1" := "MREG_1_gsd_static_negclk" (X11011000000100110011101100110111001111011000001010011000001111001001111011000000101001010) "MREG_2_gsd_static_negclk" (X000000000010111100001110001111010011010010101000111111111010000100100); "SS.1.2.1.5.7.1.1" := "MREG_1_gsd_static_negclk" (110110011010010100110101000100111100110010000011000110101001011111011011011111111011100101) "MREG_2_gsd_static_negclk" (0111010000100111001111010110110110100100001100000100110110011010011000); "SS.1.2.1.5.7.4.1" := "MREG_1_gsd_static_negclk" (X01101100110100101001101010001001111001100100000110001101010010111110110110111111110111001) "MREG_2_gsd_static_negclk" (X011010100001001110011110101101101101001000011000001001101100110100110); "SS.1.2.1.5.8.1.1" := "MREG_1_gsd_static_negclk" (011100101011000010000100100111100011011101001010010001011000000101010000010101001000000001) "MREG_2_gsd_static_negclk" (1100100111010100110111001110100110101101000010101100000000010110110110); "SS.1.2.1.5.8.4.1" := "MREG_1_gsd_static_negclk" (X00110010101101100101011010011110001101110100101001000101100000010101000001010100100000000) "MREG_2_gsd_static_negclk" (X110010011101010011011100111010011010110100001010110000000001011011011); "SS.1.2.1.5.9.1.1" := "MREG_1_gsd_static_negclk" (100000100011011110001001100101000101000000001011100000001111001110100001111100001000010000) "MREG_2_gsd_static_negclk" (0100101110000110111010000111100011111101000000111000111110010001101001); "SS.1.2.1.5.9.4.1" := "MREG_1_gsd_static_negclk" (X11000010001110000100011001010111000001110110000000011001000111000100110111000000011101000) "MREG_2_gsd_static_negclk" (X010010111000011011101000011110001111110100000011100011111001000110100); "SS.1.2.1.5.10.1.1" := "MREG_1_gsd_static_negclk" (111111111011100000011000110110110111001011100010111001111011011011110111101011001001010110) "MREG_2_gsd_static_negclk" (1110110101100101010010110000011100000001001001111111111001010011000011); "SS.1.2.1.5.10.4.1" := "MREG_1_gsd_static_negclk" (X11111111101111111111011111011011011100101110001011100111101101101111011110101100100101011) "MREG_2_gsd_static_negclk" (X111011010110010101001011000001110000000100100111111111100101001100001); "SS.1.2.1.5.11.1.1" := "MREG_1_gsd_static_negclk" (011000110010001010101000111001000001010110101010100101100111000110100000100110011101100001) "MREG_2_gsd_static_negclk" (1100011000011111111011011101100011011011111011000101000011110111101111); "SS.1.2.1.5.11.4.1" := "MREG_1_gsd_static_negclk" (X01100011001000101010100011100100000101011010101010010110011100011010000010011001110110000) "MREG_2_gsd_static_negclk" (X110001100001111111101101110110001101101111101100010100001111011110111); "SS.1.2.1.5.12.1.1" := "MREG_1_gsd_static_negclk" (110001101110011000000010000011111011101110111010110011000110001000001110111010111010111101) "MREG_2_gsd_static_negclk" (0001111010011010100101010011101100110101110010010101101110110101010110); "SS.1.2.1.5.12.4.1" := "MREG_1_gsd_static_negclk" (X11000111101000001101110001000101011010101000010110110100100011111101111010101000000111001) "MREG_2_gsd_static_negclk" (X000111101001101010010101001110110011010111001001010110111011010101011); end #*****************************************************************************# # TEST VECTORS # #*****************************************************************************# pattern MAIN ( ALLINPUT, ALLOUTPUT ) vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; #*****************************************************************************# # TESTER LOOP...............1 PROCEDURES HAVE MEMORY....no # # TEST PROCEDURE............1 TYPE......................init # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # TEST SEQUENCE.............1 TYPE......................init # #*****************************************************************************# # processed EVENT: 1.2.1.1.1.1.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.2.1 vector ( +, "STIMCLOCK" ) := [ XXXXXX0XXXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.4.1 vector ( +, "STIMCLOCK" ) := [ XXXXXX0XXXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.1.1.5.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX0XXXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0X0XXX0XXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; #*****************************************************************************# # TEST PROCEDURE............2 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............2507 PERCENT STATIC FAULTS.....87.084335 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.1.1.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX00XXXXXX0XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000XX01XXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ XXXXXX00XXXXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX0000XX01--X XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX], input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.1.1.1" ]; # processed EVENT: 1.2.1.2.1.2.1 # processed EVENT: 1.2.1.2.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100101011111010110010011010010010000000000110110100000111110001000100000000000100001000111 10001001010000011010111000000000000000001100101110101001101001110000]; # processed EVENT: 1.2.1.2.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100101011111110110010011010010010000000000110110100000111110001000100000000000100001000111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111010110010011010010010000000000110110100000111110001000100000000000100001001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111010110010011010010010000000000110110100000111110001000100000000000100001001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00100100011111110110010011010010010000000000110110100000111110001000100000000000100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.1.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.1.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............2 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.2.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.2.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.2.1.1" ]; # processed EVENT: 1.2.1.2.2.2.1 # processed EVENT: 1.2.1.2.2.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110101011111011100110110111010101111010111111010101111000001000100111010001101000011100010 01010101100010001101110101110111100100100110100111110111000111010110]; # processed EVENT: 1.2.1.2.2.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110101011111111100110110111010101111010111111010101111000001000100111010001101000011100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.2.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111011100110110111010101111010111111010101111000001000100111010001101000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111011100110110111010101111010111111010101111000001000100111010001101000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100011111111100110110111010101111010111111010101111000001000100111010001101000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.2.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.2.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............3 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.3.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.3.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.3.1.1" ]; # processed EVENT: 1.2.1.2.3.2.1 # processed EVENT: 1.2.1.2.3.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001000011 10100111010011110011101001011001111010101111001101100101101010100100]; # processed EVENT: 1.2.1.2.3.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111110100010110110111001111111100010111100011111101110110011100001100100001000011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.3.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111010100010110110111001111111100010111100011111101110110011100001100100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000010111110100010110110111001111111100010111100011111101110110011100001100100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.3.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.3.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............4 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.4.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.4.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.4.1.1" ]; # processed EVENT: 1.2.1.2.4.2.1 # processed EVENT: 1.2.1.2.4.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100001110101011010001001011100011010001101011101000100101110001101000110101110000000001100 10111011111110010110011110101110000101111001011000111010111100010100]; # processed EVENT: 1.2.1.2.4.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100001110101111010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.4.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101011010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101011010001001011100011010001101011101000100101110001101000110101110000000001100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100000110101111010001001011100011010001101011101000100101110001101000110101110000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.4.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.4.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............5 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.5.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.5.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.5.1.1" ]; # processed EVENT: 1.2.1.2.5.2.1 # processed EVENT: 1.2.1.2.5.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001001101000010001110010000000111000101010001000111001000000011100010101000100000011100100 10010101000101101010100011000111101001010101011001001010100011101001]; # processed EVENT: 1.2.1.2.5.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001001101000110001110010000000111000101010001000111001000000011100010101000100000011100100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.5.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000010001110010000000111000101010001000111001000000011100010101000100000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000010001110010000000111000101010001000111001000000011100010101000100000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001000101000110001110010000000111000101010001000111001000000011100010101000100000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.5.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.5.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............6 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.6.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.6.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.6.1.1" ]; # processed EVENT: 1.2.1.2.6.2.1 # processed EVENT: 1.2.1.2.6.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010001011100010000000000000000001011000000000001001000100000000000010000001001000001000010 10100100100000000111001010100000011100100000011100010101000100011110]; # processed EVENT: 1.2.1.2.6.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010001011100110000000000000000001011000000000001001000100000000000010000001001000001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.6.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100010000000000000000001011000000000001001000100000000000010000001001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100010000000000000000001011000000000001001000100000000000010000001001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX10]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000011100110000000000000000001011000000000001001000100000000000010000001001000001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.6.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.6.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............7 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.7.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.7.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.7.1.1" ]; # processed EVENT: 1.2.1.2.7.2.1 # processed EVENT: 1.2.1.2.7.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100001100100011100000110000010000110001000000000100001010100100110000010001111100001000110 00000100000000011100101010001001110010000001110001101000100011001010]; # processed EVENT: 1.2.1.2.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100001100100111100000110000010000110001000000000100001010100100110000010001111100001000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.7.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100011100000110000010000110001000000000100001010100100110000010001111100001001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100011100000110000010000110001000000000100001010100100110000010001111100001001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11100000100100111100000110000010000110001000000000100001010100100110000010001111100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.7.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.7.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............8 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.8.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.8.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.8.1.1" ]; # processed EVENT: 1.2.1.2.8.2.1 # processed EVENT: 1.2.1.2.8.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011001111110000010011111101101111101101111100000000010110001111010000011101100000011000001 11001010001111010110101111000011001110101111010110111110110110111111]; # processed EVENT: 1.2.1.2.8.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011001111110100010011111101101111101101111100000000010110001111010000011101100000011000001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.8.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110000010011111101101111101101111100000000010110001111010000011101100000001001001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110000010011111101101111101101111100000000010110001111010000011101100000001001001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011000111110100010011111101101111101101111100000000010110001111010000011101100000001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.8.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.8.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............9 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.9.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.9.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.9.1.1" ]; # processed EVENT: 1.2.1.2.9.2.1 # processed EVENT: 1.2.1.2.9.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001000000 01110001101100011110000001110100010001010001111010000111011001000100]; # processed EVENT: 1.2.1.2.9.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011100010100101011010111110001110010101100101111000000110011000011100100001000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.9.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011000010100101011010111110001110010101100101111000000110011000011100100001001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00010000001011100010100101011010111110001110010101100101111000000110011000011100100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.9.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.9.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............10 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.10.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.10.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.10.1.1" ]; # processed EVENT: 1.2.1.2.10.2.1 # processed EVENT: 1.2.1.2.10.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001100111 10001111010010100011101111010001010000101010001001010101111000001100]; # processed EVENT: 1.2.1.2.10.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101110111011100100101010001110001110010001110000111111101101101000010000001100111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.10.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001101111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101010111011100100101010001110001110010001110000111111101101101000010000001101111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001000010101110111011100100101010001110001110010001110000111111101101101000010000001101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.10.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.10.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............11 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.11.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.11.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.11.1.1" ]; # processed EVENT: 1.2.1.2.11.2.1 # processed EVENT: 1.2.1.2.11.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000100011 10111110110110001011011001010101010011101000101100100101011001001110]; # processed EVENT: 1.2.1.2.11.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000110001011011100100001000011110011111000011000110001000100110111111000000100011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.11.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000101011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000010001011011100100001000011110011111000011000110001000100110111111000000101011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110100010000110001011011100100001000011110011111000011000110001000100110111111000000101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.11.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.11.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............12 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.2.12.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.12.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.12.1.1" ]; # processed EVENT: 1.2.1.2.12.2.1 # processed EVENT: 1.2.1.2.12.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001100010 11100111101011110111000001101011111001111111011110000110101010001101]; # processed EVENT: 1.2.1.2.12.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100101000100000011100000011100011100101111100010000011100011011110101100001100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.2.12.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100001000100000011100000011100011100101111100010000011100011011110101100001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10110100110100101000100000011100000011100011100101111100010000011100011011110101100001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.2.12.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.2.12.4.1" ], #*****************************************************************************# # TEST PROCEDURE............3 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............1 PERCENT STATIC FAULTS.....87.096382 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.3.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.3.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.3.1.1.1" ]; # processed EVENT: 1.2.1.3.1.2.1 # processed EVENT: 1.2.1.3.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011101100100010100111010011010110011111000100010100101101011111010000111010010000010100010 00111100111111000100011000110101011101011100010000100011011000111001]; # processed EVENT: 1.2.1.3.1.3.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100010100111010011010110011111000100010100101101011111010000111010010000000101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100010100111010011010110011111000100010100101101011111010000111010010000000101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11011100100100110100111010011010110011111000100010100101101011111010000111010010000000101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.3.1.3.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.3.1.3.1" ], #*****************************************************************************# # TEST PROCEDURE............4 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............28 PERCENT STATIC FAULTS.....87.433739 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.4.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.1.1" ]; # processed EVENT: 1.2.1.4.1.2.1 # processed EVENT: 1.2.1.4.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011101110110001001110010001100001001000101100010011010100100011110101100111001000010100101 01111001110111100101001001010110011000001110010010001101100100101110]; # processed EVENT: 1.2.1.4.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011101110110101001110010001100001001000101100010011010100100011110101100111001000010100101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.4.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011100110110001001110010001100001001000101100010011010100100011110101100111001000000101101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00011100110110101001110010001100001001000101100010011010100100011110101100111001000000101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX], input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.4.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.4.1" ]; # processed EVENT: 1.2.1.4.1.5.1 # processed EVENT: 1.2.1.4.1.5.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100101011100001000000001000000101010010111000100000000100000010101001011100010000000000000 01000101011001000111010110011101001101010100011110101100111001001100]; # processed EVENT: 1.2.1.4.1.6.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100101011100101000000001000000101010010111000100000000100000010101001011100010000000000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.4.1.7.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100001000000001000000101010010111000100000000100000010101001011100010000000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100001000000001000000101010010111000100000000100000010101001011100010000000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10100100011100101000000001000000101010010111000100000000100000010101001011100010000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.4.1.7.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.4.1.7.1" ], #*****************************************************************************# # TEST PROCEDURE............5 TYPE......................normal # # SLOW TO TURN OFF..........false SEQUENCES HAVE MEMORY.....no # # STATIC FAULTS.............164 PERCENT STATIC FAULTS.....89.409637 # # TEST SEQUENCE.............1 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.1.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.1.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.1.1.1" ]; # processed EVENT: 1.2.1.5.1.2.1 # processed EVENT: 1.2.1.5.1.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011001101011010001101011011111000111101111101000110110101011010000000101011111000001100100 00000001001000000101100101110010000000010000010101010111000100000000]; # processed EVENT: 1.2.1.5.1.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011001101011110001101011011111000111101111101000110110101011010000000101011111000001100100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.1.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011010001101011011111000111101111101000110110101011010000000101011111000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011010001101011011111000111101111101000110110101011010000000101011111000001101100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10011000101011110001101011011111000111101111101000110110101011010000000101011111000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.1.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.1.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............2 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.2.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.2.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.2.1.1" ]; # processed EVENT: 1.2.1.5.2.2.1 # processed EVENT: 1.2.1.5.2.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101101001110001100010011100100010010110001111100000111111011100001100000111000100010001000 00110100001101111010000001010111011100010110100101000101101011101001]; # processed EVENT: 1.2.1.5.2.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101101001110101100010011100100010010110001111100000111111011100001100000111000100010001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.2.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110001100010011100100010010110001111100000111111011100001100000111000100000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110001100010011100100010010110001111100000111111011100001100000111000100000001000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00101100001110101100010011100100010010110001111100000111111011100001100000111000100000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.2.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.2.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............3 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.3.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.3.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.3.1.1" ]; # processed EVENT: 1.2.1.5.3.2.1 # processed EVENT: 1.2.1.5.3.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001101001000001101100001101100000100111011010110000111101010100111011111000001000000000110 00011001011111110101111110011111110001101101001111100101110101100100]; # processed EVENT: 1.2.1.5.3.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001101001000101101100001101100000100111011010110000111101010100111011111000001000000000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.3.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000001101100001101100000100111011010110000111101010100111011111000001000000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000001101100001101100000100111011010110000111101010100111011111000001000000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10001100001000101101100001101100000100111011010110000111101010100111011111000001000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.3.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.3.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............4 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.4.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.4.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.4.1.1" ]; # processed EVENT: 1.2.1.5.4.2.1 # processed EVENT: 1.2.1.5.4.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110001000111011110110100100100111110111101000011111110110101010011001101111001000000000111 00000101001000011010001101100001000110010001101000110110000000011000]; # processed EVENT: 1.2.1.5.4.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110001000111111110110100100100111110111101000011111110110101010011001101111001000000000111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.4.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111011110110100100100111110111101000011111110110101010011001101111001000000001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111011110110100100100111110111101000011111110110101010011001101111001000000001111 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11110000000111111110110100100100111110111101000011111110110101010011001101111001000000001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.4.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.4.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............5 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.5.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.5.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.5.1.1" ]; # processed EVENT: 1.2.1.5.5.2.1 # processed EVENT: 1.2.1.5.5.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101001100011110011011100011101011011001100111100110111000111010101100110011100001000011 10011110111110110100010011001110100100011111100100110100110011010100]; # processed EVENT: 1.2.1.5.5.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101001100111110011011100011101011011001100111100110111000111010101100110011100001000011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.5.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100011110011011100011101011011001100111100110111000111010101100110011100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100011110011011100011101011011001100111100110111000111010101100110011100001001011 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100001100111110011011100011101011011001100111100110111000111010101100110011100001001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.5.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.5.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............6 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.6.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.6.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.6.1.1" ]; # processed EVENT: 1.2.1.5.6.2.1 # processed EVENT: 1.2.1.5.6.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000000010 00000001011110000111000111101001101001010100011111111101000010010001]; # processed EVENT: 1.2.1.5.6.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000100110111001111011000001010011000001111001001111011000000101001010000000000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.6.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000000110111001111011000001010011000001111001001111011000000101001010000000001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11101000000000100110111001111011000001010011000001111001001111011000000101001010000000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.6.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.6.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............7 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.7.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.7.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.7.1.1" ]; # processed EVENT: 1.2.1.5.7.2.1 # processed EVENT: 1.2.1.5.7.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110010011111111000011111100011100001011111111100001111110001110000101000001101001 10100001001110011110101101101101001000011000001001101100110100110010]; # processed EVENT: 1.2.1.5.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110110011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.7.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110010011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110010011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101100111110110011111111000011111100011100001011111111100001111110001110000101000001101--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.7.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.7.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............8 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.8.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.8.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.8.1.1" ]; # processed EVENT: 1.2.1.5.8.2.1 # processed EVENT: 1.2.1.5.8.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111101100000001110111011111101101111011111101111111110100101010111111101111111100000000110 01001110101001101110011101001101011010000101011000000000101101101110]; # processed EVENT: 1.2.1.5.8.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111101100000101110111011111101101111011111101111111110100101010111111101111111100000000110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.8.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000001110111011111101101111011111101111111110100101010111111101111111100000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000001110111011111101101111011111101111111110100101010111111101111111100000001110 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 01111100100000101110111011111101101111011111101111111110100101010111111101111111100000001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.8.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.8.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............9 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.9.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.9.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.9.1.1" ]; # processed EVENT: 1.2.1.5.9.2.1 # processed EVENT: 1.2.1.5.9.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000000101 01011100001101110100001111000111111010000001110001111100100011010001]; # processed EVENT: 1.2.1.5.9.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011101010111000001110110000000011001000111000100110111000000011101000000000000101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.9.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000001101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011001010111000001110110000000011001000111000100110111000000011101000000000001101 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 01000100101011101010111000001110110000000011001000111000100110111000000011101000000000001--1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.9.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.9.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............10 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.10.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.10.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.10.1.1" ]; # processed EVENT: 1.2.1.5.10.2.1 # processed EVENT: 1.2.1.5.10.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001101000001000111111110010100011010101110001000010111001100110011101100011110100001000010 01101011001010100101100000111000000010010011111111110010100110000101]; # processed EVENT: 1.2.1.5.10.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001101000001100111111110010100011010101110001000010111001100110011101100011110100001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.10.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001000111111110010100011010101110001000010111001100110011101100011110100001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001000111111110010100011010101110001000010111001100110011101100011110100001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100000001100111111110010100011010101110001000010111001100110011101100011110100001001--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.10.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.10.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............11 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.11.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.11.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.11.1.1" ]; # processed EVENT: 1.2.1.5.11.2.1 # processed EVENT: 1.2.1.5.11.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111101011000011111111000010000011111110110001111110101100000110111011101100100000011100010 00110000111111110110111011000110110111110110001010000111101111011111]; # processed EVENT: 1.2.1.5.11.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111101011000111111111000010000011111110110001111110101100000110111011101100100000011100010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.11.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000011111111000010000011111110110001111110101100000110111011101100100000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000011111111000010000011111110110001111110101100000110111011101100100000001101010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX11]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 11111100011000111111111000010000011111110110001111110101100000110111011101100100000001101--0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.11.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.11.4.1" ], #*****************************************************************************# # TEST SEQUENCE.............12 TYPE......................normal # #*****************************************************************************# # processed EVENT: 1.2.1.5.12.1.1 input [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.12.1.1" ], input [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.12.1.1" ]; # processed EVENT: 1.2.1.5.12.2.1 # processed EVENT: 1.2.1.5.12.2.2 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001000010 11110100110101001010100111011001101011100100101011011101101010101110]; # processed EVENT: 1.2.1.5.12.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100101000101011010101000010110110100100011111101111010101000000111001000001000010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.12.4.1 # inserted SEQUENCE_DEFINITION SCANPRE vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # inserted POMeasureBeforeScanOut vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100001000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX01]; scan ( +, "PULSECLK_gsd_static_negclk" ) := [ 00001100111100101000101011010101000010110110100100011111101111010101000000111001000001001010 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--], output [ "MREG_1_gsd_static_negclk" : "SS.1.2.1.5.12.4.1" ], output [ "MREG_2_gsd_static_negclk" : "SS.1.2.1.5.12.4.1" ]; end end 2.1.5.7.3.1 vector ( +, "PULSECLK_gsd_static_negclk" ) := [ 10101101111110110011111111000011111100011100001011111111100001111110001110000101000001101001 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX]; # processed EVENT: 1.2.1.5.7.4.1 # inserted SEQUENCINTERFACES/VHDL/VCDVHDL/000075500001440000012000000000001103104161000151435ustar00jcosleystaff00000400000023INTERFACES/VHDL/VCDVHDL/exp3.vtran000064400001440000012000000151301103104161000170760ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > VHDL TEST BENCH # # Original File: "exp3.vcd" # # Target File: "exp3.vhd " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN ORIG_FILE = "../../DATA/exp3.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS { memory interface input-only pads } p_mrdy_, { MRDY* pin } p_mintr_, { MINTR* pin } { LXT901 interface input-only pads } p_tclk, { TCLK pin } p_rxd[3:0], { RXD pins } p_rclk, { RCLK pins } p_crs, { CRS pin } p_rx_dv, { RX_DV pin } p_rx_er, { RX_ER pin } p_col, { COL pin } { PCI bus input-only pads } p_pci_clk, { PCI bus CLK pin } p_rst_, { PCI bus RST* pin } p_gnt_, { GNT* pin } p_idsel, { IDSEL* pin } p_tst_, { TST* pin } { clock input-only pads } p_sysclk; { 50 MHz system clock (SYSCLK) pin } BIDIRECTS { memory interface bidirectional pads } p_mdata[31:0], { MDATA[31:0] pins } { PCI bus bidirectional pads } p_ad[31:0], { A/D pins } p_cbe_[3:0], { C/BE pins } p_par, { PAR pin } p_frame_, { FRAME* pin } p_irdy_, { IRDY* pin } p_trdy_, { TRDY* pin } p_stop_, { STOP* pin } p_devsel_, { DEVSEL* pin } p_perr_, { PERR* pin } p_mdio; { MDIO pin } OUTPUTS { memory interface output-only pads } p_maddr[17:0], { MADDR* pin } p_mcs_[3:0], { MCS* pin } p_ras_, { RAS* pin } p_mrd_, { MRD* pin } p_mwe_[3:0], { MWE* pin } p_mgwe_, { MGWE } p_mclk, { MCLK pin } { LXT901 interface output-only pads } p_txd[3:0], { TXD pins } p_tx_en, { TX_EN pin } p_lbk, { LBK pin } p_mdc, { MDC pin } { PCI bus output-only pads } p_req_, { REQ* pin } p_serr_, { SERR* pin } p_int_, { INT* pin } { clock generator output-only pads } p_clk25, { CLK25 pin } { ERST_ pin } p_erst_, { ERST_ pin } { Debug pin } p_dbg[2:0], { DBG pin } { Enables } mdata_oe, oe_ad, oe_cbe, oe_par, oe_frame, oe_irdy, oe_slave, oe_serr, oe_perr; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } PROC_BLOCK BEGIN { ******* Bi-directional control specifications ******** } { ------------------------------------------------------ } BIDIRECT_CONTROL p_mdata = output when mdata_oe = 1; BIDIRECT_CONTROL p_ad = output when oe_ad = 1; BIDIRECT_CONTROL p_cbe_ = output when oe_cbe = 1; BIDIRECT_CONTROL p_par = output when oe_par = 1; BIDIRECT_CONTROL p_frame_ = output when oe_frame = 1; BIDIRECT_CONTROL p_irdy_ = output when oe_irdy = 1; BIDIRECT_CONTROL p_trdy_ = output when oe_slave = 1; BIDIRECT_CONTROL p_stop_ = output when oe_slave = 1; BIDIRECT_CONTROL p_devsel_ = output when oe_slave = 1; BIDIRECT_CONTROL p_perr_ = output when oe_perr = 1; BIDIRECT_CONTROL p_serr_ = output when oe_serr = 1; { ******* Set a 20 ns cycle (20ns clock period) ******** } { ------------------------------------------------------ } CYCLE = 20; EDGE_ALIGN p_sysclk @ 0,10; { clean edges up on this } { ******* Don't care is an 'X' ******** } { ------------------------------------------------------ } DONT_CARE = 'X'; { ******* Output strobing windows ******** } { ------------------------------------------------------ } CHECK_WINDOW { ##### memory interface bidirectional pads ####} p_mdata[31:0], { MDATA[31:0] pins } { #### PCI bus bidirectional pads ####} p_ad[31:0], { A/D pins } p_cbe_[3:0], { C/BE pins } p_par, { PAR pin } p_frame_, { FRAME* pin } p_irdy_, { IRDY* pin } p_trdy_, { TRDY* pin } p_stop_, { STOP* pin } p_devsel_, { DEVSEL* pin } p_perr_, { PERR* pin } p_mdio, { MDIO pin } { memory interface output-only pads } p_maddr[17:0], { MADDR* pin } p_mcs_[3:0], { MCS* pin } p_ras_, { RAS* pin } p_mrd_, { MRD* pin } p_mwe_[3:0], { MWE* pin } p_mgwe_, { MGWE } p_mclk, { MCLK pin } { LXT901 interface output-only pads } p_txd[3:0], { TXD pins } p_tx_en, { TX_EN pin } p_lbk, { LBK pin } p_mdc, { MDC pin } { PCI bus output-only pads } p_req_, { REQ* pin } p_serr_, { SERR* pin } p_int_, { INT* pin } { clock generator output-only pads } p_clk25, { CLK25 pin } { ERST_ pin } p_erst_, { ERST_ pin } { Debug pin } p_dbg[2:0], { DBG pin } @ 18,19; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN resolution 0.001; target_file = "exp3.vhd"; SIMULATOR VHDL_tb_tio -93 { make it '93 compliant } MODULE="test_fed" OUTPUT_GROUP = "p_dbg[2:0]" OUTPUT_GROUP = "p_clk25, p_erst_" INPUT_GROUP = "p_pci_clk, p_rst_, p_gnt_, p_idsel" LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", LIST_ERRORS = "BY_PIN", { Can make this BY_GROUP } MAXLINES="10000" ; { Internal Enables } DELETE_PINS mdata_oe, oe_ad, oe_cbe, oe_par, oe_frame, oe_irdy, oe_slave, oe_serr, oe_perr; END; END; INTERFACES/VHDL/VCDVHDL/exp1.vtran000064400001440000012000000103041103104161000170720ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > VHDL TEST BENCH # # Original File: "exp1.vcd" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN orig_file = "../../DATA/exp1.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} INPUTS qavd; INPUTS qavs; INPUTS avd1a; INPUTS avs1a; INPUTS avd2a; INPUTS avs2a; INPUTS avd2b; INPUTS avs2b; INPUTS avd2c; INPUTS avs2c; INPUTS xclk; INPUTS atstb; INPUTS iddq_en; INPUTS bsb; BIDIRECTS cbi[14:0]; OUTPUTS sclk24; OUTPUTS sclk8; OUTPUTS cx24[3:0]; OUTPUTS sclk; INPUTS fake_oe; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } PROC_BLOCK { ************************************************************ } { * * } { * Use this section to perform bidirect data separation, * } { * to specify strobe (check) windows for outputs * } { * and to do state translations. * } { * * } { ************************************************************ } BEGIN cycle 250; {4 MHz cycle} BIDIRECT_CONTROL cbi[7:0]=input WHEN fake_oe=0; check_window * @ 195, 200; { strobe all outs at 195 } { #### state character translations for 'VCD'->'VHDL TEST BENCH'#### } state_trans outputs 'Z'->'X' END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK { ************************************************************ } { * * } { * Define simulation configurations here. Currently * } { * configured for VHDL using textio. * } { * * } { ************************************************************ } BEGIN aux_file = "exp1.tio"; target_file = "exp1.vhd"; {#### OUTPUT VECTOR FILE ####} SIMULATOR vhdl_tb_tio {#### OUTPUT FORMAT ####} LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", CONFIG_FILE="one_cfg.vhd", LIST_ERRORS = "BY_PIN", { ##### Can make this BY_GROUP ##### } MAXLINES="10000"; { #### IF you wish to exclude pins, like enables, add the following: #### } DELETE_PINS fake_oe, cx24[3:0]; TITLE "pm6124"; END; INTERFACES/VHDL/STILVHDL/000075500001440000012000000000001103104161000153025ustar00jcosleystaff00000400000023INTERFACES/VHDL/STILVHDL/exp1.vtran000064400001440000012000000055241103104161000172410ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > VHDL TEST BENCH # # Original File: "exp1.stil" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into format VHDL TEST BENCH # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'VHDL TEST BENCH'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X', '?'->'X'; disable_vector_filter; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block SIMULATOR vhdl_tb , {#### OUTPUT FORMAT ####} LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", LIST_ERRORS = "BY_PIN", { #### Can make this BY_GROUP #### } OUTPUT_GROUP = "P_MUSTANG_TDO, P_ATSEL_2_N", MAXLINES="10000"; TITLE "marylou"; target_file = "exp1.vhd"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/VHDL/EVCDVHDL/000075500001440000012000000000001103104161000152505ustar00jcosleystaff00000400000023INTERFACES/VHDL/EVCDVHDL/exp1.vtran000064400001440000012000000103431103104161000172020ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > VHDL TEST BENCH # # Original File: "exp1.evcd" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} { ############################################################### if no pins are specified using INPUTS/OUTPUTS/BIDIRECTS statements here, then evcd reader will translate all signals (nodes) and determine direction from evcd state assignments. If there are some bidirectional signals which only have input or only output states assigned in the vector file, the reader will determine them to be input (or output) instead of bidirects. ################################################################} end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'VHDL TEST BENCH' #### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L', 'c'->'H', 'f'->'Z', 'F'->'X'; { #### timing info for cyclization ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; { #### timing for output file #### } pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR vhdl_tb , LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", LIST_ERRORS = "BY_PIN", { #### Can make this BY_GROUP #### } OUTPUT_GROUP = "P_MUSTANG_TDO, P_ATSEL_2_N", MAXLINES="10000"; TITLE "marylou"; target_file = "exp1.vhd"; end; INTERFACES/VHDL/README000064400001440000012000000312441103104161000147350ustar00jcosleystaff00000400000023VHDL TEST BENCH ---------------- The main directory is "VHDL_T" and the sub-directories are -> WGLVHDL -> VCDVHDL -> STILVHDL -> EVCDVHDL -> PCFVHDL The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "WGLVHDL" contains the translation of WGL file to VHDL TEST BENCH output format. Sub-directory -> "EVCDVHDL" contains the translation of EVCD file to VHDL TEST BENCH output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... This directory contains some examples of translating Verilog VCD vectors created during simulation, WGL and STIL vectors generated by ATPG tools, to VHDL testbench modules, which includes checking of expected output state data for re-simulation verification. There are two options for the VHDL testbench format. The VHDL testbench (vhdl_tb) can be generated with straight in-line assignments and checking of signal states, or in a format which uses textio (vhdl_tb_tio) to get state data from a separate external file. The first format gives a longer compile time (since all data in is a single file) but would likely run faster during simulation, whereas the second format would have a much shorter compile time, but perhaps slightly slower run time (since state data is being read from an external file). For the vhdl_tb and vhdl_tb_tio formats, the optional parameters are: SIMULATOR vhdl_tb, { or SIMULATOR vhdl_tb_tio, } -INHIBIT_CHECKING. -93, { for vhdl_tb_tio only } -PROCESS_LABELS, LIBRARY = "NULL", USE = "NULL", UNITS = "ns", CONFIG_FILE = "NULL", CONFIG_NAME = "", ARCHITECTURE = "testbench", INSTANCE_NAME = "U0", ENTITY = "_tb", COMPONENT = "design", COMPONENT_ARCHITECTURE = "STRUCTURAL_VIEW", NINE_VALUE = "OFF", DONT_CARE = 'X', BIT_TYPE = "STD_LOGIC", BIT_VECTOR = "STD_LOGIC_VECTOR", RESULT_TYPE = "STD_LOGIC", RESULT_VECTOR = "STD_LOGIC_VECTOR", STATE_CHARACTERS = "10HLUXZW-", SEVERITY = "WARNING", LIST_ERRORS = "NULL", { vhdl_tb only } PSEUDO_SIGNAL = "NULL", MAXLINES = "nolimit", { vhdl_tb only } INPUT_GROUP = "NULL", MAX_MISMATCHES = "nn", { insert test to terminate if > nn mismatches } MAXMIS_SEVERITY = "FAILURE", OUTPUT_GROUP = "NULL", EQUIV_SIM_STATES = "a->b, c->d, e->f, ...", BUFFER_PORTS = "NULL", LINKAGE_PORTS = "NULL" ; Multiple LIBRARY and USE parameters can be specified. These should typically specify at least the following: LIBRARY = "ieee", USE = "ieee.std_logic_1164.all", USE = "ieee.std_logic_textio.all", (only for vhdl_tb_tio) In some cases it may be desirable to build a testbench file, without actually doing the checking of expected output states - building only a stimulus file. The -INHIBIT_CHECKING parameter, as in the Verilog testbench format, can be used to accomplish this in both VHDL formats. The -93 parameter can be used to force '93 compliant syntax for the declaration and opening of the textio file. The -PROCESS_LABELS flag can be used to tell vtran to add labels to all processes in the VHDL testbench, which is sometimes useful for debugging. The COMPONENT, INSTANCE_NAME, ENTITY and ARCHITECTURE parameters provide control over names used in the VHDL testbench file. The COMPONENT_ARCHITECTURE parameter is used in the CONFIGURATION block. The UNITS parameter can be used to change the time units from (the default) ns - any necessary scaling is done automatically to modify the time stamps accordingly. The CONFIGURATION declaration is placed in the file specified by CONFIG_FILE. If this parameter is missing, then the declaration is placed at the bottom of the testbench file. The NINE_VALUE parameter tells vtran to check (or not check) that all states are legal IEEE states. The DONT_CARE parameter defines the logical state on output pins that the VHDL testbench will treat as a don't care or mask condition. This state can also, and usually should be, declared with the DONT_CARE command in the PROC_BLOCK of the command file so that masking of outputs also uses this state character. After defining this character, any output states which, in addition to this character, are to be treated as a dont_care can be mapped to this character with the STATE_TRANS command. For example, if the DONT_CARE character is defined as 'X' and we want to also ignore outputs when they are in the 'Z' state, then use: state_trans outputs 'Z'->'X'; There are four optional parameters related to defining the TYPE of signals, busses and results arrays. The first two (BIT_TYPE and BIT_VECTOR) are used to specify the TYPE of signals and busses in the design. The other two (RESULT_TYPE and RESULT_VECTOR) are used to specify the TYPE of the results arrays used in the testbench. The STATE_CHARACTERS parameter allows the user to define the legal states for the selected TYPE and these are used in the std2char and vec2str functions in the testbench. For files being translated from print-on-change original vector data, all output pins (including bidirects) should have their strobe (check) time specified using the CHECK_WINDOW command. Multiple commands can be used to specify different check points for different output pin groups. During all times outside of the CHECK_WINDOW, the outputs are forced to the DONT_CARE state (which defaults to X), and checking of output state data is inhibited here. The CHECK_WINDOW command(s) also define the grouping of the output pins for checking - since they are checked at the same time. A CYCLE command must be used to specify the vector set cycle time, since the CHECK_WINDOW command is defined relative to this. Output signal grouping can be further modified using the OUTPUT_GROUP parameter, which can be used when translating either cycle-based files (like WGL or STIL) or print-on-change files (like vcd files). The parameter SEVERITY can be used to change the behavior of the testbench when it detects a pin whose state does not match the expected state. The testbench uses a VHDL "assertion" statement which reports the mismatch with a SEVERITY dictated by this parameter (default is WARNING). The parameter LIST_ERRORS also affects how pin state errors are handled. Normally, the vector for the entire group (BY_GROUP) is displayed with differences between expected and actual highlighted. Changing this parameter's value to BY_PIN results in the display of only those pins which mismatch, along with their expected and actual states (the LIST_ERRORS parameter is available only with the VHDL_TB format). When using the VHDL_TB output format, large simulation data sets can sometimes result in a very large single process in the testbench file. For some logic simulators, this presents a problem. To get around this, the MAXLINES parameter can be used to break the long single process up into multiple smaller processes. For example: MAXLINES = "50000", would limit the size of any given process to approximately 50,000 lines of code. When using the VHDL_TB_TIO output format option, the main testbench file contains a single read loop for getting input stimulus, as well as expected output data from an external textio file. This testbench file also contains the output state checking and error reporting procedures. All simulation data is contained in the textio file, where it is organized in groups of pins. The primary reason for using pin groups in the textio file is to help minimize file size. By default, all pure input pins comprise a single group, while the input data for bidirectional pins comprise a second group. Output pins are grouped according to how they are declared with the CHECK_WINDOW commands. The OUTPUT_GROUP provides an alternate method of grouping output signals - for example it may be necessary to group scan output signals separately. In order to further optimize the file size of the textio file, the INPUT_GROUP parameter can be used to define additional input pin groups. Usually, this would be done for input pins which have a high degree of activity in the file - such as clock pins. An example might be: INPUT_GROUP = "clk1, clk2", INPUT_GROUP = "enb, dir_ctrl", OUTPUT_GROUP = "scan_out1, scan_out2", Here we have used two INPUT_GROUP parameters to define two additional groups - the first with just the clk1 and clk2 pins, the second with enb and dir_ctrl pins. All other input pins would remain in their default groups. Likewise we have formed a group of the two output scan pins which will see a lot of activity during scan operations while other outputs are being masked. The MAX_MISMATCHES parameter, if present, will cause vtran to place code in the VHDL testbench that monitors the number of output state mismatches which are found by the checking procedures, and terminate program execution if the number reaches this specified maximum. MAXMIS_SEVERITY parameter provides a way to control what happens when MAX_MISMATCHES is exceeded. The EQUIV_SIM_STATES parameter indicates to vtran which output simulation states should be treated as equivalent for the purposes of checking simulated output states against expected states. If this parameter is present, state mapping is performed on the simulation output states in the testbench before being checked against the expected states (after STATE_TRANS on these). For example: EQUIV_SIM_STATES = "H->1, L->0", tells vtran to treat an "H" state in the VHDL simulation like a "1", and an "L" state like a "0". This is sometimes necessary when translating from VCD files since a 1 or 0 in the VCD file (which becomes the "expected" state in the testbench file) may actually be an H or L during simulation of the VHDL testbench (due to strength considerations). The BUFFER_PORTS and LINKAGE_PORTS parameters can be used to define pins as buffer or linkage ports for use in the component or module instantiation. These pins must still be defined as inputs, outputs or bidirects in the OVF. See the VTRAN User's Guide and the README7.x file for more information on these interfaces and the optional parameters available. An example command file for an WGL -> VHDL TEST BENCH translation would look like: { #======================================================================# # This is vtran command file. # # Translation: WGL < to > VHDL TEST BENCH # # Original File: "exp1.wgl" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK begin ORIG_FILE = "exp1.wgl"; {#### INPUT VECTOR FILE ####} TABULAR_FORMAT wgl; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the WGL # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } PROC_BLOCK begin end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK begin target_file = "exp1.vhd"; {#### OUTPUT VECTOR FILE ####} { #### You can use this lines if you wish to use TEXTIO ##### } { SIMULATOR vhdl_tb_tio } SIMULATOR vhdl_tb , {#### OUTPUT FORMAT ####} LIBRARY="IEEE", USE="IEEE.STD_LOGIC_1164.ALL", USE="IEEE.STD_LOGIC_TEXTIO.ALL", LIBRARY="STD", USE="STD.STANDARD.ALL", USE="STD.TEXTIO.ALL", BIT_TYPE="STD_LOGIC", BIT_VECTOR="STD_LOGIC_VECTOR", RESULT_TYPE="STD_LOGIC", OUTPUT_GROUP = "SDO0, SDO1", { #### group scan-out pins to reduce file size #### } LIST_ERRORS = "BY_PIN", { #### Can make this BY_GROUP #### } MAXLINES="10000"; TITLE "marylou"; end; ################################################################################ hecking of expected output states - building only a stimulus file. The -INHIBIT_CHECKING parameter, as in the Verilog testbench format, can be used to accomplish this in both VHDL formats. The -93 parameter can be used to force '93 compliant syntax for the declaration and opening of the textio file. The -PROCESS_LABELS flag can be used to tell vINTERFACES/VHDL/PCFVHDL/000075500001440000012000000000001103104161000151375ustar00jcosleystaff00000400000023INTERFACES/VHDL/PCFVHDL/exp1.pcf000064400001440000012000000155441103104161000165170ustar00jcosleystaff00000400000023!* !* Converted by vtran version: 4.2.9g !* Date: Thu Apr 29 15:20:47 PDT 1999 !* Source file: s9.stil !* sequential vector cycle 100n receive delay 90n family LSTTL !* Signal-to-Pin Assignments assign C to pins "1" assign D1 to pins "2" assign D2 to pins "3" assign SE to pins "4" assign SI to pins "5" assign Q4 to pins "6" assign SO to pins "7" assign BI to pins "8" assign GND to pins "9" ! ***Specify GND pins here assign PWR to pins "10" ! ***Specify PWR pins here power GND, PWR ! ***specify power here !* pin directions inputs C, D1, D2, SE, SI outputs Q4, SO bidirectional BI !* Order of signals in vectors pcf order default Parallel is C, D1, D2, SE, SI, Q4, SO, BI !* Order of signals for Scan vectors pcf order Scan is C, SI, SO unit "NewDesign" pcf use timing set wave1 use pcf order Parallel ! CDDSSQSB ! 12EI4OI "00010XXX" ! 5 "00010XXZ" ! 8 "10010XXZ" ! 125 "00010XXZ" ! 145 use pcf order Scan "10X" ! 225 "00X" ! 245 "01X" ! 305 "11X" ! 325 "01X" ! 345 "11X" ! 425 "01X" ! 445 "00X" ! 505 "10X" ! 525 "00L" ! 545 "10X" ! 625 "00L" ! 645 "01X" ! 705 "11X" ! 725 "01H" ! 745 use pcf order Parallel "00001XXZ" ! 805 "10001XXZ" ! 825 "00001XHZ" ! 845 use timing set wave1 "00010XXZ" ! 905 "00011XXZ" ! 1005 "10011XXZ" ! 1025 "00011XXZ" ! 1045 use pcf order Scan "11X" ! 1125 "01X" ! 1145 "11X" ! 1225 "01X" ! 1245 use pcf order Parallel "00001XXZ" ! 1305 "10001XXZ" ! 1325 "00001XXZ" ! 1345 use timing set wave2 "00000XXZ" ! 1405 "00000XX1" ! 1408 "01000XX1" ! 1555 "01000HH1" ! 1745 "01000HHH" ! 1895 "11000XXX" ! 2025 "01000HHH" ! 2045 use timing set wave1 "00010XXX" ! 2155 "00010XXZ" ! 2158 "10010XXZ" ! 2275 "00010XLZ" ! 2295 use pcf order Scan "10X" ! 2375 "00L" ! 2395 "10X" ! 2475 "00H" ! 2495 use pcf order Parallel "00000XXZ" ! 2555 "10000XXZ" ! 2575 "00000XHZ" ! 2595 "00010XXZ" ! 2655 "00011XXZ" ! 2755 "10011XXZ" ! 2775 "00011XXZ" ! 2795 use pcf order Scan "11X" ! 2875 "01X" ! 2895 "11X" ! 2975 "01X" ! 2995 use pcf order Parallel "00000XXZ" ! 3055 "10000XXZ" ! 3075 "00000XHZ" ! 3095 use timing set wave2 "00000XX1" ! 3158 "00101XX1" ! 3305 "00101HH1" ! 3495 "00101HHH" ! 3645 "10101XXX" ! 3775 "00101HHH" ! 3795 use timing set wave1 "00010XXX" ! 3905 "00010XXZ" ! 3908 "10010XXZ" ! 4025 "00010XLZ" ! 4045 use pcf order Scan "10X" ! 4125 "00L" ! 4145 "10X" ! 4225 "00H" ! 4245 use pcf order Parallel "00000XXZ" ! 4305 "10000XXZ" ! 4325 "00000XLZ" ! 4345 "00010XXZ" ! 4405 "10010XXZ" ! 4525 "00010XXZ" ! 4545 use pcf order Scan "10X" ! 4625 "00X" ! 4645 "01X" ! 4705 "11X" ! 4725 "01X" ! 4745 use pcf order Parallel "00001XXZ" ! 4805 "10001XXZ" ! 4825 "00001XHZ" ! 4845 use timing set wave2 "00000XXZ" ! 4905 "00000XX1" ! 4908 "01010XX1" ! 5055 "01010LL1" ! 5245 "01010LLH" ! 5395 "11010XXX" ! 5525 "01010LLH" ! 5545 use timing set wave1 "00010XXX" ! 5655 "00010XXZ" ! 5658 "10010XXZ" ! 5775 "00010XLZ" ! 5795 use pcf order Scan "10X" ! 5875 "00H" ! 5895 "10X" ! 5975 "00H" ! 5995 use pcf order Parallel "00000XXZ" ! 6055 "10000XXZ" ! 6075 "00000XLZ" ! 6095 "00010XXZ" ! 6155 "00011XXZ" ! 6255 "10011XXZ" ! 6275 "00011XXZ" ! 6295 use pcf order Scan "00X" ! 6355 "10X" ! 6375 "00X" ! 6395 "10X" ! 6475 "00X" ! 6495 use pcf order Parallel "00001XXZ" ! 6555 "10001XXZ" ! 6575 "00001XHZ" ! 6595 use timing set wave2 "00000XXZ" ! 6655 "00000XX1" ! 6658 "00101XX1" ! 6805 "00101HH1" ! 6995 "00101HHH" ! 7145 "10101XXX" ! 7275 "00101HHH" ! 7295 use timing set wave1 "00010XXX" ! 7405 "00010XXZ" ! 7408 "10010XXZ" ! 7525 "00010XHZ" ! 7545 use pcf order Scan "10X" ! 7625 "00H" ! 7645 "10X" ! 7725 "00L" ! 7745 use pcf order Parallel "00000XXZ" ! 7805 "10000XXZ" ! 7825 "00000XLZ" ! 7845 "00010XXZ" ! 7905 "00011XXZ" ! 8005 "10011XXZ" ! 8025 "00011XXZ" ! 8045 use pcf order Scan "11X" ! 8125 "01X" ! 8145 "00X" ! 8205 "10X" ! 8225 "00X" ! 8245 use pcf order Parallel "00001XXZ" ! 8305 "10001XXZ" ! 8325 "00001XLZ" ! 8345 use timing set wave2 "00000XXZ" ! 8405 "00000XX1" ! 8408 "01100XX1" ! 8555 "01100HH1" ! 8745 "01100HHH" ! 8895 "11100XXX" ! 9025 "01100HHH" ! 9045 use timing set wave1 "00010XXX" ! 9155 "00010XXZ" ! 9158 "10010XXZ" ! 9275 "00010XHZ" ! 9295 use pcf order Scan "10X" ! 9375 "00L" ! 9395 "10X" ! 9475 "00L" ! 9495 use pcf order Parallel "00000XXZ" ! 9555 "10000XXZ" ! 9575 "00000XHZ" ! 9595 "00010XXZ" ! 9655 "00011XXZ" ! 9755 "10011XXZ" ! 9775 "00011XXZ" ! 9795 use pcf order Scan "11X" ! 9875 "01X" ! 9895 "00X" ! 9955 "10X" ! 9975 "00X" ! 9995 use pcf order Parallel "00000XXZ" ! 10055 "10000XXZ" ! 10075 "00000XLZ" ! 10095 use timing set wave2 "00000XX1" ! 10158 "01011XX1" ! 10305 "01011HH1" ! 10495 "01011HHH" ! 10645 "11011XXX" ! 10775 "01011HHH" ! 10795 use timing set wave1 "00010XXX" ! 10905 "00010XXZ" ! 10908 "10010XXZ" ! 11025 "00010XHZ" ! 11045 use pcf order Scan "10X" ! 11125 "00L" ! 11145 "10X" ! 11225 "00L" ! 11245 use pcf order Parallel "00000XXZ" ! 11305 "10000XXZ" ! 11325 "00000XHZ" ! 11345 "00010XXZ" ! 11405 "00011XXZ" ! 11505 "10011XXZ" ! 11525 "00011XXZ" ! 11545 use pcf order Scan "00X" ! 11605 "10X" ! 11625 "00X" ! 11645 "01X" ! 11705 "11X" ! 11725 "01X" ! 11745 use pcf order Parallel "00000XXZ" ! 11805 "10000XXZ" ! 11825 "00000XLZ" ! 11845 use timing set wave2 "00000XX1" ! 11908 "00101XX1" ! 12055 "00101HH1" ! 12245 "00101HHH" ! 12395 "10101XXX" ! 12525 "00101HHH" ! 12545 use timing set wave1 "00010XXX" ! 12655 "00010XXZ" ! 12658 "10010XXZ" ! 12775 "00010XHZ" ! 12795 use pcf order Scan "10X" ! 12875 "00H" ! 12895 "10X" ! 12975 "00H" ! 12995 use pcf order Parallel "00000XXZ" ! 13055 "10000XXZ" ! 13075 "00000XLZ" ! 13095 "00010XXZ" ! 13155 "00011XXZ" ! 13255 "10011XXZ" ! 13275 "00011XXZ" ! 13295 use pcf order Scan "00X" ! 13355 "10X" ! 13375 "00X" ! 13395 "10X" ! 13475 "00X" ! 13495 use pcf order Parallel "00001XXZ" ! 13555 "10001XXZ" ! 13575 "00001XHZ" ! 13595 use timing set wave2 "00000XXZ" ! 13655 "00000XX1" ! 13658 "01111XX1" ! 13805 "01111HH1" ! 13995 "01111HHL" ! 14145 "11111XXX" ! 14275 "01111HHL" ! 14295 use timing set wave1 "00010XXX" ! 14405 "00010XXZ" ! 14408 "10010XXZ" ! 14525 "00010XLZ" ! 14545 use pcf order Scan "10X" ! 14625 "00L" ! 14645 "10X" ! 14725 "00H" ! 14745 use pcf order Parallel "00000XXZ" ! 14805 "10000XXZ" ! 14825 "00000XHZ" ! 14845 end pcf end unit INTERFACES/VHDL/PCFVHDL/exp1.vtran000064400001440000012000000045411103104161000170740ustar00jcosleystaff00000400000023 { #======================================================================# # This is vtran command file. # # Translation: PCF < to > VHDL TEST BENCH # # Original File: "exp1.pcf" # # Target File: "exp1.vhd " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file = "exp1.pcf"; {#### INPUT VECTOR FILE ####} tabular_format pcf; {#### INPUT FORMAT ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the PCF # # vector data to translate into VHDL TEST BENCH format # #======================================================================# } proc_block begin { #### state character translations for 'PCF'->'VHDL TEST BENCH'#### } state_trans outputs 'H'->'1', 'L'->'0'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block begin header 500; simulator VHDL_tb {#### OUTPUT FORMAT ####} instance_name = "U0", entity = "PentiumIV_ent", component = "PentiumIV" ; target_file = "exp1.vhd"; {#### OUTPUT VECTOR FILE ####} end; end; INTERFACES/WGL/000075500001440000012000000000001103104161000137455ustar00jcosleystaff00000400000023INTERFACES/WGL/VCDWGL/000075500001440000012000000000001103104161000147335ustar00jcosleystaff00000400000023INTERFACES/WGL/VCDWGL/exp2.vtran000064400001440000012000000172141103104161000166720ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > WGL # # Original File: "exp1.vcd" # # Target File: "exp1.wgl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } OVF_BLOCK BEGIN CASE_SENSITIVE = TRUE ; ORIG_FILE "exp2.vcd"; {#### INPUT VECTOR FILE ####} SCRIPT_FORMAT verilog_vcd; {#### INPUT FORMAT ####} { ##### all pins and their directions #####} BIDIRECTS pa[27:0] pbrk_n; OUTPUTS pclko ; BIDIRECTS pcrst_n pcs_n[7:0] pcts_n[1:0] pd[31:0]; INPUTS penmi_n; OUTPUTS phak_n; INPUTS phld_n; BIDIRECTS pioa[7:0]; OUTPUTS plok_n; BIDIRECTS pmiso pmosi; INPUTS ppdw_n; BIDIRECTS prclk; OUTPUTS pre_n; BIDIRECTS pread; OUTPUTS prst; BIDIRECTS prts_n[1:0] prxd[1:0] psck pscs_n[3:0]; INPUTS ptck; BIDIRECTS ptclk[2:0]; INPUTS ptdi; BIDIRECTS ptdo ptioa[2:0] ptiob[2:0]; INPUTS ptms ptrst_n; BIDIRECTS ptxd[1:0]; INPUTS pwait_n pwak_n; OUTPUTS pwe_n pwrite; INPUTS pwrst_n; OUTPUTS pxak_n; INPUTS pxin; OUTPUTS pxout; BIDIRECTS pxrq_n; OUTPUTS pads_pcrst_n_2, pads_ptdo_n_2 , pads_pbrk_n_2 , pads_puck_n_2 , pads_prts1_n_2, pads_pcts1_n_2, pads_prxd1_n_2, pads_ptxd1_n_2, pads_prts0_n_2, pads_pcts0_n_2, pads_prxd0_n_2, pads_ptxd0_n_2, pads_psck_n_2, pads_pmiso_n_2, pads_pmosi_n_2, pads_pscs0_n_2, pads_pscs1_n_2, pads_pscs2_n_2, pads_pscs3_n_2, pads_pioa7_n_2, pads_pioa6_n_2, pads_pioa5_n_2, pads_pioa4_n_2, pads_pioa3_n_2, pads_pioa2_n_2, pads_pioa1_n_2, pads_pioa0_n_2, pads_ptiob2_n_2, pads_ptioa2_n_2, pads_ptclk2_n_2, pads_ptiob1_n_2, pads_ptioa1_n_2, pads_ptclk1_n_2, pads_ptiob0_n_2, pads_ptioa0_n_2, pads_pd9_n_2 , pads_pa27_n_2, pads_pa26_n_2, pads_pa25_n_2, pads_pa24_n_2, pads_pxrq_n_2, pads_pcs5_n_2, pads_pcs6_n_2, pads_pcs7_n_2, pads_pcs4_n_2; END; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into WGL format # #======================================================================# } PROC_BLOCK BEGIN DISABLE_VECTOR_FILTER; { #### state character translations for 'VCD'->'WGL'#### } STATE_TRANS 'x'->'X', 'z'->'Z' ; { Separate bidir in from out data using control pins } BIDIRECT_CONTROL pcrst_n = output when pads_pcrst_n_2 =0; BIDIRECT_CONTROL ptdo = output when pads_ptdo_n_2 =0; BIDIRECT_CONTROL pbrk_n = output when pads_pbrk_n_2 =0; BIDIRECT_CONTROL prclk = output when pads_puck_n_2 =0; BIDIRECT_CONTROL prts_n[1] = output when pads_prts1_n_2 =0; BIDIRECT_CONTROL pcts_n[1] = output when pads_pcts1_n_2 =0; BIDIRECT_CONTROL prxd[1] = output when pads_prxd1_n_2 =0; BIDIRECT_CONTROL ptxd[1] = output when pads_ptxd1_n_2 =0; BIDIRECT_CONTROL prts_n[0] = output when pads_prts0_n_2 =0; BIDIRECT_CONTROL pcts_n[0] = output when pads_pcts0_n_2 =0; BIDIRECT_CONTROL prxd[0] = output when pads_prxd0_n_2 =0; BIDIRECT_CONTROL ptxd[0] = output when pads_ptxd0_n_2 =0; BIDIRECT_CONTROL psck = output when pads_psck_n_2 =0; BIDIRECT_CONTROL pmiso = output when pads_pmiso_n_2 =0; BIDIRECT_CONTROL pmosi = output when pads_pmosi_n_2 =0; BIDIRECT_CONTROL pscs_n[0] = output when pads_pscs0_n_2 =0; BIDIRECT_CONTROL pscs_n[1] = output when pads_pscs1_n_2 =0; BIDIRECT_CONTROL pscs_n[2] = output when pads_pscs2_n_2 =0; BIDIRECT_CONTROL pscs_n[3] = output when pads_pscs3_n_2 =0; BIDIRECT_CONTROL pioa[7] = output when pads_pioa7_n_2 =0; BIDIRECT_CONTROL pioa[6] = output when pads_pioa6_n_2 =0; BIDIRECT_CONTROL pioa[5] = output when pads_pioa5_n_2 =0; BIDIRECT_CONTROL pioa[4] = output when pads_pioa4_n_2 =0; BIDIRECT_CONTROL pioa[3] = output when pads_pioa3_n_2 =0; BIDIRECT_CONTROL pioa[2] = output when pads_pioa2_n_2 =0; BIDIRECT_CONTROL pioa[1] = output when pads_pioa1_n_2 =0; BIDIRECT_CONTROL pioa[0] = output when pads_pioa0_n_2 =0; BIDIRECT_CONTROL ptiob[2] = output when pads_ptiob2_n_2 =0; BIDIRECT_CONTROL ptioa[2] = output when pads_ptioa2_n_2 =0; BIDIRECT_CONTROL ptclk[2] = output when pads_ptclk2_n_2 =0; BIDIRECT_CONTROL ptiob[1] = output when pads_ptiob1_n_2 =0; BIDIRECT_CONTROL ptioa[1] = output when pads_ptioa1_n_2 =0; BIDIRECT_CONTROL ptclk[1] = output when pads_ptclk1_n_2 =0; BIDIRECT_CONTROL ptiob[0] = output when pads_ptiob0_n_2 =0; BIDIRECT_CONTROL ptioa[0] = output when pads_ptioa0_n_2 =0; BIDIRECT_CONTROL pd[31], pd[30], pd[29], pd[28], pd[27], pd[26], pd[25], pd[24], pd[23], pd[22], pd[21], pd[20], pd[19], pd[18], pd[17], pd[16], pd[15], pd[14], pd[13], pd[12], pd[11], pd[10], pd[9], pd[8], pd[7], pd[6], pd[5], pd[4], pd[3], pd[2], pd[1], pd[0] = output when pads_pd9_n_2 =0; BIDIRECT_CONTROL pa[27] = output when pads_pa27_n_2 =0; BIDIRECT_CONTROL pa[26] = output when pads_pa26_n_2 =0; BIDIRECT_CONTROL pa[25] = output when pads_pa25_n_2 =0; BIDIRECT_CONTROL pa[24] = output when pads_pa24_n_2 =0; BIDIRECT_CONTROL pxrq_n = output when pads_pxrq_n_2 =0; BIDIRECT_CONTROL pcs_n[4] = output when pads_pcs4_n_2 =0; BIDIRECT_CONTROL pcs_n[5] = output when pads_pcs5_n_2 =0; BIDIRECT_CONTROL pcs_n[6] = output when pads_pcs6_n_2 =0; BIDIRECT_CONTROL pcs_n[7] = output when pads_pcs7_n_2 =0; { collapse to cycle-based data, strobe all pins at 99 in cycle } CYCLE = 100; ALIGN_TO_STEP 100 99; { need to be sure all pins are stable here and any clocks are in their active state here (99) - use ALIGN_TO_CYCLE if need different strobe times for different pins } { now define some timing for WGL file } { since VCD file does not contain this info separately } PINTYPE NRZ * @ 0; { drive all inputs at 5 } PINTYPE STB * @ 90; { strobe all outputs at 90 } PINTYPE RO pxin @ 50, 100; { clock pin return-to-1 behavior } SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } TVF_BLOCK BEGIN SIMULATOR WGL; {#### OUTPUT FORMAT ####} TARGET_FILE "exp2.wgl"; {#### OUTPUT FILE ####} END; END; , pads_pscs1_n_2, pads_pscs2_n_2, pads_pscs3_n_2, pads_pioa7_n_2, pads_pioa6_n_2, pads_pioa5_n_2, pads_pioa4_n_2, pads_pioa3_n_2, pads_pioa2_n_2, pads_pioa1_n_2, pads_pioa0_n_2, pads_ptiob2_n_2, pads_ptioa2_n_2, pads_ptclk2_n_2, pads_ptiob1_n_2, pads_ptioa1_n_2, pads_ptclk1_n_2, pads_ptiob0_n_2, pads_ptioa0_n_2, pads_pd9_n_2 , pads_pa27_n_2, pads_pa26INTERFACES/WGL/VCDWGL/exp1.vtran000064400001440000012000000230631127012712200167000ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: VCD < to > WGL # # Original File: "exp1.vcd" # # Target File: "exp1.wgl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block BEGIN orig_file = "exp1.vcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} INPUTS rstn scan_en_n test_en_n clkin clk_ratio hclkin hcs_n; BIDIRECTS has_n hwr hwait_n hrdy_n hblast hhold hholda ; INPUTS harb hboff; BIDIRECTS hbe_n[3] hbe_n[2] hbe_n[1] hbe_n[0] hd[31] hd[30] hd[29] hd[28] hd[27] hd[26] hd[25] hd[24] hd[23] hd[22] hd[21] hd[20] hd[19] hd[18] hd[17] hd[16] hd[15] hd[14] hd[13] hd[12] hd[11] hd[10] hd[9] hd[8] hd[7] hd[6] hd[5] hd[4] hd[3] hd[2] hd[1] hd[0] ; BIDIRECTS srck0 srfs0 ; INPUTS srd0; BIDIRECTS srck1 srfs1 ; INPUTS srd1; BIDIRECTS srck2 srfs2 ; INPUTS srd2; BIDIRECTS srck3 srfs3 ; INPUTS srd3; BIDIRECTS stck0 stfs0 std0 stck1 stfs1 std1 stck2 stfs2 std2 stck3 stfs3 std3 gpio[15] gpio[14] gpio[13] gpio[12] gpio[11] gpio[10] gpio[9] gpio[8] gpio[7] gpio[6] gpio[5] gpio[4] gpio[3] gpio[2] gpio[1] gpio[0]; INPUTS jtsel lx_bisten pjclk pjrstb pjms pjdi; BIDIRECTS pjdo; INPUTS ljclk ljrstb ljms ljdi; BIDIRECTS ljdo; INPUTS ej_rst_n; BIDIRECTS {actually tri-state output pins } ejtag[2] ejtag[1] ejtag[0] ej_dclk; INPUTS pll_rstn pll_oe pll_bp pll_pd pll_sel[2] pll_sel[1] pll_sel[0]; BIDIRECTS pll_clkout; INPUTS dm_sel[5] dm_sel[4] dm_sel[3] dm_sel[2] dm_sel[1] dm_sel[0] tm_dsp tm_hi tm_sb ; INPUTS { actually control pins for bidirs } pad_ej_outen pad_gpio_outen[0] pad_gpio_outen[1] pad_gpio_outen[10] pad_gpio_outen[11] pad_gpio_outen[12] pad_gpio_outen[13] pad_gpio_outen[14] pad_gpio_outen[15] pad_gpio_outen[2] pad_gpio_outen[3] pad_gpio_outen[4] pad_gpio_outen[5] pad_gpio_outen[6] pad_gpio_outen[7] pad_gpio_outen[8] pad_gpio_outen[9] pad_has_n_outen pad_hbe_n_outen pad_hblast_outen pad_hd_outen_d pad_hd_outen_z pad_hhold_outen pad_hholda_outen pad_hrdy_n_outen pad_hwait_n_outen pad_hwr_outen pad_ljdo_outen pad_pjdo_outen pad_pll_clkout_outen pad_sck_outen[0] pad_sck_outen[1] pad_sck_outen[2] pad_sck_outen[3] pad_sck_outen[4] pad_sck_outen[5] pad_sck_outen[6] pad_sck_outen[7] pad_sfs_outen[0] pad_sfs_outen[1] pad_sfs_outen[2] pad_sfs_outen[3] pad_sfs_outen[4] pad_sfs_outen[5] pad_sfs_outen[6] pad_sfs_outen[7] pad_sxd_outen[0] pad_sxd_outen[1] pad_sxd_outen[2] pad_sxd_outen[3]; END: { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into WGL format # #======================================================================# } proc_block BEGIN add_pin CLK = 1; disable_vector_filter; { #### state character translations for 'VCD'->'WGL'#### } STATE_TRANS inputs 'x'->'X', 'z'->'X' ; STATE_TRANS outputs 'x'->'Z', 'z'->'Z' ; { #### Collapse to 6 ns cycle, strobing pins as specified #### } cycle 6; align_to_cycle 6 PURE_INPUTS @ 1, BIDIR_INPUTS @ 3, BIDIR_OUTPUTS @ 2 ; { #### Separate bidirectional data using control pins #### } bidirect_control hd[31:0] = output when pad_hd_outen_d = 0; bidirect_control has_n = output when pad_has_n_outen = 0; bidirect_control hblast = output when pad_hblast_outen = 0; bidirect_control hwr = output when pad_hwr_outen = 0; bidirect_control hbe_n[3:0] = output when pad_hbe_n_outen = 0; bidirect_control hhold = output when pad_hhold_outen = 0; bidirect_control hholda = output when pad_hholda_outen = 0; bidirect_control hrdy_n = output when pad_hrdy_n_outen = 0; bidirect_control hwait_n = output when pad_hwait_n_outen = 0; bidirect_control srck0 = output when pad_sck_outen[0] = 0; bidirect_control srck1 = output when pad_sck_outen[1] = 0; bidirect_control srck2 = output when pad_sck_outen[2] = 0; bidirect_control srck3 = output when pad_sck_outen[3] = 0; bidirect_control stck0 = output when pad_sck_outen[4] = 0; bidirect_control stck1 = output when pad_sck_outen[5] = 0; bidirect_control stck2 = output when pad_sck_outen[6] = 0; bidirect_control stck3 = output when pad_sck_outen[7] = 0; bidirect_control srfs0 = output when pad_sfs_outen[0] = 0; bidirect_control srfs1 = output when pad_sfs_outen[1] = 0; bidirect_control srfs2 = output when pad_sfs_outen[2] = 0; bidirect_control srfs3 = output when pad_sfs_outen[3] = 0; bidirect_control stfs0 = output when pad_sfs_outen[4] = 0; bidirect_control stfs1 = output when pad_sfs_outen[5] = 0; bidirect_control stfs2 = output when pad_sfs_outen[6] = 0; bidirect_control stfs3 = output when pad_sfs_outen[7] = 0; bidirect_control std0 = output when pad_sxd_outen[0] = 0; bidirect_control std1 = output when pad_sxd_outen[1] = 0; bidirect_control std2 = output when pad_sxd_outen[2] = 0; bidirect_control std3 = output when pad_sxd_outen[3] = 0; bidirect_control gpio[15] = output when pad_gpio_outen[15] = 0; bidirect_control gpio[14] = output when pad_gpio_outen[14] = 0; bidirect_control gpio[13] = output when pad_gpio_outen[13] = 0; bidirect_control gpio[12] = output when pad_gpio_outen[12] = 0; bidirect_control gpio[11] = output when pad_gpio_outen[11] = 0; bidirect_control gpio[10] = output when pad_gpio_outen[10] = 0; bidirect_control gpio[9] = output when pad_gpio_outen[9] = 0; bidirect_control gpio[8] = output when pad_gpio_outen[8] = 0; bidirect_control gpio[7] = output when pad_gpio_outen[7] = 0; bidirect_control gpio[6] = output when pad_gpio_outen[6] = 0; bidirect_control gpio[5] = output when pad_gpio_outen[5] = 0; bidirect_control gpio[4] = output when pad_gpio_outen[4] = 0; bidirect_control gpio[3] = output when pad_gpio_outen[3] = 0; bidirect_control gpio[2] = output when pad_gpio_outen[2] = 0; bidirect_control gpio[1] = output when pad_gpio_outen[1] = 0; bidirect_control gpio[0] = output when pad_gpio_outen[0] = 0; bidirect_control pjdo = output when pad_pjdo_outen = 0; bidirect_control ljdo = output when pad_ljdo_outen = 0; bidirect_control ejtag[2] = output when pad_ej_outen = 0; bidirect_control ejtag[1] = output when pad_ej_outen = 0; bidirect_control ejtag[0] = output when pad_ej_outen = 0; bidirect_control ej_dclk = output when pad_ej_outen = 0; bidirect_control pll_clkout = output when pad_pll_clkout_outen = 0; { #### define some timing for the WGL file #### } PINTYPE NRZ * @ 2; { #### drive all inputs at 2 #### } PINTYPE STB * @ 5; { #### strobe all outputs at 5 #### } PINTYPE RZ clkin @ 1, 4; { #### clock pin behavior #### } pintype RZ2X CLK @ 0, 50, 125, 200; SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN DELETE_PINS { #### These are the control pins #### } pad_ej_outen pad_gpio_outen[0] pad_gpio_outen[1] pad_gpio_outen[10] pad_gpio_outen[11] pad_gpio_outen[12] pad_gpio_outen[13] pad_gpio_outen[14] pad_gpio_outen[15] pad_gpio_outen[2] pad_gpio_outen[3] pad_gpio_outen[4] pad_gpio_outen[5] pad_gpio_outen[6] pad_gpio_outen[7] pad_gpio_outen[8] pad_gpio_outen[9] pad_has_n_outen pad_hbe_n_outen pad_hblast_outen pad_hd_outen_d pad_hd_outen_z pad_hhold_outen pad_hholda_outen pad_hrdy_n_outen pad_hwait_n_outen pad_hwr_outen pad_ljdo_outen pad_pjdo_outen pad_pll_clkout_outen pad_sck_outen[0] pad_sck_outen[1] pad_sck_outen[2] pad_sck_outen[3] pad_sck_outen[4] pad_sck_outen[5] pad_sck_outen[6] pad_sck_outen[7] pad_sfs_outen[0] pad_sfs_outen[1] pad_sfs_outen[2] pad_sfs_outen[3] pad_sfs_outen[4] pad_sfs_outen[5] pad_sfs_outen[6] pad_sfs_outen[7] pad_sxd_outen[0] pad_sxd_outen[1] pad_sxd_outen[2] pad_sxd_outen[3]; SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp1.wgl"; {#### OUTPUT VECTOR FILE ####} END; tm_sb ; INPUTS { actually control pins for bidirs } pad_ej_outen pad_gpio_outen[0] pad_gpio_outen[1] pad_gpio_outen[10] pad_gpio_outen[11] pad_gpio_outen[12] pad_gpio_outen[13] pad_gpio_outen[14] pad_gpio_outen[15] pad_gpio_outen[2] pad_gpio_outen[3] pad_gpio_outen[4] pad_gpio_outen[5] pad_gpio_outen[6] pad_gpio_outen[7] pad_gpio_outen[8] pad_gpio_outen[9] pad_has_n_outen pad_hbe_n_outen pad_hblast_outen pad_hd_outINTERFACES/WGL/VCDWGL/exp1.vcd000064400001440000012000000376321103104161000163210ustar00jcosleystaff00000400000023$date Sep 20, 2000 16:57:02 $end $version ncsim: v2.2.(s3) $end $timescale 10 ps $end $scope module membistv_chip $end $scope module chip $end $var wire 1 ! hclkin $end $var wire 1 " harb $end $var wire 1 # hcs_n $end $var wire 1 $ hhold $end $var wire 1 % hholda $end $var wire 1 & hblast $end $var wire 1 ' has_n $end $var wire 1 ( hwr $end $var wire 1 ) hbe_n [3] $end $var wire 1 * hbe_n [2] $end $var wire 1 + hbe_n [1] $end $var wire 1 , hbe_n [0] $end $var wire 1 - hwait_n $end $var wire 1 . hboff $end $var wire 1 / hrdy_n $end $var wire 1 0 hd [31] $end $var wire 1 1 hd [30] $end $var wire 1 2 hd [29] $end $var wire 1 3 hd [28] $end $var wire 1 4 hd [27] $end $var wire 1 5 hd [26] $end $var wire 1 6 hd [25] $end $var wire 1 7 hd [24] $end $var wire 1 8 hd [23] $end $var wire 1 9 hd [22] $end $var wire 1 : hd [21] $end $var wire 1 ; hd [20] $end $var wire 1 < hd [19] $end $var wire 1 = hd [18] $end $var wire 1 > hd [17] $end $var wire 1 ? hd [16] $end $var wire 1 @ hd [15] $end $var wire 1 A hd [14] $end $var wire 1 B hd [13] $end $var wire 1 C hd [12] $end $var wire 1 D hd [11] $end $var wire 1 E hd [10] $end $var wire 1 F hd [9] $end $var wire 1 G hd [8] $end $var wire 1 H hd [7] $end $var wire 1 I hd [6] $end $var wire 1 J hd [5] $end $var wire 1 K hd [4] $end $var wire 1 L hd [3] $end $var wire 1 M hd [2] $end $var wire 1 N hd [1] $end $var wire 1 O hd [0] $end $var wire 1 P srck0 $end $var wire 1 Q srd0 $end $var wire 1 R srfs0 $end $var wire 1 S stck0 $end $var wire 1 T std0 $end $var wire 1 U stfs0 $end $var wire 1 V srck1 $end $var wire 1 W srd1 $end $var wire 1 X srfs1 $end $var wire 1 Y stck1 $end $var wire 1 Z std1 $end $var wire 1 [ stfs1 $end $var wire 1 \ srck2 $end $var wire 1 ] srd2 $end $var wire 1 ^ srfs2 $end $var wire 1 _ stck2 $end $var wire 1 ` std2 $end $var wire 1 a stfs2 $end $var wire 1 b srck3 $end $var wire 1 c srd3 $end $var wire 1 d srfs3 $end $var wire 1 e stck3 $end $var wire 1 f std3 $end $var wire 1 g stfs3 $end $var wire 1 h gpio [15] $end $var wire 1 i gpio [14] $end $var wire 1 j gpio [13] $end $var wire 1 k gpio [12] $end $var wire 1 l gpio [11] $end $var wire 1 m gpio [10] $end $var wire 1 n gpio [9] $end $var wire 1 o gpio [8] $end $var wire 1 p gpio [7] $end $var wire 1 q gpio [6] $end $var wire 1 r gpio [5] $end $var wire 1 s gpio [4] $end $var wire 1 t gpio [3] $end $var wire 1 u gpio [2] $end $var wire 1 v gpio [1] $end $var wire 1 w gpio [0] $end $var wire 1 x pjclk $end $var wire 1 y pjdo $end $var wire 1 z pjrstb $end $var wire 1 { pjms $end $var wire 1 | pjdi $end $var wire 1 } ljclk $end $var wire 1 ~ ljdo $end $var wire 1 !! ljrstb $end $var wire 1 "! ljms $end $var wire 1 #! ljdi $end $var wire 1 $! ej_rst_n $end $var wire 1 %! ej_dclk $end $var wire 1 &! ejtag [2] $end $var wire 1 '! ejtag [1] $end $var wire 1 (! ejtag [0] $end $var wire 1 )! scan_en_n $end $var wire 1 *! test_en_n $end $var wire 1 +! jtsel $end $var wire 1 ,! lx_bisten $end $var wire 1 -! tm_dsp $end $var wire 1 .! tm_hi $end $var wire 1 /! tm_sb $end $var wire 1 0! rstn $end $var wire 1 1! dm_sel [5] $end $var wire 1 2! dm_sel [4] $end $var wire 1 3! dm_sel [3] $end $var wire 1 4! dm_sel [2] $end $var wire 1 5! dm_sel [1] $end $var wire 1 6! dm_sel [0] $end $var wire 1 7! pll_rstn $end $var wire 1 8! pll_oe $end $var wire 1 9! pll_bp $end $var wire 1 :! pll_pd $end $var wire 1 ;! pll_clkout $end $var wire 1 ! pll_sel [1] $end $var wire 1 ?! pll_sel [0] $end $var wire 1 )! clk_ratio $end $var wire 1 @! pad_hhold_outen $end $var wire 1 A! pad_hholda_outen $end $var wire 1 B! pad_hblast_outen $end $var wire 1 C! pad_has_n_outen $end $var wire 1 D! pad_hwr_outen $end $var wire 1 E! pad_hbe_n_outen $end $var wire 1 F! pad_hwait_n_outen $end $var wire 1 G! pad_hrdy_n_outen $end $var wire 1 H! pad_hd_outen_d $end $var wire 1 I! pad_hd_outen_z $end $var wire 1 J! pad_sck_outen [0] $end $var wire 1 K! pad_sfs_outen [0] $end $var wire 1 L! pad_sck_outen [4] $end $var wire 1 M! pad_sxd_outen [0] $end $var wire 1 N! pad_sfs_outen [4] $end $var wire 1 O! pad_sck_outen [1] $end $var wire 1 P! pad_sfs_outen [1] $end $var wire 1 Q! pad_sck_outen [5] $end $var wire 1 R! pad_sxd_outen [1] $end $var wire 1 S! pad_sfs_outen [5] $end $var wire 1 T! pad_sck_outen [2] $end $var wire 1 U! pad_sfs_outen [2] $end $var wire 1 V! pad_sck_outen [6] $end $var wire 1 W! pad_sxd_outen [2] $end $var wire 1 X! pad_sfs_outen [6] $end $var wire 1 Y! pad_sck_outen [3] $end $var wire 1 Z! pad_sfs_outen [3] $end $var wire 1 [! pad_sck_outen [7] $end $var wire 1 \! pad_sxd_outen [3] $end $var wire 1 ]! pad_sfs_outen [7] $end $var wire 1 ^! pad_gpio_outen [15] $end $var wire 1 _! pad_gpio_outen [14] $end $var wire 1 `! pad_gpio_outen [13] $end $var wire 1 a! pad_gpio_outen [12] $end $var wire 1 b! pad_gpio_outen [11] $end $var wire 1 c! pad_gpio_outen [10] $end $var wire 1 d! pad_gpio_outen [9] $end $var wire 1 e! pad_gpio_outen [8] $end $var wire 1 f! pad_gpio_outen [7] $end $var wire 1 g! pad_gpio_outen [6] $end $var wire 1 h! pad_gpio_outen [5] $end $var wire 1 i! pad_gpio_outen [4] $end $var wire 1 j! pad_gpio_outen [3] $end $var wire 1 k! pad_gpio_outen [2] $end $var wire 1 l! pad_gpio_outen [1] $end $var wire 1 m! pad_gpio_outen [0] $end $scope module pad_top $end $var wire 1 n! pad_ej_outen $end $upscope $end $scope module pad_right $end $var wire 1 o! pad_pjdo_outen $end $var wire 1 p! pad_ljdo_outen $end $var wire 1 p! pad_pll_clkout_outen $end $upscope $end $upscope $end $upscope $end $enddefinitions $end $dumpvars z! z" z# x$ x% z& z' z( z) z* z+ z, z- z. z/ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z: z; z< z= z> z? z@ zA zB zC zD zE zF zG zH zI zJ zK zL zM zN zO xP zQ xR xS xT xU xV zW xX xY xZ x[ x\ z] x^ x_ x` xa xb zc xd xe xf xg xh xi xj xk xl xm xn xo xp xq xr xs xt xu xv xw 0x xy 0z 0{ 0| z} x~ z!! z"! z#! z$! x%! x&! x'! x(! 1)! 1*! 0+! z,! z-! z.! 0/! 00! z1! z2! z3! z4! z5! z6! z7! 08! 09! 0:! x;! 0! 1?! x@! xA! 1B! 1C! 1D! 1E! 1F! 1G! 1H! 1I! xJ! xK! xL! xM! xN! xO! xP! xQ! xR! xS! xT! xU! xV! xW! xX! xY! xZ! x[! x\! x]! x^! x_! x`! xa! xb! xc! xd! xe! xf! xg! xh! xi! xj! xk! xl! xm! 0n! 0o! 0p! $end #600 19! 1+! #640 0;! #750 1 ptms $end $var wire 1 ? ptrst_n $end $var wire 2 @ ptxd[1:0] $end $var wire 1 A pwait_n $end $var wire 1 B pwak_n $end $var wire 1 C pwe_n $end $var wire 1 D pwrite $end $var wire 1 E pwrst_n $end $var wire 1 F pxak_n $end $var wire 1 G pxin $end $var wire 1 H pxout $end $var wire 1 I pxrq_n $end $upscope $end $scope module dut $end $var wire 1 J pads_pa24_n_2 $end $var wire 1 K pads_pa25_n_2 $end $var wire 1 L pads_pa26_n_2 $end $var wire 1 M pads_pa27_n_2 $end $var wire 1 N pads_pbrk_n_2 $end $var wire 1 O pads_pcrst_n_2 $end $var wire 1 P pads_pcs4_n_2 $end $var wire 1 Q pads_pcs5_n_2 $end $var wire 1 R pads_pcs6_n_2 $end $var wire 1 S pads_pcs7_n_2 $end $var wire 1 T pads_pcts0_n_2 $end $var wire 1 U pads_pcts1_n_2 $end $var wire 1 V pads_pd9_n_2 $end $var wire 1 W pads_pioa0_n_2 $end $var wire 1 X pads_pioa1_n_2 $end $var wire 1 Y pads_pioa2_n_2 $end $var wire 1 Z pads_pioa3_n_2 $end $var wire 1 [ pads_pioa4_n_2 $end $var wire 1 \ pads_pioa5_n_2 $end $var wire 1 ] pads_pioa6_n_2 $end $var wire 1 ^ pads_pioa7_n_2 $end $var wire 1 _ pads_pmiso_n_2 $end $var wire 1 ` pads_pmosi_n_2 $end $var wire 1 a pads_prts0_n_2 $end $var wire 1 b pads_prts1_n_2 $end $var wire 1 c pads_prxd0_n_2 $end $var wire 1 d pads_prxd1_n_2 $end $var wire 1 e pads_psck_n_2 $end $var wire 1 f pads_pscs0_n_2 $end $var wire 1 g pads_pscs1_n_2 $end $var wire 1 h pads_pscs2_n_2 $end $var wire 1 i pads_pscs3_n_2 $end $var wire 1 j pads_ptclk1_n_2 $end $var wire 1 k pads_ptclk2_n_2 $end $var wire 1 l pads_ptdo_n_2 $end $var wire 1 m pads_ptioa0_n_2 $end $var wire 1 n pads_ptioa1_n_2 $end $var wire 1 o pads_ptioa2_n_2 $end $var wire 1 p pads_ptiob0_n_2 $end $var wire 1 q pads_ptiob1_n_2 $end $var wire 1 r pads_ptiob2_n_2 $end $var wire 1 s pads_ptxd0_n_2 $end $var wire 1 t pads_ptxd1_n_2 $end $var wire 1 u pads_puck_n_2 $end $var wire 1 v pads_pxrq_n_2 $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars x* x/ xA xB xE 1G x# x) x1 x3 xC xF xH bxxxxxxxxxxxxxxxxxxxxxxxxxxxx ! x" x$ bxxxxxxxx % bxx & bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ' x( bxxxxxxxx + x, x- x. x0 x2 bxx 4 bxx 5 x6 bxxxx 7 x8 bxxx 9 x: x; bxxx < bxxx = x> x? bxx @ xD xI xs xM x` xJ xh xQ x] xZ xl xW xb xk xt xj xc xV x_ xK xg xP x^ xS x[ xO xX xu xo xd xn xT xm xe xL xf xv xi xR x\ xY xN xr xU xq xa xp $end #15500 0H #100000 1/ 1B 1E 08 0> 0? 0: 1* 1A 1( bxx1 9 #156500 1l #176700 z; #186300 1O #186900 1N #206100 0$ #207400 1" #269800 1v #287700 13 #289900 1W #290200 1\ 1] 1I #290400 1Z 1^ #290500 1[ #290700 1X 1j #291100 1Y #292200 1L #292500 1K 1M #292800 1T #292900 1J #293000 1b bxxxx1xxx1xxxxxxxxxxxxxxxxxxx ! #293900 bxxxx1xx11xxxxxxxxxxxxxxxxxxx ! #294100 bxxxx1x111xxxxxxxxxxxxxxxxxxx ! #294300 1m bxxxx11111xxxxxxxxxxxxxxxxxxx ! #294400 z1 bxxxx1111111xxxxxxxxxxxxxxxxx ! #294700 bxxxx1111111xxxxxx1xxxxxxxxxx ! #294800 bxxxx1111111xxxxxx1xxxxx1xxxx ! #295200 1p #295500 1n #295900 bxxxx1111111xxxxxx1xx1xx1xxxx ! #296000 bxxxx1111111xxxxxx1xx1x11xxxx ! #296400 1r #296500 1, 12 #296600 zC #296900 1U #297000 1u bxxxx1111111xxxxxx1x11x11xxxx ! #297600 bxxxx1111111xxx1xx1x11x11xxxx ! #297700 bxxxx1111111x111xx1x11x11xxxx ! #297800 bxxxx11111111111xx1x11x11xxxx ! #298100 zD #298200 1d #298600 bxxxx11111111111xx1x11111xxxx ! #299000 bxxxx11111111111xx1111111xxxx ! #299100 bxxxx11111111111x111111111xxx ! #299200 1o bxxxx1111111111111111111111xx ! #299300 bxxxx111111111111111111111111 ! #299500 1q #299900 1k 1P #300100 1t #300300 1c #300400 1a #300800 1` #301000 1s #301100 1R 1e #302100 1Q #302200 1S #303500 1_ #310800 bx11 9 #311600 1g 1i #312100 bx1xx111111111111111111111111 ! #312400 bx11x111111111111111111111111 ! #312500 b111x111111111111111111111111 ! #312800 b1111111111111111111111111111 ! #313300 bx1 & #313600 b1x 4 #313900 1h #314000 bxx1 < #315000 bxx1 = #315400 1f #315500 bx11 < #316300 b1x1 = #316900 10 #317000 b11 & #318300 b1x 5 #319000 b111 < #319300 b111 = #319700 bxxx1xxxx % b111 9 #320300 b1x @ b11 5 #320800 1. b11 4 #320900 b11 @ #321000 16 #321300 bx1x1xxxx % #322300 b1111xxxx % #323400 1- #331400 b1x1x 7 #333800 b111x 7 #335300 b1111 7 #348600 bx1xxxxxx + #348700 b11xxxxxx + #348800 b11xxxxx1 + #348900 b11xx1xx1 + #349200 b111x1xx1 + #349700 b11111xx1 + #350000 b111111x1 + #350500 b11111111 + #500000 0G #511600 1H #1000000 1G #1015500 0H #1500000 0G #1511600 1H #2000000 1G #2015500 0H #2071000 0# #2500000 0G #2511600 1H #3000000 1G #3015500 0H #3500000 0G #3511600 1H #4000000 1G #4015500 0H #4092600 b11111xxx % #4093100 b111111xx % #4093400 b111111x1 % #4093600 b11111111 % #4101700 1F #4106400 1) #4500000 0G #4511600 1H #5000000 1G #5015500 0H #5069300 1V #5090600 bxxxxxxxxxzxxxxxxxxxxxxxxxxxxxxxx ' #5090700 bxxxxxxxxxzxxxzxxxxxxxxxxxxxxxxxx ' #5092500 bxxxxxzxxxzxxxzxxxxxxxxxxxxxxxxxx ' #5092800 bxxxxzzxxxzxxxzxxxxxxxxxxxxxxxxxx ' #5094100 bzxxxzzxxxzxxxzxxxxxxxxxxxxxxxxxx ' #5094900 bzxxxzzxzxzxxxzxxxxxxxxxxxxxxxxxx ' #5095800 bzxzxzzxzxzxxxzxxxxxxxxxxxxxxxxxx ' #5096200 bzxzxzzzzxzxxxzxxxxxxxxxxxxxxxxxx ' #5096300 bzxzxzzzzxzxxxzxxxxxxxxxxxxxxxxxz ' #5096500 bzxzzzzzzxzxxxzxxxxxxxxxxxxxxxxxz ' #5096600 bzxzzzzzzxzxxxzxxxxxxxxxxxxxzxxxz ' #5097000 bzxzzzzzzzzzxxzxxxxxxxxxxxxxzxxxz ' #5097200 bzxzzzzzzzzzzzzxxxxxxxxxxxxxzxxxz ' #5097600 bzxzzzzzzzzzzzzxxxxxxxxxxxzxzxxxz ' #5097800 bzzzzzzzzzzzzzzxxxxxxxxxxxzxzxxxz ' #5098100 bzzzzzzzzzzzzzzxxxxxxxxxxxzxzxzxz ' #5098400 bzzzzzzzzzzzzzzxxxxxxxxxxxzxzxzzz ' #5098700 bzzzzzzzzzzzzzzxxxxxxxxxxxzxzzzzz ' #5098900 bzzzzzzzzzzzzzzxxxxxxxxxxxzzzzzzz ' #5099700 bzzzzzzzzzzzzzzxxxxzxxxxxxzzzzzzz ' #5099800 bzzzzzzzzzzzzzzxxxxzxxxxxzzzzzzzz ' #5100200 bzzzzzzzzzzzzzzxxxxzxxxzxzzzzzzzz ' #5100300 bzzzzzzzzzzzzzzxxxxzxxzzxzzzzzzzz ' #5100400 bzzzzzzzzzzzzzzxxxzzxzzzxzzzzzzzz ' #5100600 bzzzzzzzzzzzzzzxxzzzxzzzzzzzzzzzz ' #5100800 bzzzzzzzzzzzzzzxxzzzzzzzzzzzzzzzz ' #5101100 bzzzzzzzzzzzzzzxzzzzzzzzzzzzzzzzz ' #5101200 bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz ' #5500000 0G #5511600 1H #6000000 1G #6015500 0H #6500000 0G #6511600 1H #7000000 1G #7015500 0H #7500000 0G #7511600 1H #8000000 1G #8015500 0H #8100000 1$ #8179700 03 #8500000 0G #8511600 1H #9000000 1G #9015500 0H #9500000 0G #9511600 1H #10000000 1G #10015500 0H #10100000 0* #10500000 0G #10511600 1H #11000000 1G #11015500 0H #11072900 0v #11101500 1I #11102900 b1111011101111111111111111111 ! #11104200 b1111011001111111111111111111 ! #11104400 b1111010001111111111111111111 ! #11104500 b1111010001111111101111111111 ! #11104600 b1111000001111111101111101111 ! #11104700 b1111000000011111101111101111 ! #11106100 b1111000000011111101101101111 ! #11106200 b1111000000011111101101001111 ! #11106300 11 #11106700 02 #11107200 b1111000000011111101001001111 ! #11107700 b1111000000011101101001001111 ! #11107900 b1111000000010001101001001111 ! #11108000 b1111000000000001101001001111 ! #11108700 1C b1111000000000001101000001111 ! #11109100 b1111000000000001100000001111 ! #11109200 b1111000000000001000000000111 ! #11109300 b1111000000000000000000000011 ! #11109400 b1111000000000000000000000000 ! #11109500 1, #11111000 1D #11500000 0G #11511600 1H #12000000 1G #12015500 0H #12070700 1v #12091100 1I #12093900 b1111100010000000000000000000 ! #12094800 b1111100110000000000000000000 ! #12095000 b1111101110000000000000000000 ! #12095200 z1 b1111111110000000000000000000 ! #12095300 b1111111111100000000000000000 ! #12095600 b1111111111100000010000000000 ! #12095700 b1111111111100000010000010000 ! #12096800 b1111111111100000010010010000 ! #12096900 b1111111111100000010010110000 ! #12097300 1, #12097400 zC 12 #12097900 b1111111111100000010110110000 ! #12098500 b1111111111100010010110110000 ! #12098600 b1111111111101110010110110000 ! #12098700 b1111111111111110010110110000 ! #12098900 zD #12099500 b1111111111111110010111110000 ! #12099900 b1111111111111110011111110000 ! #12100000 b1111111111111110111111111000 ! #12100100 b1111111111111111111111111100 ! #12100200 b1111111111111111111111111111 ! #12500000 0G #12511600 1H #13000000 1G #13015500 0H #13103000 0) #13500000 0G #13511600 1H #14000000 1G #14015500 0H #14100000 b1000000000000000000000000000 ! 02 #14500000 0G #14511600 1H #15000000 1G #15015500 0H #15100000 0I #15200000 b00000000000000000000000000000000 ' #15500000 0G #15511600 1H #16000000 1G #16015500 0H #16500000 0G #16511600 1H #17000000 1G #17015500 0H #17101800 0F #17500000 0G #17511600 1H #18000000 1G #18015500 0H #18100000 1I #18200000 b11111111111111111111111111111111 ' #18500000 0G #18511600 1H #19000000 1G #19015500 0H #19099900 1F #19200000 bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz ' #19500000 0G #19511600 1H #20000000 1G #20015500 0H #20100000 12 #20500000 0G #20511600 1H #21000000 1G #21015500 0H #21100000 0I #21500000 0G #21511600 1H #22000000 1G #22015500 0H #22500000 0G #22511600 1H #23000000 1G #23015500 0H #23072900 0V #23101800 0F #23102400 bzzzzzzzzz0zzzzzzzzzzzzzzzzzzzzzz ' #23103700 bzzzz0zzzz0zzzzzzzzzzzzzzzzzzzzzz ' #23104300 b0zzz0zzzz0zzzzzzzzzzzzzzzzzzzzzz ' #23104500 b0zzz00zzz0zzzzzzzzzzzzzzzzzzzzzz ' #23105500 b0zzz00z0z0zzz0zzzzzzzzzzzzzzzzzz ' #23106800 b0zzz0000z0zzz0zzzzzzzzzzzzzzzzz0 ' #23107000 b0zz00000z0zzz0zzzzzzzzzzzzz0zzz0 ' #23107500 b0z000000z0zzz0zzzzzzzzzzzzz0zzz0 ' #23107700 b0z000000000zz0zzzzzzzzzzzzz0zzz0 ' #23108000 b0z000000000z00zzzzzzzzzzz0z0zzz0 ' #23108100 b0z000000000000zzzzzzzzzzz0z0zzz0 ' #23108600 b00000000000000zzzzzzzzzzz0z0z0z0 ' #23109100 b00000000000000zzzzzzzzzzz0z0z000 ' #23109300 b00000000000000zzzzzzzzzzz0z00000 ' #23109600 b00000000000000zzzzzzzzzzz0000000 ' #23110200 b00000000000000zzzz0zzzzzz0000000 ' #23110600 b00000000000000zzzz0zzz0z00000000 ' #23110700 b00000000000000zzzz0zz00z00000000 ' #23110800 b00000000000000zzzz0z000z00000000 ' #23111000 b00000000000000zz0z0z000z00000000 ' #23111100 b00000000000000zz000z000z00000000 ' #23111300 b00000000000000zz000z000000000000 ' #23111600 b00000000000000z00000000000000000 ' #23111800 b00000000000000000000000000000000 ' #23500000 0G #23511600 1H #24000000 1G #24015500 0H #24100000 1I #24500000 0G #24511600 1H #25000000 1G #25015500 0H #25075300 1V #25096600 b000000000z0000000000000000000000 ' #25096700 b000000000z000z000000000000000000 ' #25098500 b00000z000z000z000000000000000000 ' #25098800 b0000zz000z000z000000000000000000 ' #25099900 1F #25100100 bz000zz000z000z000000000000000000 ' #25100900 bz000zz0z0z000z000000000000000000 ' #25101800 bz0z0zz0z0z000z000000000000000000 ' #25102200 bz0z0zzzz0z000z000000000000000000 ' #25102300 bz0z0zzzz0z000z00000000000000000z ' #25102500 bz0zzzzzz0z000z00000000000000000z ' #25102600 bz0zzzzzz0z000z0000000000000z000z ' #25103000 bz0zzzzzzzzz00z0000000000000z000z ' #25103200 bz0zzzzzzzzzzzz0000000000000z000z ' #25103600 bz0zzzzzzzzzzzz00000000000z0z000z ' #25103800 bzzzzzzzzzzzzzz00000000000z0z000z ' #25104100 bzzzzzzzzzzzzzz00000000000z0z0z0z ' #25104400 bzzzzzzzzzzzzzz00000000000z0z0zzz ' #25104700 bzzzzzzzzzzzzzz00000000000z0zzzzz ' #25104900 bzzzzzzzzzzzzzz00000000000zzzzzzz ' #25105700 bzzzzzzzzzzzzzz0000z000000zzzzzzz ' #25105800 bzzzzzzzzzzzzzz0000z00000zzzzzzzz ' #25106200 bzzzzzzzzzzzzzz0000z000z0zzzzzzzz ' #25106300 bzzzzzzzzzzzzzz0000z00zz0zzzzzzzz ' #25106400 bzzzzzzzzzzzzzz000zz0zzz0zzzzzzzz ' #25106600 bzzzzzzzzzzzzzz00zzz0zzzzzzzzzzzz ' #25106800 bzzzzzzzzzzzzzz00zzzzzzzzzzzzzzzz ' #25107100 bzzzzzzzzzzzzzz0zzzzzzzzzzzzzzzzz ' #25107200 bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz ' #25500000 0G #25511600 1H #26000000 1G #26015500 0H #26100000 1* #26500000 0G #26511600 1H #27000000 1G #27015500 0H #27500000 0G #27511600 1H #28000000 1G #28015500 0H #28100000 12 b1111111111111111111111111111 ! 1I #28106400 1) #28500000 0G #28511600 1H #29000000 1G #29015500 0H #29068600 0v #29097200 1I #29098600 b1111011101111111111111111111 ! #29099900 b1111011001111111111111111111 ! #29100000 0$ #29100100 b1111010001111111111111111111 ! #29100200 b1111010001111111101111111111 ! #29100300 b1111000001111111101111101111 ! #29100400 b1111000000011111101111101111 ! #29101800 b1111000000011111101101101111 ! #29101900 b1111000000011111101101001111 ! #29102000 11 #29102900 b1111000000011111101001001111 ! #29103400 b1111000000011101101001001111 ! #29103600 b1111000000010001101001001111 ! #29103700 web1: {20} _2 $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars x* x/ xA xB xE 1G x# x) x1 x3 xC xF xH bxxxxxxxxxxxxxxxxxxxxxxxxxxxx ! x" x$ bxxxxxxxx % bxx & bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ' x( bxxxxxxxx + x, x-INTERFACES/WGL/VCDWGL/exp3.vcd000064400001440000012000000041261103104161000163130ustar00jcosleystaff00000400000023$date Mon Mar 26 10:21:05 2007 $end $version VERILOG-XL 1.6.0.1 $end $timescale 1 ns $end $scope module integrity $end $var reg 1 ! CCVREF $end $var reg 1 " GCLKIN $end $var reg 1 # HCLKINN $end $var reg 1 $ HCLKINP $end $var reg 1 % HLREF $end $var reg 1 & RSTINB $end $var wire 4 ' GCBEB [0:3] $end $upscope $end $enddefinitions $end $dumpvars bX ' X! 0" X# 0$ X% 0& $end #1 Z# #2 Z! Z% #25 1$ #45 0$ #55 1$ #80 0$ #125 1$ #145 0$ #155 1$ #180 0$ #201 1# #202 1% #220 Z" #225 1$ #235 0" #240 Z" #245 0$ #255 1$ #265 0" #280 0$ #315 1$ #335 0$ #340 1$ #350 Z" #360 0$ #365 0" #390 Z" #435 0" #520 Z" #525 1$ #535 0" #540 Z" #545 0$ #555 1$ #565 0" #580 0$ #615 1$ #635 0$ #640 1$ #650 Z" #660 0$ #665 0" #690 Z" #735 0" #810 1" #815 1$ #825 0" #835 0$ #840 1" 1$ #860 0$ #865 0" #900 Z" #905 1$ #915 0" #920 Z" #925 0$ #935 1$ #945 0" #960 0$ #1000 Z" #1005 1$ #1015 0" #1020 Z" #1025 0$ #1035 1$ #1045 0" #1060 0$ #1085 1! #1095 1$ #1115 0$ #1120 1$ #1140 0$ #1285 0! #1295 1$ #1315 0$ #1320 1$ #1340 0$ #1495 1$ #1515 0$ #1520 1$ #1530 1" #1540 0$ #1545 0" #1570 1" #1615 0" #1685 1! #1695 1$ #1715 0$ #1720 1$ #1730 1" #1740 0$ #1745 0" #1770 1" #1815 0" #1884 0# #1890 1" #1895 1$ #1905 0" #1915 0$ #1920 1" 1$ #1940 0$ #1945 0" #1961 0! #1964 1# #1970 1" #1975 1$ #1985 0" #1995 0$ #2000 1" 1$ #2020 0$ #2025 0" #2044 0# #2050 1" #2055 1$ #2065 0" #2075 0$ #2080 1" 1$ #2100 0$ #2105 0" #2121 1! #2124 1# #2130 1" #2135 1$ #2145 0" #2155 0$ #2160 1" 1$ #2180 0$ #2185 0" #2204 0# #2210 1" #2215 1$ #2225 0" #2235 0$ #2240 1" 1$ #2260 0$ #2265 0" #2281 0! #2284 1# #2290 1" #2295 1$ #2305 0" #2315 0$ #2320 1" 1$ #2340 0$ #2345 0" #2364 0# #2370 1" #2375 1$ #2385 0" #2395 0$ #2400 1" 1$ #2420 0$ #2425 0" #2441 1! #2444 1# #2450 1" #2455 1$ #2465 0" #2475 0$ #2480 1" 1$ #2500 0$ #2505 0" #2520 0# #2530 1" #2535 1$ #2545 0" #2555 0$ #2560 1" 1$ #2580 0$ #2585 0" #2600 0! 1# #2610 1" #2615 1$ #2625 0" #2635 0$ #2640 1" 1$ #2660 0$ #2665 0" #2684 0# #2695 1$ #2715 0$ #2720 1$ #2730 1" #2740 0$ #2745 0" #2770 1" #2815 0" #2881 1! #2884 1# #2890 1" #2895 1$ #2905 0" #2915 0$ #2920 1" 1$ #2940 0$ #2945 0" INTERFACES/WGL/VCDWGL/exp3.vtran000064400001440000012000000023511103104161000166670ustar00jcosleystaff00000400000023 ovf_block begin orig_file exp3.vcd ; script_format verilog_vcd ; INPUTS CCVREF GCLKIN HCLKINN HCLKINP HLREF RSTINB ; OUTPUTS GCBEB[0] GCBEB[1] GCBEB[2] GCBEB[3] ; end proc_block begin TEMPLATE_CYCLIZATION TERMINATE_ON_DEFAULTS = "100" MATCH_REPORT = "match.rpt", MATCH_TRACE_START = 1, MATCH_TRACE_STOP = 99; TIMESET tp1 -DEFAULT CYCLE = 100; PINTYPE NRZ * @ 2; PINTYPE -PRIMARY RZ2X GCLKIN @ 20, 35, 40, 65; PINTYPE -PRIMARY RZ2X HCLKINP @ 25, 45, 55, 80; PINTYPE STB * @ 35 ; SELECT_RANGE 0.0 300.0; SELECT_RANGE 500.0 700.0; ENDTIMESET; TIMESET tp2 WEIGHT 3; CYCLE = 80; SAMPLE_POINT CCVREF, RSTINB, HCLKINN, HLREF @ 5; PINTYPE NRZ * @ 0; PINTYPE RZ2X GCLKIN @ 10, 25, 40, 65; PINTYPE RZ2X HCLKINP @ 15, 35, 40, 60; PINTYPE STB * @ 25 ; IDENTIFIER (GCLKIN=1)&(RSTINB=0); SELECT_RANGE 1880.0 2680.0; ENDTIMESET; TIMESET tp3 CYCLE = 200; PINTYPE NRZ * @ 4; SAMPLE_POINT CCVREF @ 5.1; PINTYPE -PRIMARY RZ2X HCLKINP @ 15, 35, 40, 60; PINTYPE -PRIMARY RZ2X GCLKIN @ 50, 65, 90, 135; PINTYPE STB GCBEB[0], GCBEB[1] @ 95 ; PINTYPE STB GCBEB[2], GCBEB[3] @ 25 ; ENDTIMESET; end tvf_block begin resolution 0.1; target_file exp3.wgl; simulator wgl; end end INTERFACES/WGL/STILWGL/000075500001440000012000000000001127637177700151315ustar00jcosleystaff00000400000023INTERFACES/WGL/STILWGL/exp1.vtran000064400001440000012000000051451103104161000170300ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > WGL # # Original File: "exp1.stil" # # Target File: "exp1.wgl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -expand_loops -expand_reps ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into WGL format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'WGL'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp1.wgl"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/WGL/STILWGL/exp2.vtran000064400001440000012000000050011103104161000170200ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > WGL # # Original File: "exp1.stil" # # Target File: "exp2.wgl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into WGL format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'WGL'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp2.wgl"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/WGL/STILWGL/exp3.vtran000064400001440000012000000050071103104161000170270ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: STIL < to > WGL # # Original File: "exp1.stil" # # Target File: "exp3.wgl " # # Command File: "exp3.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin tabular_format stil -cycle -scan ; {#### INPUT FORMAT ####} orig_file = "../../DATA/exp1.stil" ; {#### INPUT VECTOR FILE ####} end; { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the STIL # # vector data to translate into WGL format # #======================================================================# } proc_block begin { #### state character translations for 'STIL'->'WGL'#### } state_trans inputs 'D'->'0', 'U'->'1', '?'->'X'; state_trans outputs 'T'->'X', 'x'->'X', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 't'->'X', 'R'->'0', 'G'->'1', 'Q'->'X'; end; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp3.wgl"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/WGL/EVCDWGL/000075500001440000012000000000001103104161000150405ustar00jcosleystaff00000400000023INTERFACES/WGL/EVCDWGL/exp1.vtran000064400001440000012000000101471133335674400170220ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > WGL # # Original File: "exp1.evcd" # # Target File: "exp1.wgl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into WGL format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'WGL'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; {#### timing info ####} cycle 20 align_to_cycle 20 * @ 12, mclk @ 18, ma[6] @ 20, ma[7] @ 20; pintype nrz * @ 5; pintype stb * @ 18; pintype rz clki @ 10, 20; pintype nrz ma[6], ma[7] @ 19; end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp1.wgl"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/WGL/EVCDWGL/exp2.vtran000064400001440000012000000076221133335722300170200ustar00jcosleystaff00000400000023{ #======================================================================# # This is vtran command file. # # Translation: EVCD < to > WGL # # Original File: "exp1.evcd" # # Target File: "exp2.wgl " # # Command File: "exp2.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block begin orig_file "../../DATA/exp1.evcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} { bidirects clki clk2x vcxo_ctrl bclko test bopt devid[3:0] dsp_only hrst_ had[31:0] hc13 hc11 hc9_0[9:0] fa22 fa23 uart_rx uart_tx usbp usbn em1_tx_clk em1_txd[3:0] em1_tx_en em1_txer em1_crs em1_col em1_rx_clk em1_rxd[3:0] em1_rxdv em1_rxer em1_mdc em1_mdio md[15:0] ma[12:0] mb[1:0] mm[1:0] mras_ mcas_ mwe_ mcs_[1:0] mcke mclk gpio42_40[42:40] gpio38 gpio33 gpio26 gpio25 gpio22_13[22:13] gpio8_5[8:5] gpio3 gpio2 gpio1 trst_ tck tms tdi tdo afetx0 aferx0 aferx1 fafe_sclk fafe_stb fafe_ctrlin fafe_ctrlout mon_done mon_clk mon_out vregenn vddo vsso pllvdd pllvss regvdd regvss ; } end { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the EVCD # # vector data to translate into WGL format # #======================================================================# } proc_block begin { #### state character translations for 'EVCD'->'WGL'#### } STATE_TRANS pure_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X', 'f'->'Z', 'F'->'Z'; STATE_TRANS pure_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', 'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; STATE_TRANS bidir_inputs 'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1', '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X', 'c'->'X'; STATE_TRANS bidir_outputs 'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X', '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0', 'c'->'1', 'f'->'Z', 'F'->'X'; {#### timing info ####} Include "../../DATA/exp2.tcyc" end { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN delete_pins vddo vsso pllvdd pllvss regvdd regvss; SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp2.wgl"; {#### OUTPUT VECTOR FILE ####} END; INTERFACES/WGL/README000064400001440000012000000277351103104161000146430ustar00jcosleystaff00000400000023WGL -------- The main directory is "WGL" and the sub-directories are -> STILWGL -> VCDWGL -> EVCDWGL The sub-directories are named to represent the translation invoked by them. For example: Sub-directory -> "STILWGL" contains the translation of STIL file to WGL output format. Sub-directory -> "EVCDWGL" contains the translation of EVCD file to WGL output format. The example translations in the sub-directory can be run by typing: vtran expn.vtran where n=1,2................... Since there are a number of examples using the WGL reader (to translate from WGL files to other formats) in the other INTERFACES directories, this section focuses on the WGL writer. The current WGL writer parameters include: SIMULATOR WGL, -FORCE_SPACES, { forces space between bus states in vec file } -QUOTE_NAMES, { all signal names are quoted in WGL file } -SEPARATE_BIDIRECTS, { modifies pattern listing for bidirects } -edge_format1, { modifies syntax on edge timing } NUMBERS = "ON" | "OFF", { causes vector lines to be numbered - OFF default } AddressElement = "Plus", { adds "+" to address of vector statements } AddressElement = "CycleNumber", { adds cycle number to address of } { vector statements } AddressElement = "Time", { adds time stamp to address of } { vector statements } UNITS = "ps" { specify time units - default is ns } ; For example, SIMULATOR WGL AddressElement = "Plus"; would produce vector lines that look like, vector(+, TEST_tp) := [ ..... and SIMULATOR WGL AddressElement = "Time"; would produce vector lines that look like, vector(23400nS, TEST_tp) := [ ..... When translating flat simulation data files, such as Verilog VCD files, to the cycle-based WGL format, the vtran command file must include commands which define or perform the following: IN THE OVF_BLOCK: 1) The signal names and their directions (INPUTS, OUTPUTS or BIDIRECTS). IN THE PROC_BLOCK: 2) State translations as needed using STATE_TRANS - see examples. 3) Bidirectional data separation using BIDIRECT_CONTROL statements and control pin expressions - state data in the VCD file for bidirectional pins is merged together so we must separate it between input and output data for the WGL file. 4) CYCLE time - needed to define the cycle-time of the vectors in the target WGL file. 5) Strobe (sample) times for signals to determine their state in each cycle. This can be done with either an ALIGN_TO_STEP command (which will sample all pins at one time in the cycle) or the ALIGN_TO_CYCLE command (which allows you to specify different sample times in the cycles for different pins). If there are multiple timsets in the vector data, use the TEMPLATE_CYCLIZATION feature for cyclizing. 6) Timing for the WGL file - use the PINTYPE commands, along with the SEPARATE_TIMING command. An example command file for an VCD -> WGL translation would look like: { #======================================================================# # This is vtran command file. # # Translation: VCD < to > WGL # # Original File: "exp1.vcd" # # Target File: "exp1.wgl " # # Command File: "exp1.vtran" # # Reference File:"Readme.txt" # # Author: SOURCE III, Inc. # # VTRAN 7.1.1 (C) 2004 Source III, Inc. # #======================================================================# } { #======================================================================# # ORIGINAL VECTOR FILE- BLOCK # # This block provides information about the input file and # # input format. # #======================================================================# } ovf_block BEGIN orig_file = "exp1.vcd"; {#### INPUT VECTOR FILE ####} script_format verilog_vcd; {#### INPUT FORMAT ####} {#### INPUT/OUTPUT PIN DESCRIPTION ####} INPUTS rstn scan_en_n test_en_n clkin clk_ratio hclkin hcs_n; BIDIRECTS has_n hwr hwait_n hrdy_n hblast hhold hholda ; INPUTS harb hboff; BIDIRECTS hbe_n[3] hbe_n[2] hbe_n[1] hbe_n[0] hd[31] hd[30] hd[29] hd[28] hd[27] hd[26] hd[25] hd[24] hd[23] hd[22] hd[21] hd[20] hd[19] hd[18] hd[17] hd[16] hd[15] hd[14] hd[13] hd[12] hd[11] hd[10] hd[9] hd[8] hd[7] hd[6] hd[5] hd[4] hd[3] hd[2] hd[1] hd[0] ; BIDIRECTS srck0 srfs0 ; INPUTS srd0; BIDIRECTS srck1 srfs1 ; INPUTS srd1; BIDIRECTS srck2 srfs2 ; INPUTS srd2; BIDIRECTS srck3 srfs3 ; INPUTS srd3; BIDIRECTS stck0 stfs0 std0 stck1 stfs1 std1 stck2 stfs2 std2 stck3 stfs3 std3 gpio[15] gpio[14] gpio[13] gpio[12] gpio[11] gpio[10] gpio[9] gpio[8] gpio[7] gpio[6] gpio[5] gpio[4] gpio[3] gpio[2] gpio[1] gpio[0]; INPUTS jtsel lx_bisten pjclk pjrstb pjms pjdi; BIDIRECTS pjdo; INPUTS ljclk ljrstb ljms ljdi; BIDIRECTS ljdo; INPUTS ej_rst_n; BIDIRECTS {actually tri-state output pins } ejtag[2] ejtag[1] ejtag[0] ej_dclk; INPUTS pll_rstn pll_oe pll_bp pll_pd pll_sel[2] pll_sel[1] pll_sel[0]; BIDIRECTS pll_clkout; INPUTS dm_sel[5] dm_sel[4] dm_sel[3] dm_sel[2] dm_sel[1] dm_sel[0] tm_dsp tm_hi tm_sb ; INPUTS { actually control pins for bidirs } pad_ej_outen pad_gpio_outen[0] pad_gpio_outen[1] pad_gpio_outen[10] pad_gpio_outen[11] pad_gpio_outen[12] pad_gpio_outen[13] pad_gpio_outen[14] pad_gpio_outen[15] pad_gpio_outen[2] pad_gpio_outen[3] pad_gpio_outen[4] pad_gpio_outen[5] pad_gpio_outen[6] pad_gpio_outen[7] pad_gpio_outen[8] pad_gpio_outen[9] pad_has_n_outen pad_hbe_n_outen pad_hblast_outen pad_hd_outen_d pad_hd_outen_z pad_hhold_outen pad_hholda_outen pad_hrdy_n_outen pad_hwait_n_outen pad_hwr_outen pad_ljdo_outen pad_pjdo_outen pad_pll_clkout_outen pad_sck_outen[0] pad_sck_outen[1] pad_sck_outen[2] pad_sck_outen[3] pad_sck_outen[4] pad_sck_outen[5] pad_sck_outen[6] pad_sck_outen[7] pad_sfs_outen[0] pad_sfs_outen[1] pad_sfs_outen[2] pad_sfs_outen[3] pad_sfs_outen[4] pad_sfs_outen[5] pad_sfs_outen[6] pad_sfs_outen[7] pad_sxd_outen[0] pad_sxd_outen[1] pad_sxd_outen[2] pad_sxd_outen[3]; END: { #======================================================================# # PROCESSING- BLOCK # # The Processing block does necessary processing on the VCD # # vector data to translate into WGL format # #======================================================================# } proc_block BEGIN add_pin CLK = 1; disable_vector_filter; { #### state character translations for 'VCD'->'WGL'#### } STATE_TRANS inputs 'x'->'X', 'z'->'X' ; STATE_TRANS outputs 'x'->'Z', 'z'->'Z' ; { #### Collapse to 6 ns cycle, strobing pins as specified #### } cycle 6; align_to_cycle 6 PURE_INPUTS @ 1, BIDIR_INPUTS @ 3, BIDIR_OUTPUTS @ 2 ; { #### Separate bidirectional data using control pins #### } bidirect_control hd[31:0] = output when pad_hd_outen_d = 0; bidirect_control has_n = output when pad_has_n_outen = 0; bidirect_control hblast = output when pad_hblast_outen = 0; bidirect_control hwr = output when pad_hwr_outen = 0; bidirect_control hbe_n[3:0] = output when pad_hbe_n_outen = 0; bidirect_control hhold = output when pad_hhold_outen = 0; bidirect_control hholda = output when pad_hholda_outen = 0; bidirect_control hrdy_n = output when pad_hrdy_n_outen = 0; bidirect_control hwait_n = output when pad_hwait_n_outen = 0; bidirect_control srck0 = output when pad_sck_outen[0] = 0; bidirect_control srck1 = output when pad_sck_outen[1] = 0; bidirect_control srck2 = output when pad_sck_outen[2] = 0; bidirect_control srck3 = output when pad_sck_outen[3] = 0; bidirect_control stck0 = output when pad_sck_outen[4] = 0; bidirect_control stck1 = output when pad_sck_outen[5] = 0; bidirect_control stck2 = output when pad_sck_outen[6] = 0; bidirect_control stck3 = output when pad_sck_outen[7] = 0; bidirect_control srfs0 = output when pad_sfs_outen[0] = 0; bidirect_control srfs1 = output when pad_sfs_outen[1] = 0; bidirect_control srfs2 = output when pad_sfs_outen[2] = 0; bidirect_control srfs3 = output when pad_sfs_outen[3] = 0; bidirect_control stfs0 = output when pad_sfs_outen[4] = 0; bidirect_control stfs1 = output when pad_sfs_outen[5] = 0; bidirect_control stfs2 = output when pad_sfs_outen[6] = 0; bidirect_control stfs3 = output when pad_sfs_outen[7] = 0; bidirect_control std0 = output when pad_sxd_outen[0] = 0; bidirect_control std1 = output when pad_sxd_outen[1] = 0; bidirect_control std2 = output when pad_sxd_outen[2] = 0; bidirect_control std3 = output when pad_sxd_outen[3] = 0; bidirect_control gpio[15] = output when pad_gpio_outen[15] = 0; bidirect_control gpio[14] = output when pad_gpio_outen[14] = 0; bidirect_control gpio[13] = output when pad_gpio_outen[13] = 0; bidirect_control gpio[12] = output when pad_gpio_outen[12] = 0; bidirect_control gpio[11] = output when pad_gpio_outen[11] = 0; bidirect_control gpio[10] = output when pad_gpio_outen[10] = 0; bidirect_control gpio[9] = output when pad_gpio_outen[9] = 0; bidirect_control gpio[8] = output when pad_gpio_outen[8] = 0; bidirect_control gpio[7] = output when pad_gpio_outen[7] = 0; bidirect_control gpio[6] = output when pad_gpio_outen[6] = 0; bidirect_control gpio[5] = output when pad_gpio_outen[5] = 0; bidirect_control gpio[4] = output when pad_gpio_outen[4] = 0; bidirect_control gpio[3] = output when pad_gpio_outen[3] = 0; bidirect_control gpio[2] = output when pad_gpio_outen[2] = 0; bidirect_control gpio[1] = output when pad_gpio_outen[1] = 0; bidirect_control gpio[0] = output when pad_gpio_outen[0] = 0; bidirect_control pjdo = output when pad_pjdo_outen = 0; bidirect_control ljdo = output when pad_ljdo_outen = 0; bidirect_control ejtag[2] = output when pad_ej_outen = 0; bidirect_control ejtag[1] = output when pad_ej_outen = 0; bidirect_control ejtag[0] = output when pad_ej_outen = 0; bidirect_control ej_dclk = output when pad_ej_outen = 0; bidirect_control pll_clkout = output when pad_pll_clkout_outen = 0; { #### define some timing for the WGL file #### } PINTYPE NRZ * @ 2; { #### drive all inputs at 2 #### } PINTYPE STB * @ 5; { #### strobe all outputs at 5 #### } PINTYPE RZ clkin @ 1, 4; { #### clock pin behavior #### } pintype RZ2X CLK @ 0, 50, 125, 200; SEPARATE_TIMING; END; { #======================================================================# # TARGET VECTOR FILE-BLOCK # # This block contains information about the output format and # # other optional parameters. # #======================================================================# } tvf_block BEGIN DELETE_PINS { #### These are the control pins #### } pad_ej_outen pad_gpio_outen[0] pad_gpio_outen[1] pad_gpio_outen[10] pad_gpio_outen[11] pad_gpio_outen[12] pad_gpio_outen[13] pad_gpio_outen[14] pad_gpio_outen[15] pad_gpio_outen[2] pad_gpio_outen[3] pad_gpio_outen[4] pad_gpio_outen[5] pad_gpio_outen[6] pad_gpio_outen[7] pad_gpio_outen[8] pad_gpio_outen[9] pad_has_n_outen pad_hbe_n_outen pad_hblast_outen pad_hd_outen_d pad_hd_outen_z pad_hhold_outen pad_hholda_outen pad_hrdy_n_outen pad_hwait_n_outen pad_hwr_outen pad_ljdo_outen pad_pjdo_outen pad_pll_clkout_outen pad_sck_outen[0] pad_sck_outen[1] pad_sck_outen[2] pad_sck_outen[3] pad_sck_outen[4] pad_sck_outen[5] pad_sck_outen[6] pad_sck_outen[7] pad_sfs_outen[0] pad_sfs_outen[1] pad_sfs_outen[2] pad_sfs_outen[3] pad_sfs_outen[4] pad_sfs_outen[5] pad_sfs_outen[6] pad_sfs_outen[7] pad_sxd_outen[0] pad_sxd_outen[1] pad_sxd_outen[2] pad_sxd_outen[3]; SIMULATOR WGL {#### OUTPUT FORMAT ####} -QUOTE_NAMES, {##### quote pin names in WGL file ##### } AddressElement = "CycleNumber"; { #### add cycle num to vector addresses #### } TARGET_FILE = "exp1.wgl"; {#### OUTPUT VECTOR FILE ####} END; ################################################################################ 3) Bidirectional data separation usINTERFACES/TEMPLATE_CYCL.spec000064400001440000012000000454061103104161000162260ustar00jcosleystaff00000400000023/* * * *********************************************************** * ** ** * ** Copyright (C) 2008, Source III, Inc. ** * ** ** * *********************************************************** * */ VTRAN TEMPLATE CYCLIZATION FEATURE Specification March 21, 2008 In versions through Release 6.1, vtran has provided the capability to read print-on-change (POC) vector data (such as from VCD files) and cyclize it for cycle-based formats (such as WGL, STIL, and numerous testers). This cyclization process is performed by one of two general methods whereby the user specifies the signal timing necessary for the work. The first method uses one of the ALIGN processes available in vtran - ALIGN_TO_CYCLE, ALIGN_TO_STEP or ALIGN_TO_SIGNAL. For these, the user essentially tells vtran the cycle time for the cyclization, and where within each cycle to sample each signal's data. If there is a need for timing information to be specified in the output file format, then the PINTYPE commands can be used to provide it. The second method is to specify the timing which is contained in the input POC file using these same PINTYPE statements, and then add an AUTO_ALIGN statement. This will cause vtran to calculate the sample points for the cyclization based on this specified signal timing and behavior. In both of the cyclization approaches described above, note that there is only a single set of timing, or TIMESET, which can be specified and applied. For some applications, this limitation is unacceptable. The TEMPLATE CYCLIZATION feature in vtran allows the user to specify a number of TIMESETs that are included in the POC vector data, and then perform cyclization on the data by matching the different TIMESET waveforms with the waveforms found in the POC data. Using this feature, for example, vtran can cyclize a VCD file that included several different cycle types (with different cycle times and signal timing) such as say a scan_cycle, a capture_cycle and a run_cycle. A special mode, described below, also allows for the assignment of multiple TIMESETs to cyclized vectors. The TEMPLATE CYCLIZATION feature is invoked in the PROC_BLOCK by specifying a TEMPLATE_CYCLIZATION command along with one or more TIMESETs in the vtran command file. TIMESETs are blocks of statements which specify a cycle time (CYCLE command) and the signal behavior/timing (using PINTYPE commands). When used in the TIMESET block, PINTYPE statements can have a -PRIMARY flag included which tells vtran that this is a signal to use for cycle matching. A second flag, -ACTIVE_ONLY, can be specified for -PRIMARY signals to indicate that a match is allowed only when the signal (normally a RZ or RO clock) is active. Without this flag, a clock can be matched either actively (when a pulse is present) or passively (when no pulsing is present). In addition, an IDENTIFIER statement can be included to provide logical information that can be used as an alternative to the -PRIMARY flags (or in conjunction with them) during the cycle identification process. **Note** that the logic state values used in the IDENTIFIER statements are those state characters coming directly from the file being read (the ORIG_FILE), prior to any STATE_TRANS mappings that might be specified. These states are those sampled during each cycle according to the PINTYPE timing specified for each signal, or according to a specific sample point specified by a SAMPLE_POINT statement - both are discussed below. In order to provide further guidance to the cyclization process, a WEIGHT parameter can be specified for each TIMESET which will be used to resolve cycles where more than one TIMESET has a match. Typical TEMPLATE_CYCLIZATION statement and TIMESET blocks might look like: PROC_BLOCK BEGIN . . . . TEMPLATE_CYCLIZATION CYCLIZATION_SKEW = "0.5" , TERMINATE_ON_DEFAULTS = "20", MATCH_REPORT = "designfile.rpt", MATCH_TRACE_START = 1 ; MATCH_TRACE_STOP = 8 ; VIEW_OUTPUT = "designfile.view" ; TIMESET SCAN_SHIFT CYCLE 3.2; PINTYPE NRZ * @ 0.5, 0.1; PINTYPE -PRIMARY RZ cpref_clk @ 1.0, 2.0; PINTYPE STB * @ 3.0, 3.1; IDENTIFIER (scan_load=1)&(scan_enb=1) ; ENDTIMESET; TIMESET CAPTURE CYCLE 6.4; PINTYPE NRZ * @ .8, .1; PINTYPE -PRIMARY RZ cpref_clk @ 2.0, 4.5; PINTYPE -PRIMARY -ACTIVE_ONLY RO ubf_clk @ 1.5, 4.8; PINTYPE STB * @ 6.1, 6.2; IDENTIFIER (scan_load=0)&(scan_enb=1) ; ENDTIMESET; TIMESET RUN CYCLE 4.0; WEIGHT 1 ; SAMPLE_POINT all_inputs @ 2.5; PINTYPE NRZ * @ .4, .1; PINTYPE -PRIMARY RZ cpref_clk @ 2.0, 3.0; PINTYPE -PRIMARY RO ubf_clk @ 1.0, 3.2; PINTYPE STB * @ 3.5, 3.6; IDENTIFIER scan_enb = 0 ; ENDTIMESET; TIMESET DUMMY -DEFAULT CYCLE 4.0; SAMPLE_POINT cpref_clk @ 1.5; PINTYPE NRZ * @ .4, .1; PINTYPE RZ cpref_clk @ 2.0, 3.0; PINTYPE RO ubf_clk @ 1.0, 3.2; PINTYPE STB * @ 3.1, 3.2; ENDTIMESET; TEMPLATE_CYCLIZATION STATEMENT ------------------------------ The TEMPLATE_CYCLIZATION statement initializes the cyclization process and sets up some user options. The first option is CYCLIZATION_SKEW. This parameter allows the user to specify a SKEW tolerance to be used during waveform matching. If this parameter is not specified, the tolerance defaults to .5 fs (very small). Setting it to 0.5ns, as in the example above, means that -PRIMARY signal edges can make a transition within +-0.5ns of the PINTYPE timing specified and still be considered as a match. The TERMINATE_ON_DEFAULTS parameter will cause the cyclization process to terminate when the specified number of -DEFAULT cycles are used. This can be used as a way to flag the user that the criteria specified for matching cycles (-PRIMARY and IDENTIFIER) are inadequate, since they are obviously unable to uniquely match all of the cycle waveforms encountered. Each time there is a -DEFAULT cycle used (because all of the TIMESETS were MISMATCHes), a warning is sent to the screen (stderr). Setting this parameter to -1 will disable the TERMINATE_ON_DEFAULTS action as well as the printing of the warning. The MATCH_REPORT parameter specifies a file name and directs vtran to place cycle matching statistics in this file. This can be useful in debugging the cyclization process and adjusting the matching criteria. When a MATCH_REPORT parameter is specified, a trace of the MATCH activity on a cycle-by-cycle basis can be recorded in the file using the MATCH_TRACE statements. The syntax for these is: MATCH_TRACE_START = nn ; MATCH_TRACE_STOP = mm ; Where nn and mm are the cycle numbers for starting and stoping the trace. The final optional parameter is VIEW_OUTPUT. This also specifies a file name and directs vtran to produce a flat, viewable waveform set of POC data in this file. The flattening takes place directly on the cyclized data and the current default format of this data is Verilog VCD format. This is intended as a way to view and compare the post-cyclization data with the original input POC data - again to help in debugging and verifying that the cyclized data accurately reflects the initial input data. In one possible scenario, another Source III product, vcap, can be used to check the original POC input file with this flattened version of the cyclized data and verify that they are the same, and hence that the cyclization process was successful. The VIEW_OUTPUT feature will not be available in the initial product release. CYCLE MATCHING -------------- In a given TIMESET, if multiple signals have a -PRIMARY flag set in their PINTYPE statements, then they become a logical AND operation from a cycle matching perspective. Only one INDENTIFIER is allowed per TIMESET, but it can contain an arbitrarily complex logical expression. TIMESETS which contain both -PRIMARY flags and an INDETIFIER statement will attempt cycle matching using a logical AND of all the conditions. If more than one TIMESET template matches a sequence of vectors from a POC file, then the WEIGHT parameter can be used to decide the successful match. If no WEIGHT is specified, then it is 0 for that TIMESET. If none of the TIMESET templates match the waveforms in a set of POC vector data, then the TIMESET with the -DEFAULT flag is used for cyclization. If there is no -DEFAULT TIMESET, then the first TIMESET specified becomes the default. The cycle-matching algorithms used by vtran have several levels. The basic methodology incorporates an accumulated score which is computed from evaluating a cycle's worth of vector data against the waveforms of -PRIMARY signals and any IDENTIFIER logic expression that may be present. Since the overall match status is the logical AND of all of these, if any -PRIMARY or IDENTIFIER is a MISMATCH, then the entire TIMESET is considered a MISMATCH. Initially one cycle's worth of vector data for each TIMESET is accumulated. All TIMESETS are assumed to be potential matches if they have at least one -PRIMARY or an IDENTIFIER specified. These begin with a score of 1. The program then goes thru the -PRIMARY tagged waveforms of these TIMESETs to see if they match that in the vectors. The -PRIMARY matching can have one of 3 possible results. If the edges and logic levels of the PINTYPE exactly match those in the vector data then it is considered an active MATCH and the score is changed from 1 to 2. If there are edges in the vector data, but they do not match those in the PINTYPE statement, the TIMESET is a MISMATCH and the score is set to 0. And if there are no edges in the vector data for this cycle (clock is not running for example) then the TIMESET is considered a passive MATCH for this cycle (so its score is not altered), unless the -ACTIVE_ONLY flag is also specified in which case it would be considered a MISMATCH and the score would be set to 0. The IDENTIFIER evaluation will either produce a MATCH or a MISMATCH for each TIMESET cycle. An IDENTIFIER MATCH will cause the score to be changed from 1 to 2. A MISMATCH will cause the score to be set to 0. Once all of the TIMESETS have been analyzed against the vector data in the cycle, those that have a score of 2 (have at least one active MATCH and no MISMATCHES) have any WIEGHT factor added in. The TIMESET with the highest score will be deemed the MATCH for this cycle. If all of the TIMESETs are a MISMATCH for this cycle, then the -DEFAULT TIMESET is used as the MATCH (as mentioned above). The following flow chart illustrates the cycle matching processing: BEGIN | v LOOP ON ALL VECTORS <---------------| | | v | FOR ALL TIMESETS <------------| | SCORE=1 | | | | | v | | ACCUMULATE 1 CYCLE's WORTH | | OF DATA FROM POC FILE | | | | | | | v | | | CYCLIZE STATE DATA BASED | | | ON COMPUTED SAMPLE TIMES | | | FROM PINTYPE STATEMENTS | | | | | | | | | | v v | | CHECK ALL -PRIMARYs | | SCORE=2 IF ACTIVE MATCH--MISMATCH--->| | | SCORE=0 | | v | | CHECK IDENTIFIER | | SCORE=2 IF ACTIVE MATCH--MISMATCH--->| | | SCORE=0 | | v | | IF(SCORE==2) | | SCORE=SCORE+WEIGHT | | | | | v | | MORE TIMESETS ? ------YES------>| | | | v | TIMESET WITH HIGHEST | SCORE IS MATCH | (OR DEFAULT) | | | v | ADVANCE CYCLE & CHECK | FOR MORE VECTORS -----MORE--------->| | v DONE One of the challenges to the successful cyclization of POC data with multiple timesets in it, is to provide sufficient criteria to the cyclizer so that all cycles can be uniquely identified. It is usually a good idea to use the -PRIMARY flag on any clocks that will be running in the cycle. Often, cycles can also be uniquely identified using a signal state or logical combination of signal states. The IDENTIFIER criteria for cycle identification & matching should be used whenever possible. Since the MATCHing algorithm produces a MISMATCH whenever any of the -PRIMARY or IDENTIFIER criteria fail, the strategy for specifying these criteria in the TIMESET blocks should focus on identifying criteria which collectively uniquely identify the TIMESET. SELECT_RANGE ------------ For cases where the user knows the exact times where a particular timeset or timesets should be selected, this information can be used by vtran to make the selection. The cyclization process then can be made more efficient by using time ranges in which a specific timeset should be selected. One example of a case where this feature can greatly improve efficiency is when the TIMESET blocks used with Template Cyclization have cycle lengths that differ from each other by orders of magnitude. The new feature adds a SELECT_RANGE statement to the TIMESET block. The format of this statement is: SELECT_RANGE start_time end_time; For example: SELECT_RANGE 200.0 10000.0; The start time value of the SELECT_RANGE statement is included in the time sequence in which the timeset should be selected. The end time of the SELECT_RANGE statement is excluded; it is the time at which normal template cyclization should resume, or at which a different SELECT_RANGE statement may start. The SELECT_RANGE statement is optional. A TIMESET block may have multiple SELECT_RANGE statements. Select ranges may be defined for multiple timesets, but must not overlap. Once a TIMESET is selected for a cycle based on the SELECT_RANGE statement criteria, the normal template cyclization checks of PRIMARY signals and IDENTIFIERs for all TIMESETs are skipped, i.e the SELECT_RANGE criteria, when met, overrides any other selection criteria. Here is an example of its use; timeset WFT2 cycle 1000; pintype nrz * @ 0; pintype stb * @ 500, 1000; pintype rz Sclk @ 0, 5; select_range 130000, 144000; select_range 144250, 169000; endtimeset SAMPLE_POINT ------------ Prior to the cyclization process, vtran uses the timing specified in each TIMESET to compute the appropriate sample point within each cycle for each signal. For example, an input with a PINTYPE NRZ at 1.0 will be sampled at 1.0 ns into the cycle. A clock with PINTYPE RZ at (3.0, 4.0) will be sampled at 3.5 ns into the cycle, and likewise outputs with a PINTYPE STB at (6.1, 6.2) will be sampled at 6.1 ns into the cycle. An alternative to this automatic sample-point calculation is the use of the SAMPLE_POINT statement in the TIMESET block. This statement provides a way of explicitly specifying the time point within each TIMESET cycle where signals should have their states sampled. The syntax is: SAMPLE_POINT @