vgen_examples/ 755 143 12 0 6125646502 6656 vgen_examples/README 644 143 12 2071 6137203071 7614 VGEN VERSION 3.7 Usage The VGEN compiler can be invoked as follows: vgen source_file [output_file] where source_file is the name of the file containing your VGEN source program, and output_file is an optional output file name where the resulting vectors will be placed. If no output_file is specified, the output vectors will be placed in a default file named source_file.vec. A number of example VGEN source files are contained in the vgen_examples subdirectory on this tape, which can be compiled and used to experiment with. These source files utilize various features of the VGEN language and, along with the VGEN User's Manual, provide a good way of learning the language. In order to compile one of the example files, type: vgen exam_i [vec_file] where i = 1, 2, ... The [vec_file] is an optional output file name. The resulting vector file will be placed in a file named exam_i.vec [or vec_file if specified]. *** See the README.EXM file for a description of each exam_i file and the features/interfaces they illustrate. vgen_examples/exam_0 644 143 12 4510 6116505057 10036 { FILE: exam_0 PURPOSE: Demonstrate basic features VGEN features. This example uses Subroutines, FOR loops, STATE_TRANS, Bidirect merging, pin timing and many more features. DEVICE: Simple IC SIMULATOR: TSTL2 Toshiba format with both input stimulus and expected output state data. NOTES: Illustrates the required setup for generating TSTL2 files. } { define the pins } INPUTS R/W EXT REP* CLK,, DB<7..0>,,ADR<7..0>,,MODE<3..0> ; { ,, for space } bidirects ,,BIBUS<7..0>; outputs ,,O1, O2; busformat DB=hex, bibus=hex; { db and bibus in hex } CYCLE 90, all; { ,all keeps identical vectors form being filtered } SIMULATOR tstl2; STRING Z 'ZZ'; STRING X 'XX'; STRING TEMP; INT I; title "CIRCUIT1"; { define pin timings } pintype dt db @ 30; { shift db 30 ns to the right } pintype dt adr @ 10; { shift adr 10 ns to the right } pintype pp clk @ 30, 50; { clk pulse } pintype bidr bibus @ 15, 70; { bibus drive at 10, strobe at 70 } pintype stb o1, o2 @ 75; { strobe at 70 } { pintiming on db adr bibus o1 o2 clk ; } { do not enable for TSTL2 } { required to handle outputs and bidirects for TSTL2 } state_trans outputs '1'->'H', '0'->'L'; { output states } merge_bidirects 10HLZX; { merge bidirect i/o to single column } { FIRST RESET EVERYTHING } DB=lo; ADR=LO; MODE R/W EXT REP* = LO; CLK = HI; bibus = Z; o1, o2 = X; bibus.O = X; VGEN; VGEN; CALL CLOCK (4); MODE=1; VGEN; { NOW TEST MODES } FOR I=1 UNTIL 15 BEGIN EXT R/W = HI; CALL WRITE('4b'H, '22'H, I); { WRITE TO LOC 22 HEX } CALL READ('D7', I); { READ FROM LOC D7 HEX } END { TEST DB PATTERNS } TEMP = 1; EXT = 0; REP* = 1; FOR I = 0 UNTIL 18 BEGIN CALL WRITE(TEMP, I, 4); TEMP = TEMP < 1; END; END { SUBROUTINE DEFINITIONS } SUBROUTINE CLOCK (N) BEGIN REPEAT N BEGIN CLK = LO; VGEN; CLK = HI; VGEN; END END SUBROUTINE WRITE(D, A, M) BEGIN DB = D; R/W = 0; bibus = ~D; bibus.O = X; { input to bibus } ADR = A; MODE = M; VGEN; CALL CLOCK(1); END SUBROUTINE READ(A, I) BEGIN R/W=HI; ADR = A; DB = lo; bibus = Z; bibus.O = ~I; { output from bibus } o1 = 1; o2 = 0; VGEN; CALL CLOCK(2); bibus.O = X; { no more output } o1, o2 = X; END vgen_examples/exam_1 644 143 12 3326 6116505057 10043 { FILE: EXAM_1 PURPOSE: Demonstrate basic features VGEN features. This example uses the 'group' command to group pins under a single name. Boolean logic is used to simulate the functioning of the device. The state_trans command is also used. DEVICE: Simple PCB SIMULATOR: VALID_PRIM Valid primary I/O tabular format. No timing is used since this is a simply a set of combinational logic. NOTES: With no pin formatting defined, all pins are NRZ changing at the start of each cycle. } {Define the pin names} {vector output order is as listed} INPUTS p9 p8 p7 p6 p5 p4 p3 p2 p1; outputs o3 o2 o1; {cycle sets the time increment for each output vector} CYCLE 100; {define the simulator to be used} SIMULATOR valid_prim; {display the pin names vertically as comments every 55 lines in the output vectors} header 54; {Integer variables are declared. These will be used as counters for addressing} int i; {combine the inputs under a single group name P9 is MSB and P1 is LSB in this grouping} group g1 p9 p8 p7 p6 p5 p4 p3 p2 p1; {initialize all the inputs to high} g1 = hi; {initialize all the outputs} o1 o2 = hi; o3 = lo; {generate the startup vector} vgen; for i=0 until 256 begin {shift i left and set the input state} g1 = i < 1; {calculate the output states} o1 = (p1 & p2 & p3 & p4) | (p5 & p6) | (p7 & p8 & p9); o2 = ((p1|p2)&(p3|p4)&(p5|p6)) & p7; o3 = o1 ^ o2; {generate the vector} vgen; end; {end of for loop} {End of simulation} { Map 1->H and 0->L for outputs } STATE_TRANS outputs '1'->'H', '0'->'L'; end vgen_examples/exam_10 644 143 12 20570 6116505057 10143 { FILE: EXAM_10 PURPOSE: demonstrate math/logic operations - switch statement DEVICE: 74S281 4-bit parallel binary accumulator SIMULATOR: MAXPLUS creates inputs and (optionally) expected outputs. The Maxplus "Group Create" command is used by VGEN to define buses. Absolute timestamps are used. NOTES: the propogate and generate outputs are used for look ahead carry generators (74S182) and are not used in this simulation } {define the pin names} {data in} INPUTS IN[3:0]; {register select} INPUTS RS[1:0]; {register control} INPUTS RC; {Mode Control} INPUTS MODE; {Function Select} INPUTS AS[2:0]; {Carry in} INPUTS CARRY*; {Clock} INPUTS CLK; {Propogate and Generate outputs} OUTPUTS PROP*,GEN*; {Carry Output} OUTPUTS COUT; {Shift Left Input/Shift Right Output} OUTPUTS LR; {Shift Right Input/Shift Left Output} OUTPUTS RL; {Data Outputs} OUTPUTS OUT[3:0]; {setup counter variables} INT i,j; {set up a variable to hold the state of ALU Register B} STRING REGB 'uuuu'b; {FUNCTION TABLES (/ = complement) ARITHMETIC FUNCTIONS (A is IN, B is ALU REGISTER B) AS CARRY* = H CARRY* = L MODE 0 OUT = HI OUT = HI L 1 OUT = B-A OUT = B-A-1 L 2 OUT = A-B OUT = A-B-1 L 3 OUT = A+B+1 OUT = A+B L 4 OUT = B+1 OUT = B L 5 OUT = /B* OUT = /B L 6 OUT = A+1 OUT = A L 7 OUT = /A+1 OUT = /A L LOGIC FUNCTIONS AS MODE 0 OUT = L H 1 OUT = A XOR B H 2 OUT = /(A XOR B) H 3 OUT = A XOR B H 4 OUT = A * B H 5 OUT = /(A+B) H 6 OUT = /(A * B) H 7 OUT = A + B H SHIFT MODE FUNCTIONS BEFORE AFTER FUNCTION RS RC RL SHFTIN LR CLK RL OUT (ALU B) LR LOAD 0 X Z OUT[3:0] Z C Z OUT[3:0] Z LSL 2 L Qa Q[3:0] li C Q1 li,Q[3:1] li LSA 2 H Qa Q[3:0] li C Q1 Q3,li,Q[2:1] li RSL 1 L ri Q[3:0] Q3 C ri Q[2:0],ri Q2 RSA 1 H ri Q[3:0] Q2 C ri Q3,Q[1:0],ri Q1 HOLD 3 X X Q[3:0] X C Z Q[3:0] Z HOLD X X X Q[3:0] X L RL Q[3:0] LR (Q - previous state of OUT ri - previous state of RL li - previous state of LR } {cycle sets the time increment for each output vector} CYCLE 100; {define the simulator to be used} SIMULATOR MAXPLUS; {subroutine to generate a clock pulse - takes the expected output as a parameter} SUBROUTINE CLOCK(EXP) BEGIN {clock hi and generate a vector} CLK = HI; VGEN; {clock lo, exp output set and generate a vector} OUT = EXP; CLK = LO; VGEN; END {subroutine to load ALU Register B with Parameter DATA} SUBROUTINE LOADB(DATA) BEGIN {Use Arithmetic function 6 OUT = A} AS=6; CARRY* = LO; MODE = LO; {SET INPUT} IN = DATA; {setup Shift functions} RS = 0; RL = 'Z'; LR = 'Z'; VGEN; {set expected output} OUT = DATA; VGEN; call Clock(DATA); {set REG B Holding variable} REGB = Data; END {The main portion of the vector generation starts here First initialize pins } IN RS RC MODE AS CARRY* CLK = LO; COUT = 'L'; LR RL = 'Z'; OUT = HI; VGEN; {Arithmetic functions} {Load B with 0} call LOADB(0); {seven arithmetic functions} for i=0 until 7 BEGIN {load the B Register with 8} call LOADB(8); {set the AS for the funtion to test} AS = i; CARRY* = HI; MODE = LO; switch(i) BEGIN case 0: {OUT = HIGH} VGEN; {set outputs} OUT = HI; VGEN; {alternate function} CARRY* = LO; VGEN; break; case 1: {OUT = B-A} IN = 3; VGEN; {OUT = 8-3} OUT = REGB-IN; VGEN; {alternate function} {OUT = B-A-1} CARRY* = LO; VGEN; {OUT = 8-3-1} OUT = REGB-IN-1; VGEN; break; case 2: {OUT = A-B} IN = 12; VGEN; {OUT = 12-8} OUT = IN-REGB; VGEN; {alternate function} {OUT = A-B-1} CARRY* = LO; VGEN; {OUT = 12-8-1} OUT = IN-REGB-1; VGEN; break; case 3: {OUT = A+B+1} IN = 4; VGEN; {OUT = 4+8+1} OUT = REGB+IN+1; VGEN; {alternate function} {OUT = A+B} CARRY* = LO; VGEN; {OUT = 4+8} OUT = REGB+IN; VGEN; break; case 4: {OUT = B+1} VGEN; {OUT = 8+1} OUT = REGB+1; VGEN; {alternate function} {OUT = B} CARRY* = LO; VGEN; {OUT = 8} OUT = REGB; VGEN; break; case 5: {OUT = /B+1} VGEN; {OUT = /8+1} OUT = ~REGB+1; VGEN; {alternate function} {OUT = /B} CARRY* = LO; VGEN; {OUT = /8} OUT = ~REGB; VGEN; break; case 6: {OUT = A+1} IN = 6; VGEN; {OUT = 6+1} OUT = IN+1; VGEN; {alternate function} {OUT = A} CARRY* = LO; VGEN; {OUT = 6} OUT = IN; VGEN; break; case 7: {OUT = /A+1} IN = 9; VGEN; {OUT = 9+1} OUT = ~IN+1; VGEN; {alternate function} {OUT = /A} CARRY* = LO; VGEN; {OUT = /9} OUT = ~IN; VGEN; break; END; END; {Logic functions} {seven logic functions} for i=0 until 7 BEGIN {load the B Register with 5} call LOADB(5); {set the AS for the funtion to test} AS = i; CARRY* = HI; MODE = HI; switch(i) BEGIN case 0: {OUT = LO} VGEN; OUT = LO; VGEN; CARRY* = LO; VGEN; break; case 1: case 3: {OUT = A XOR B} IN = 3; VGEN; {OUT = 3 xor 5} OUT = REGB^IN; VGEN; break; case 2: {OUT = /(A XOR B)} IN = 12; VGEN; {OUT = /(12 XOR 5)} OUT = ~(IN^REGB); VGEN; break; case 4: {OUT = A * B} IN = 6; VGEN; {OUT = 5&6} OUT = IN & REGB; VGEN; break; case 5: {OUT = /(A + B)} IN = 2; VGEN; {OUT = /(2|5)} OUT = ~(REGB|IN); VGEN; break; case 6: {OUT = /(A * B)} IN = 6; VGEN; {OUT = /(6&5)} OUT = ~(IN®B); VGEN; break; case 7: { OUT = A + B} IN = 8; VGEN; {OUT = 8+5} OUT = IN+REGB; VGEN; break; END; END; END Left Input/Shift Right Output} OUTPUTS LR; {Shift Right Input/Shift Left Output} OUTPUTS RL; {Data Outputs} OUTPUTS OUT[3:0]; {vgen_examples/exam_11 644 143 12 5415 6116505057 10125 { FILE: EXAM_11 PURPOSE: demonstrate switch (Case) operations and conditionals DEVICE: State Machine SIMULATOR: TSTL2 Toshiba TSTL2 format. NOTES: } {define the pin names} {clock, enb} INPUTS CLK, ENB; {Data Outputs 1 of 9 select - ,, puts space in front} OUTPUTS ,,OUT[8:0]; {timing for pins - don't enable it ! } pintype pp CLK @ 25, 50; pintype dt ENB @ 5; pintype stb out @ 85; {setup counter variables} INT i; {output state} int OutState; {previous State} int PrevState; {STATE TABLE PREV CURRENT NEXT X 1 2 X 2 3 2 3 4 5 3 6 7 3 8 9 3 1 X 4 5 X 5 3 X 6 7 X 7 8 X 8 9 X 9 3 } {cycle sets the time increment for each output vector} CYCLE 100; {define the simulator to be used} SIMULATOR TSTL2; {stranslate output state characters} STATE_TRANS outputs '1'->'H', '0'->'L'; {subroutine to generate a clock pulse - takes the expected output as a parameter} SUBROUTINE CLOCK(NextState) BEGIN {Clock Hi} Clk enb = HI; {Outputs change } PrevState = OutState; OutState = NextState; {Set single bit select high} Out = 1<(OutState-1); VGEN; Clk ENB = LO; vgen; END; {The main portion of the vector generation starts here First initialize pins } CLK ENB = LO; OUT = 1; PrevState = 3; OutState = 1; VGEN; {100 vectors} for i=0 until 100 BEGIN switch (OutState) BEGIN case 1: {Clock to next state} Call Clock(2); break; case 2: {Clock to next state} Call Clock(3); break; case 3: {Clock to next state, check previous state to see what the next state is.} if (PrevState\==\2) then Call Clock(4); else if (PrevState\==\9) then Call Clock(1); else Call Clock(PrevState+1); break; case 4: {Clock to next state} Call Clock(5); break; case 5: {Clock to next state} Call Clock(3); break; case 6: {Clock to next state} Call Clock(7); break; case 7: {Clock to next state} Call Clock(3); break; case 8: {Clock to next state} Call Clock(9); break; case 9: {Clock to next state} Call Clock(3); break; END; END; END vgen_examples/exam_12 644 143 12 5052 6116505057 10123 { FILE: EXAM_12 PURPOSE: demonstrate 'state_trans' and 'merge_bidirects'. demonstrate the use of 'bidirects' and 'pintype'. DEVICE: 2Kx8 Prom SIMULATOR: UDF User defined tabular format. Invoked via: 'SIMULATOR UDF "Format string" [,bit_sep='c'] [,include_bi_outs] See the manual for specifics regarding the parameters. NOTES: uses pin timing to define pin waveforms. Timing is set up seperately for the input and output portion of 'BIDIRECTS' } {define the pin names (use ',,' before pins to place a spacve in the output vectors} {Program} {Program Enable} INPUTS PGMEN; INPUTS ,,PGM; {Verify} INPUTS VFY; {Address} INPUTS ,,Addr[10:0]; {Data - In and Out} BIDIRECTS ,,DATA[7:0]; {setup counter variables} INT i; {DEVICE DATA} TABLE PRDATA BEGIN 1 'fe' 2 'fd' 4 'fb' 8 'f7' '10' 'ef' '20' 'df' '40' 'bf' '80' '7f' END; {cycle sets the time increment for each output vector} CYCLE 200; {define the simulator to be used} SIMULATOR UDF "T%10at - $States:"; {define Pin formatting} {address is NRZ at T0} PINTYPE NRZ Addr PGMEN @0; {Databus (input portion) is RZ when (when not driven for pgm pulse)} PINTYPE RX 'Z' DATA @10 130; PINTYPE RO PGM @20 120; {Databus.o is RZ when (when not enabled for verify)} PINTYPE RX 'Z' DATA.o @160 190; PINTYPE RO VFY @150 180; {translate outputs from 0-1 to L-H} STATE_TRANS outputs '0'->'L','1'->'H'; {MERGE DATA PIN INPUT and OUTPUT to single bus (states are specified in order of precedence} MERGE_BIDIRECTS HL01ZX; {The main portion of the vector generation starts here First initialize pins } {Pintiming off until PGM/VFY mode entered} PINTIMING OFF PGM VFY DATA DATA.o ADDR; Addr = LO; DATA = 'XX'; DATA.o = 'XX'; PGM VFY = HI; PGMEN = LO; VGEN; {Enable Program/Verify - use 'v' to denote High voltage} PGMEN = 'V'; DATA = 'ZZ'; DATA.o = 'ZZ'; VGEN; {Now in pgm/vfy mode - enable pintiming} PINTIMING ON PGM VFY DATA DATA.o ADDR; {PGM and VFY to low to enable pulses} PGM = LO; VFY = LO; {2048 vectors} for i=0 until 2047 BEGIN addr = i; {Modulus} {note the parentheses are required i-(i/16)*16 will not work. Operator precedence is not supported in VGEN} {input and output portion of bidirects treated seperately} data = PRData((i-((i/16)*16))); data.o = data vgen; END; END vgen_examples/exam_13 644 143 12 25734 6116505057 10155 { FILE: EXAM_13 PURPOSE: Demonstrate the use of the pintype command to define pin waveforms. Also demonstrates the use of file I/O to input vectors. DEVICE: microcomputer interface bus SIMULATOR: QSIM This is the LSIM format using both input stimulus and expected output states. NOTES: uses a while loop to process the vector file. Conditionals are used to break out of the while loop when end of file (EOF) is reached } {Define the pin names} {Clock 2x} inputs CLK2XIN ; {System Clock} outputs SYSCLKB; {32 bit address bus} bidirects ADBUS_31 ADBUS_30 ADBUS_29 ADBUS_28 ADBUS_27 ADBUS_26 ADBUS_25 ADBUS_24 ADBUS_23 ADBUS_22 ADBUS_21 ADBUS_20 ADBUS_19 ADBUS_18 ADBUS_17 ADBUS_16 ADBUS_15 ADBUS_14 ADBUS_13 ADBUS_12 ADBUS_11 ADBUS_10 ADBUS_9 ADBUS_8 ADBUS_7 ADBUS_6 ADBUS_5 ADBUS_4 ADBUS_3 ADBUS_2 ADBUS_1 ADBUS_0; {Address Control} bidirects ADR_3 ADR_2 ; {Diag pins, ALE, BurstWrite and Data Enable outputs} outputs DIAG_1 DIAG_0 MG_ALE BURST_WRNB MG_DATAENB ; {bidirectional pins} bidirects MG_RDB MG_WRB ; bidirects BUSGNTB ; {control inputs} inputs ACKB MG_BUSERRB RDCENB BUSREQB MG_INTB_5 MG_INTB_4 MG_INTB_3 MG_INTB_2 MG_INTB_1 MG_INTB_0 RSTB BRCOND_3 BRCOND_2 BRCOND_1 BRCOND_0 RESVD_4 RESVD_3 RESVD_2 RESVD_1 RESVD_0 ; {group the address bus inputs under a single name} group ADBUS ADBUS_31 ADBUS_30 ADBUS_29 ADBUS_28 ADBUS_27 ADBUS_26 ADBUS_25 ADBUS_24 ADBUS_23 ADBUS_22 ADBUS_21 ADBUS_20 ADBUS_19 ADBUS_18 ADBUS_17 ADBUS_16 ADBUS_15 ADBUS_14 ADBUS_13 ADBUS_12 ADBUS_11 ADBUS_10 ADBUS_9 ADBUS_8 ADBUS_7 ADBUS_6 ADBUS_5 ADBUS_4 ADBUS_3 ADBUS_2 ADBUS_1 ADBUS_0; {group the address bus outputs under a single name} group ADBUS.o ADBUS_31.o ADBUS_30.o ADBUS_29.o ADBUS_28.o ADBUS_27.o ADBUS_26.o ADBUS_25.o ADBUS_24.o ADBUS_23.o ADBUS_22.o ADBUS_21.o ADBUS_20.o ADBUS_19.o ADBUS_18.o ADBUS_17.o ADBUS_16.o ADBUS_15.o ADBUS_14.o ADBUS_13.o ADBUS_12.o ADBUS_11.o ADBUS_10.o ADBUS_9.o ADBUS_8.o ADBUS_7.o ADBUS_6.o ADBUS_5.o ADBUS_4.o ADBUS_3.o ADBUS_2.o ADBUS_1.o ADBUS_0.o; {group the diagnostic pins under a single name} group DIAG DIAG_1 DIAG_0 ; {group the interrupt pins under a single name} group MG_INTB MG_INTB_5 MG_INTB_4 MG_INTB_3 MG_INTB_2 MG_INTB_1 MG_INTB_0 ; {group the burst pins under a single name} group BRCOND BRCOND_3 BRCOND_2 BRCOND_1 BRCOND_0 ; {group reserved pins under a single name} group RESVD RESVD_4 RESVD_3 RESVD_2 RESVD_1 RESVD_0 ; {cycle sets the time increment for each output vector} cycle 100; {define the simulator to be used} simulator masm; {define the pintypes} {return to zero change to state at 25ns, return at 75ns} pintype rz CLK2XIN @ 25 75 ; {return to state, active at 80-90ns, the 'U' is the state character used for the return to state, any valid state character can be used for the return to state.} pintype rx 'U' SYSCLKB @ 80 90 ; {non-return to zero, by default changes at T0 the start of the cycle} pintype nrz ADBUS_31 ADBUS_30 ADBUS_29 ADBUS_28 ADBUS_27 ADBUS_26 ADBUS_25 ADBUS_24 ADBUS_23 ADBUS_22 ADBUS_21 ADBUS_20 ADBUS_19 ADBUS_18 ADBUS_17 ADBUS_16 ADBUS_15 ADBUS_14 ADBUS_13 ADBUS_12 ADBUS_11 ADBUS_10 ADBUS_9 ADBUS_8 ADBUS_7 ADBUS_6 ADBUS_5 ADBUS_4 ADBUS_3 ADBUS_2 ADBUS_1 ADBUS_0 @ 0 ; {return to state, active at 80-90ns, the 'U' is the state character used for the return to state, any valid state character can be used for the return to state.} pintype rx 'U' ADBUS_31.o ADBUS_30.o ADBUS_29.o ADBUS_28.o ADBUS_27.o ADBUS_26.o ADBUS_25.o ADBUS_24.o ADBUS_23.o ADBUS_22.o ADBUS_21.o ADBUS_20.o ADBUS_19.o ADBUS_18.o ADBUS_17.o ADBUS_16.o ADBUS_15.o ADBUS_14.o ADBUS_13.o ADBUS_12.o ADBUS_11.o ADBUS_10.o ADBUS_9.o ADBUS_8.o ADBUS_7.o ADBUS_6.o ADBUS_5.o ADBUS_4.o ADBUS_3.o ADBUS_2.o ADBUS_1.o ADBUS_0.o @ 80 90 ; {non-return to zero, changes at the specified time, in this case 0ns = T0} pintype nrz ADR_3 ADR_2 @ 0 ; {return to state, active at 80-90ns, the 'U' is the state character used for the return to state, any valid state character can be used for the return to state.} pintype rx 'U' ADR_3.o ADR_2.o DIAG_1 DIAG_0 MG_ALE BURST_WRNB MG_DATAENB @ 80 90 ; {non-return to zero, changes at the specified time, in this case 0ns = T0} pintype nrz MG_WRB @ 0 ; {return to state, active at 80-90ns, the 'U' is the state character used for the return to state, any valid state character can be used for the return to state.} pintype rx 'U' MG_WRB.o @ 80 90 ; pintype rx 'U' MG_RDB.o @ 80 90 ; {non-return to zero, changes at the specified time, in this case 0ns = T0} pintype nrz MG_RDB @ 0 ; pintype nrz BUSGNTB @ 0 ; {return to state, active at 80-90ns, the 'U' is the state character used for the return to state, any valid state character can be used for the return to state.} pintype rx 'U' BUSGNTB.o @ 80 90 ; {non-return to zero, changes at the specified time, in this case 0ns = T0} pintype nrz ACKB MG_BUSERRB RDCENB BUSREQB MG_INTB_5 MG_INTB_4 MG_INTB_3 MG_INTB_2 MG_INTB_1 MG_INTB_0 RSTB BRCOND_3 BRCOND_2 BRCOND_1 BRCOND_0 RESVD_4 RESVD_3 RESVD_2 RESVD_1 RESVD_0 @ 0 ; {open the file "exam_13.vvh" for reading} fopen(f1,"exam_13.vvh"); {enable the pintiming on the following pins} pintiming on CLK2XIN, SYSCLKB, ADBUS_31 ADBUS_30 ADBUS_29 ADBUS_28 ADBUS_27 ADBUS_26 ADBUS_25 ADBUS_24 ADBUS_23 ADBUS_22 ADBUS_21 ADBUS_20 ADBUS_19 ADBUS_18 ADBUS_17 ADBUS_16 ADBUS_15 ADBUS_14 ADBUS_13 ADBUS_12 ADBUS_11 ADBUS_10 ADBUS_9 ADBUS_8 ADBUS_7 ADBUS_6 ADBUS_5 ADBUS_4 ADBUS_3 ADBUS_2 ADBUS_1 ADBUS_0 ADBUS_31.o ADBUS_30.o ADBUS_29.o ADBUS_28.o ADBUS_27.o ADBUS_26.o ADBUS_25.o ADBUS_24.o ADBUS_23.o ADBUS_22.o ADBUS_21.o ADBUS_20.o ADBUS_19.o ADBUS_18.o ADBUS_17.o ADBUS_16.o ADBUS_15.o ADBUS_14.o ADBUS_13.o ADBUS_12.o ADBUS_11.o ADBUS_10.o ADBUS_9.o ADBUS_8.o ADBUS_7.o ADBUS_6.o ADBUS_5.o ADBUS_4.o ADBUS_3.o ADBUS_2.o ADBUS_1.o ADBUS_0.o ADR_3 ADR_2 ADR_3.o ADR_2.o DIAG_1 DIAG_0 MG_ALE BURST_WRNB MG_DATAENB ; pintiming on MG_RDB MG_RDB.o MG_WRB ; pintiming on MG_WRB.O; pintiming on BUSGNTB BUSGNTB.o ACKB MG_BUSERRB RDCENB BUSREQB MG_INTB_5 MG_INTB_4 MG_INTB_3 MG_INTB_2 MG_INTB_1 MG_INTB_0 RSTB BRCOND_3 BRCOND_2 BRCOND_1 BRCOND_0 RESVD_4 RESVD_3 RESVD_2 RESVD_1 RESVD_0 ; {integer variable for counter} int I; {create string variables to hold pin states} string ADREN ; string ADBUSEN ; string CTLEN ; string BUSGNTEN ; string iADR iDIAG; {The main portion of the vector generation starts here} {initialize the clock pin} CLK2XIN=1; i=1; while 1 begin {read the following pins and variables from the opened file} fread(f1, "%B%H%8H%H%H%H%H%B%B%B%B%B%H%B%B%B%B%B%2H%B%H%2H\n", SYSCLKB, ADBUSEN, ADBUS, ADREN, iADR, CTLEN, iDIAG, MG_ALE, BURST_WRNB, MG_DATAENB, MG_RDB, MG_WRB, BUSGNTEN, BUSGNTB, ACKB, MG_BUSERRB, RDCENB, BUSREQB, MG_INTB, RSTB, BRCOND, RESVD); {if the end of the file has been reached, break out of the for loop} if($FILE_STAT \!=\ 0) then break; {set pin states} ADR_3 ADR_2 DIAG_1 DIAG_0 = iADR; DIAG_1 DIAG_0 = iDIAG; {if the ADBUSEN is '10' binary the set the ADBUS outputs and tri-state the ADBUS inputs (ADBUS is a bi-directional bus)} if (ADBUSEN \==\ '10'B) then begin ADBUS.o=ADBUS; ADBUS='ZZZZZZZZ'; end; {set ADR_3 and ADR_2 as output states if MF_RDB or MG_WRB are LO} if ((ADREN \==\ '10'B) & ((MG_RDB \==\ '0'B) | (MG_WRB \==\ '0'B))) then begin ADR_3.o=ADR_3; ADR_2.o=ADR_2; ADR_3='Z'; ADR_2='Z'; end; {Do we need a burst transfer} if (CTLEN \!=\ '10'B) then begin MG_ALE='U'; BURST_WRNB='U'; MG_DATAENB='U'; MG_RDB.o='U'; MG_WRB.o='U'; end else begin MG_RDB.o=MG_RDB; MG_WRB.o=MG_WRB; MG_RDB='Z'; MG_WRB='Z'; end; if (BUSGNTEN \!=\ '10'B) then begin BUSGNTB.o='U'; end else begin BUSGNTB.o=BUSGNTB; BUSGNTB='Z'; end; {set the diag states} if ((SYSCLKB \!=\ '1'B) | (CTLEN \!=\ '10'B) | (MG_RDB \!=\ '0'B)) then DIAG_1='U'; if ((SYSCLKB \!=\ '1'B) | ((CTLEN \!=\ '10'B) | (MG_RDB \!=\ '0'B) | (DIAG_1 \!=\ '1'B))) then DIAG_0='U'; {set the rest of the pins} if I \<=\ 9 then begin SYSCLKB='U'; ADBUS.o='UUUUUUUU'; ADR_3.o='U'; ADR_2.o='U'; MG_ALE='U'; BURST_WRNB='U'; MG_DATAENB='U'; MG_RDB.o='U'; MG_WRB.o='U'; BUSGNTB.o='U'; DIAG_1='U'; DIAG_0='U'; end; {generate a vector} vgen; {reset to 'U'} ADBUS.o='UUUUUUUU'; ADR_3.o='U'; ADR_2.o='U'; MG_ALE='U'; BURST_WRNB='U'; MG_DATAENB='U'; MG_RDB.o='U'; MG_WRB.o='U'; BUSGNTB.o='U'; DIAG_1='U'; DIAG_0='U'; {increment the counter} i = i+1; end; {close the vector file} fclose(f1); end; he cycle} pintype nrz ADBUS_31 ADBUvgen_examples/exam_13.vvh 644 143 12 1200 6116505057 10715 10a5a5a5a52c22011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 10a5a5a5a52822011112111113f0000 02a5a5a5a52822011112111113f0000 vgen_examples/exam_14 644 143 12 11717 6116505057 10152 { FILE: EXAM_14 PURPOSE: demonstrate basic file i/o , bit ranges, and local variables DEVICE: Memory SIMULATOR: VIEWSIM_GEN Produces a vector file and a '.CMD' command file. The command file defines all of the pins as a single vector ('allpins') and reads in the vector file. ie: "vector allpins pin1 pin2 ... pinn bus1 bus2 ... busn" "wfm allpins < *.vec" NOTES: loads output states from a file. } {Define the pin names - ',,' is used to add space} INPUTS r/w ext rep* clk,, DB<7..0>,,aDR<7..0>,,MODe<3..0>; bidirects expins*[7:0]; {set the initial time value} time 5500; {cycle sets the time increment for each output vector} CYCLE 90; {define the simulator to be used} SIMULATOR viewsim_gen; {create string variables to hold pin states} STRING Z ; string TEMP1[8] ; string TEMP ; string addr; {integer variables declared, used to count} INT I, j; {define the pintypes} {db NRZ 30 ns after T0} pintype nrz db @ 30; {adr NRZ 10 ns after T0} pintype nrz adr @ 10; {enable the pin formatting} pintiming on db adr ; {initialize the pins} i = 7; {because the default radix is hex, two characters are required to set the bus to 'z', only one is used so that a later demontration of conditionals using bit ranges can be made} Z[7:0] = 'Z'; temp1[i] = 1; ext ADR=LO; r/w MODE R/W rep* =LO; DB = Z; expins* CLK = HI; expins*.o = 'AA'; { Illustrate the use of bit ranges in conditionals. Only 4 bits were initialized} if (db[4:3]\!=\'ZZ'b) then echo " Z Compare fail: db = $db$"; if (db[7:4]\!=\Z[3:0]) then echo " Z Compare 1 fail: db = $db$"; {generate intial vector} VGEN; {Clock 4 times} CALL CLOCK (4); {Set the MODE pin HI and generate a vector} MODE=1; VGEN; {if the cycle time is not 90 the the simulator is not setup correctly, the echo command displays output on the user console} if $cycle\==\90 then echo " OK"; else echo " BAD"; {open the file "exam_14.exe", this file contains the expected output states} fopen(f1, "exam_14.ext"); {for modes 1 through 15 write the data from the file into address 22h} FOR I=1 UNTIL 15 BEGIN EXT R/W = HI; {read 2 bits of hex data from the file and set the state of the expins to the data read from the file} fread(f1, "%2H\n", expins*.o); {set the pins the the data read} expins* = ~expins*.o; {test for end of file} if ($FILE_STAT\!=\0) then echo "Error in file read"; {set the address} addr = '22'H; {generate the write vector} CALL WRITE('4b'H, &addr, I); {pin by pin assign} temp1 = db; if temp1\!=\'4b' then echo " ERROR, temp1 = $temp1$"; {pin by pin assign} temp1 = db[7:0]; if temp1\!=\'4b' then echo " ERROR, temp1 = $temp1$"; {check valid pin data on bus} if ((temp1[0]\!=\db[0]) | (temp1[1]\!=\db[1]) | (temp1[2]\!=\0)) then echo " ERROR in compound"; {Read from location D7h} CALL READ('D7'); END; {Close the file} fclose(f1); TEMP = 1; TEMP1 = '1'b; EXT = 0; REP* = 1; {write 18 consecutive bytes of data} FOR I = 0 UNTIL 18 BEGIN {write the data} CALL WRITE(TEMP1, I, 4); {check for valid pin state on the bus} if temp[i]\!=\'1'b then echo "ERROR !! temp = $temp$, i = $i$"; {bit manipulation -> the follwing is equivalent to temp < 1 (shift left)} temp[i+1] = temp[i]; temp[i] = 0; temp1 = temp1 < 1; END; call write(5, 9, 3); END {Subroutine for clock cycle - takes as a parameter the number of clock pulses desired} SUBROUTINE CLOCK (N) BEGIN { pulse the clock pin 'N' times } REPEAT N BEGIN {CLK LO and generate a vector} CLK = LO; VGEN; {CLK HI and generate a vector} CLK = HI; VGEN; END END {Subroutine for write cycle - takes three parameters D - data bus, A - Address Bus, M - Mode} SUBROUTINE WRITE(D, A, M) BEGIN {declare local variables. These are not the same variables used above as global variables. Local variable supersede global variables of the same name} int j, i; {pin by pin assign} for j=0 until 7 begin db[j] = d[j]; end; R/W = 0; i = 2; j = 9; {here is an example of using expressions to index into buses} ADR[(j-2):4] = A[j-i:(i+i)]; MODE = M; ADR[3:0] = A[i+1:i-2]; VGEN; CALL CLOCK(1); END {Subroutine for read cycle - takes the address (A) as a parameter} SUBROUTINE READ(A) BEGIN {declare local variables. These are not the same variables used above as global variables. Local variable supersede global variables of the same name} int i; string temp[8]; temp = Z; {pin by pin assign} for i=0 until 7 begin db[i] = temp[i]; end; R/W=HI; ADR = A; VGEN; CALL CLOCK(2); END ns*.o; {test for end of file} if ($FILE_Svgen_examples/exam_14.ext 644 143 12 61 6116505057 10657 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF 00 vgen_examples/exam_15 644 143 12 10312 6116505060 10133 { FILE: EXAM_15 PURPOSE: demonstrate file I/O - used to merge 2 vector files. DEVICE: N/A SIMULATOR: ORCAD Time field begins in column 1 and is 10 digits wide. The first vector starts in column 13. Individual pins have a space between columns, but there are no spaces between bus pins. NOTES: } {Define the pin names - ',,' is used to add space} INPUTS r/w ext rep* clk,, DB<7..0>,,aDR<7..0>,,MODe<3..0> ; { ,, for space } inputs expins[7:0]; inputs Q2, Q1, Q0; outputs out2, out1; {cycle sets the time increment for each output vector} CYCLE 90; {define the simulator to be used} SIMULATOR orcad; {create string variables to hold pin states} string s1, s2, s3; {create integer variables and initialize to zero} int i1, i2 0; {define additional characters as whitespace - these are ignored during file reads (they are treated as blanks)} whitespace ',', ';'; {group the pins under a single name (similar to a bus, but can combine pins and buses)} group b1 r/w ext rep* clk ; group b2 DB<7..0>,,aDR<7..0>,,MODe<3..0> expins[7:0]; group b3 q2, q1, q0, out2, out1; {define the bus radix to be hex} busformat hex; {clear the file error flag} $FILE_STAT = 0; {open the first vector file} fopen(t1, "exam_15.x3"); {read from the file until the word "START" (or EOF) is found at the beginning of a line. This is where the vectors start} while (s1\!=\'START'B)&($FILE_STAT\==\0) begin {read 5 characters into s1 and advance the file pointer to the next line ('\n')} fread(t1, "%5B\n", s1); {i1 is used to count lines processed} i1 = i1 + 1; end; {report the starting vector line} echo "File 1 start line = $i1$"; {reset the file i/o error flag and line counter} $FILE_STAT = 0; i1 = 0; {Open the second vector file} fopen(t2, "exam_15.x6"); {read from the file until the "$" (or EOF) is found at the beginning of a line. This is where the vectors start} while (s1\!=\'$'B)&($FILE_STAT\==\0) begin {read 1 character into s1 and advance the file pointer to the next line ('\n')} fread(t2, "%B\n", s1); {i1 is used to count lines processed} i1 = i1 + 1; end; {report the starting vector line} echo "File 2 start line = $i1$"; {from file 1 read: an integer into i1 (the time stamp), 4 bits of data into s1 (group b1), 7 hex bytes into s2 (group b2) from file 2 read: in integer into i2 (second time stamp), 5 bits if data into s3 (group b3)} fread(t1, " %d / %4B%7H\n", i1, s1, s2); fread(t2, "%d %5B\n", i2, s3); {Merge until no more data (EOF)} while (1) begin { if the timestamp from file 1 is before (less than) the time stamp from file 2} if(i1\<\i2) then begin {set the cycle time} $time = i1; {Set the groups from file 1} b1 = s1; b2 = s2; {read the next data from file 1} fread(t1, " %d / %4B%7H\n", i1, s1, s2); {if EOF the merging is done} if ($file_stat\!=\0) then break; end; { if the timestamp from file 2 is before (less than) the time stamp from file 1} else if (i2\<\i1) then begin {set the cycle time} $time = i2; {Set the groups from file 2} b3 = s3; {read the next data from file 2} fread(t2, "%d %5B\n", i2, s3); {if EOF the merging is done} if ($file_stat\!=\0) then break; end; { if the timestamp from file 1 and 2 are equal} else begin {set the cycle time} $time = i1; {Set the groups from file 1 and file 2} b1 = s1; b2 = s2; b3 = s3; {read the next data from file 1} fread(t1, " %d / %4B%7H\n", i1, s1, s2); {if EOF the merging is done} if ($file_stat\!=\0) then break; {read the next data from file 1} fread(t2, "%d %5B\n", i2, s3); {if EOF the merging is done} if ($file_stat\!=\0) then break; end; {output the vector just merged} vgen; end; {close the vector files} fclose(t1); fclose(t2); END gits wide. The first vector starts in column 13. Individual pins have a space between columns, but there are no spaces between bus pins. NOTES: } {Define the pin names - ',,' is used to add space} INPUTS r/w ext rep* clk,, DB<7..vgen_examples/exam_15.x3 644 143 12 20370 6116505060 10471 FILE_TYPE = TABULAR_TRACE; R/W ,2 EXT ,2 REP* ,2 CLK ,2 DB<7..0> ,16 ADR<7..0> ,16 MODE<3..0> ,16 EXPINS<7..0> ,16 START_TAB_TRACE; 5500 / 0,0,0,1,XX,XX,0,FF; 5510 / 0,0,0,1,XX,00,0,FF; 5530 / 0,0,0,1,ZZ,00,0,FF; 5590 / 0,0,0,0,ZZ,00,0,FF; 5680 / 0,0,0,1,ZZ,00,0,FF; 5770 / 0,0,0,0,ZZ,00,0,FF; 5860 / 0,0,0,1,ZZ,00,0,FF; 5950 / 0,0,0,0,ZZ,00,0,FF; 6040 / 0,0,0,1,ZZ,00,0,FF; 6130 / 0,0,0,0,ZZ,00,0,FF; 6220 / 0,0,0,1,ZZ,00,0,FF; 6310 / 0,0,0,1,ZZ,00,1,FF; 6400 / 0,1,0,1,ZZ,00,1,11; 6410 / 0,1,0,1,ZZ,22,1,11; 6430 / 0,1,0,1,4B,22,1,11; 6490 / 0,1,0,0,4B,22,1,11; 6580 / 0,1,0,1,4B,22,1,11; 6670 / 1,1,0,1,4B,22,1,11; 6680 / 1,1,0,1,4B,D7,1,11; 6700 / 1,1,0,1,ZZ,D7,1,11; 6760 / 1,1,0,0,ZZ,D7,1,11; 6850 / 1,1,0,1,ZZ,D7,1,11; 6940 / 1,1,0,0,ZZ,D7,1,11; 7030 / 1,1,0,1,ZZ,D7,1,11; 7120 / 0,1,0,1,ZZ,D7,2,22; 7130 / 0,1,0,1,ZZ,22,2,22; 7150 / 0,1,0,1,4B,22,2,22; 7210 / 0,1,0,0,4B,22,2,22; 7300 / 0,1,0,1,4B,22,2,22; 7390 / 1,1,0,1,4B,22,2,22; 7400 / 1,1,0,1,4B,D7,2,22; 7420 / 1,1,0,1,ZZ,D7,2,22; 7480 / 1,1,0,0,ZZ,D7,2,22; 7570 / 1,1,0,1,ZZ,D7,2,22; 7660 / 1,1,0,0,ZZ,D7,2,22; 7750 / 1,1,0,1,ZZ,D7,2,22; 7840 / 0,1,0,1,ZZ,D7,3,33; 7850 / 0,1,0,1,ZZ,22,3,33; 7870 / 0,1,0,1,4B,22,3,33; 7930 / 0,1,0,0,4B,22,3,33; 8020 / 0,1,0,1,4B,22,3,33; 8110 / 1,1,0,1,4B,22,3,33; 8120 / 1,1,0,1,4B,D7,3,33; 8140 / 1,1,0,1,ZZ,D7,3,33; 8200 / 1,1,0,0,ZZ,D7,3,33; 8290 / 1,1,0,1,ZZ,D7,3,33; 8380 / 1,1,0,0,ZZ,D7,3,33; 8470 / 1,1,0,1,ZZ,D7,3,33; 8560 / 0,1,0,1,ZZ,D7,4,44; 8570 / 0,1,0,1,ZZ,22,4,44; 8590 / 0,1,0,1,4B,22,4,44; 8650 / 0,1,0,0,4B,22,4,44; 8740 / 0,1,0,1,4B,22,4,44; 8830 / 1,1,0,1,4B,22,4,44; 8840 / 1,1,0,1,4B,D7,4,44; 8860 / 1,1,0,1,ZZ,D7,4,44; 8920 / 1,1,0,0,ZZ,D7,4,44; 9010 / 1,1,0,1,ZZ,D7,4,44; 9100 / 1,1,0,0,ZZ,D7,4,44; 9190 / 1,1,0,1,ZZ,D7,4,44; 9280 / 0,1,0,1,ZZ,D7,5,55; 9290 / 0,1,0,1,ZZ,22,5,55; 9310 / 0,1,0,1,4B,22,5,55; 9370 / 0,1,0,0,4B,22,5,55; 9460 / 0,1,0,1,4B,22,5,55; 9550 / 1,1,0,1,4B,22,5,55; 9560 / 1,1,0,1,4B,D7,5,55; 9580 / 1,1,0,1,ZZ,D7,5,55; 9640 / 1,1,0,0,ZZ,D7,5,55; 9730 / 1,1,0,1,ZZ,D7,5,55; 9820 / 1,1,0,0,ZZ,D7,5,55; 9910 / 1,1,0,1,ZZ,D7,5,55; 10000 / 0,1,0,1,ZZ,D7,6,66; 10010 / 0,1,0,1,ZZ,22,6,66; 10030 / 0,1,0,1,4B,22,6,66; 10090 / 0,1,0,0,4B,22,6,66; 10180 / 0,1,0,1,4B,22,6,66; 10270 / 1,1,0,1,4B,22,6,66; 10280 / 1,1,0,1,4B,D7,6,66; 10300 / 1,1,0,1,ZZ,D7,6,66; 10360 / 1,1,0,0,ZZ,D7,6,66; 10450 / 1,1,0,1,ZZ,D7,6,66; 10540 / 1,1,0,0,ZZ,D7,6,66; 10630 / 1,1,0,1,ZZ,D7,6,66; 10720 / 0,1,0,1,ZZ,D7,7,77; 10730 / 0,1,0,1,ZZ,22,7,77; 10750 / 0,1,0,1,4B,22,7,77; 10810 / 0,1,0,0,4B,22,7,77; 10900 / 0,1,0,1,4B,22,7,77; 10990 / 1,1,0,1,4B,22,7,77; 11000 / 1,1,0,1,4B,D7,7,77; 11020 / 1,1,0,1,ZZ,D7,7,77; 11080 / 1,1,0,0,ZZ,D7,7,77; 11170 / 1,1,0,1,ZZ,D7,7,77; 11260 / 1,1,0,0,ZZ,D7,7,77; 11350 / 1,1,0,1,ZZ,D7,7,77; 11440 / 0,1,0,1,ZZ,D7,8,88; 11450 / 0,1,0,1,ZZ,22,8,88; 11470 / 0,1,0,1,4B,22,8,88; 11530 / 0,1,0,0,4B,22,8,88; 11620 / 0,1,0,1,4B,22,8,88; 11710 / 1,1,0,1,4B,22,8,88; 11720 / 1,1,0,1,4B,D7,8,88; 11740 / 1,1,0,1,ZZ,D7,8,88; 11800 / 1,1,0,0,ZZ,D7,8,88; 11890 / 1,1,0,1,ZZ,D7,8,88; 11980 / 1,1,0,0,ZZ,D7,8,88; 12070 / 1,1,0,1,ZZ,D7,8,88; 12160 / 0,1,0,1,ZZ,D7,9,99; 12170 / 0,1,0,1,ZZ,22,9,99; 12190 / 0,1,0,1,4B,22,9,99; 12250 / 0,1,0,0,4B,22,9,99; 12340 / 0,1,0,1,4B,22,9,99; 12430 / 1,1,0,1,4B,22,9,99; 12440 / 1,1,0,1,4B,D7,9,99; 12460 / 1,1,0,1,ZZ,D7,9,99; 12520 / 1,1,0,0,ZZ,D7,9,99; 12610 / 1,1,0,1,ZZ,D7,9,99; 12700 / 1,1,0,0,ZZ,D7,9,99; 12790 / 1,1,0,1,ZZ,D7,9,99; 12880 / 0,1,0,1,ZZ,D7,A,AA; 12890 / 0,1,0,1,ZZ,22,A,AA; 12910 / 0,1,0,1,4B,22,A,AA; 12970 / 0,1,0,0,4B,22,A,AA; 13060 / 0,1,0,1,4B,22,A,AA; 13150 / 1,1,0,1,4B,22,A,AA; 13160 / 1,1,0,1,4B,D7,A,AA; 13180 / 1,1,0,1,ZZ,D7,A,AA; 13240 / 1,1,0,0,ZZ,D7,A,AA; 13330 / 1,1,0,1,ZZ,D7,A,AA; 13420 / 1,1,0,0,ZZ,D7,A,AA; 13510 / 1,1,0,1,ZZ,D7,A,AA; 13600 / 0,1,0,1,ZZ,D7,B,BB; 13610 / 0,1,0,1,ZZ,22,B,BB; 13630 / 0,1,0,1,4B,22,B,BB; 13690 / 0,1,0,0,4B,22,B,BB; 13780 / 0,1,0,1,4B,22,B,BB; 13870 / 1,1,0,1,4B,22,B,BB; 13880 / 1,1,0,1,4B,D7,B,BB; 13900 / 1,1,0,1,ZZ,D7,B,BB; 13960 / 1,1,0,0,ZZ,D7,B,BB; 14050 / 1,1,0,1,ZZ,D7,B,BB; 14140 / 1,1,0,0,ZZ,D7,B,BB; 14230 / 1,1,0,1,ZZ,D7,B,BB; 14320 / 0,1,0,1,ZZ,D7,C,CC; 14330 / 0,1,0,1,ZZ,22,C,CC; 14350 / 0,1,0,1,4B,22,C,CC; 14410 / 0,1,0,0,4B,22,C,CC; 14500 / 0,1,0,1,4B,22,C,CC; 14590 / 1,1,0,1,4B,22,C,CC; 14600 / 1,1,0,1,4B,D7,C,CC; 14620 / 1,1,0,1,ZZ,D7,C,CC; 14680 / 1,1,0,0,ZZ,D7,C,CC; 14770 / 1,1,0,1,ZZ,D7,C,CC; 14860 / 1,1,0,0,ZZ,D7,C,CC; 14950 / 1,1,0,1,ZZ,D7,C,CC; 15040 / 0,1,0,1,ZZ,D7,D,DD; 15050 / 0,1,0,1,ZZ,22,D,DD; 15070 / 0,1,0,1,4B,22,D,DD; 15130 / 0,1,0,0,4B,22,D,DD; 15220 / 0,1,0,1,4B,22,D,DD; 15310 / 1,1,0,1,4B,22,D,DD; 15320 / 1,1,0,1,4B,D7,D,DD; 15340 / 1,1,0,1,ZZ,D7,D,DD; 15400 / 1,1,0,0,ZZ,D7,D,DD; 15490 / 1,1,0,1,ZZ,D7,D,DD; 15580 / 1,1,0,0,ZZ,D7,D,DD; 15670 / 1,1,0,1,ZZ,D7,D,DD; 15760 / 0,1,0,1,ZZ,D7,E,EE; 15770 / 0,1,0,1,ZZ,22,E,EE; 15790 / 0,1,0,1,4B,22,E,EE; 15850 / 0,1,0,0,4B,22,E,EE; 15940 / 0,1,0,1,4B,22,E,EE; 16030 / 1,1,0,1,4B,22,E,EE; 16040 / 1,1,0,1,4B,D7,E,EE; 16060 / 1,1,0,1,ZZ,D7,E,EE; 16120 / 1,1,0,0,ZZ,D7,E,EE; 16210 / 1,1,0,1,ZZ,D7,E,EE; 16300 / 1,1,0,0,ZZ,D7,E,EE; 16390 / 1,1,0,1,ZZ,D7,E,EE; 16480 / 0,1,0,1,ZZ,D7,F,FF; 16490 / 0,1,0,1,ZZ,22,F,FF; 16510 / 0,1,0,1,4B,22,F,FF; 16570 / 0,1,0,0,4B,22,F,FF; 16660 / 0,1,0,1,4B,22,F,FF; 16750 / 1,1,0,1,4B,22,F,FF; 16760 / 1,1,0,1,4B,D7,F,FF; 16780 / 1,1,0,1,ZZ,D7,F,FF; 16840 / 1,1,0,0,ZZ,D7,F,FF; 16930 / 1,1,0,1,ZZ,D7,F,FF; 17020 / 1,1,0,0,ZZ,D7,F,FF; 17110 / 1,1,0,1,ZZ,D7,F,FF; 17200 / 0,0,1,1,ZZ,D7,4,FF; 17210 / 0,0,1,1,ZZ,00,4,FF; 17230 / 0,0,1,1,01,00,4,FF; 17290 / 0,0,1,0,01,00,4,FF; 17380 / 0,0,1,1,01,00,4,FF; 17480 / 0,0,1,1,01,01,4,FF; 17500 / 0,0,1,1,02,01,4,FF; 17560 / 0,0,1,0,02,01,4,FF; 17650 / 0,0,1,1,02,01,4,FF; 17750 / 0,0,1,1,02,02,4,FF; 17770 / 0,0,1,1,04,02,4,FF; 17830 / 0,0,1,0,04,02,4,FF; 17920 / 0,0,1,1,04,02,4,FF; 18020 / 0,0,1,1,04,03,4,FF; 18040 / 0,0,1,1,08,03,4,FF; 18100 / 0,0,1,0,08,03,4,FF; 18190 / 0,0,1,1,08,03,4,FF; 18290 / 0,0,1,1,08,04,4,FF; 18310 / 0,0,1,1,10,04,4,FF; 18370 / 0,0,1,0,10,04,4,FF; 18460 / 0,0,1,1,10,04,4,FF; 18560 / 0,0,1,1,10,05,4,FF; 18580 / 0,0,1,1,20,05,4,FF; 18640 / 0,0,1,0,20,05,4,FF; 18730 / 0,0,1,1,20,05,4,FF; 18830 / 0,0,1,1,20,06,4,FF; 18850 / 0,0,1,1,40,06,4,FF; 18910 / 0,0,1,0,40,06,4,FF; 19000 / 0,0,1,1,40,06,4,FF; 19100 / 0,0,1,1,40,07,4,FF; 19120 / 0,0,1,1,80,07,4,FF; 19180 / 0,0,1,0,80,07,4,FF; 19270 / 0,0,1,1,80,07,4,FF; 19370 / 0,0,1,1,80,08,4,FF; 19390 / 0,0,1,1,00,08,4,FF; 19450 / 0,0,1,0,00,08,4,FF; 19540 / 0,0,1,1,00,08,4,FF; 19640 / 0,0,1,1,00,09,4,FF; 19720 / 0,0,1,0,00,09,4,FF; 19810 / 0,0,1,1,00,09,4,FF; 19910 / 0,0,1,1,00,0A,4,FF; 19990 / 0,0,1,0,00,0A,4,FF; 20080 / 0,0,1,1,00,0A,4,FF; 20180 / 0,0,1,1,00,0B,4,FF; 20260 / 0,0,1,0,00,0B,4,FF; 20350 / 0,0,1,1,00,0B,4,FF; 20450 / 0,0,1,1,00,0C,4,FF; 20530 / 0,0,1,0,00,0C,4,FF; 20620 / 0,0,1,1,00,0C,4,FF; 20720 / 0,0,1,1,00,0D,4,FF; 20800 / 0,0,1,0,00,0D,4,FF; 20890 / 0,0,1,1,00,0D,4,FF; 20990 / 0,0,1,1,00,0E,4,FF; 21070 / 0,0,1,0,00,0E,4,FF; 21160 / 0,0,1,1,00,0E,4,FF; 21260 / 0,0,1,1,00,0F,4,FF; 21340 / 0,0,1,0,00,0F,4,FF; 21430 / 0,0,1,1,00,0F,4,FF; 21530 / 0,0,1,1,00,10,4,FF; 21610 / 0,0,1,0,00,10,4,FF; 21700 / 0,0,1,1,00,10,4,FF; 21800 / 0,0,1,1,00,11,4,FF; 21880 / 0,0,1,0,00,11,4,FF; 21970 / 0,0,1,1,00,11,4,FF; 22070 / 0,0,1,1,00,12,4,FF; 22150 / 0,0,1,0,00,12,4,FF; 22240 / 0,0,1,1,00,12,4,FF; END_TAB_TRACE; END. ZZ,D7,2,22; 7840 / 0,1,0,1,ZZ,D7,3,33; 7850 / 0,1,0,1,ZZ,22,3,33; 7870 / 0,1,0,1,4B,22,3,33; 7930 / 0,1,0,0,4B,22,3,33; 8020 / 0,1,0,1,4B,22,3,33; 8110 / 1,1,0,1,4B,22,3,33; 8120 / 1,1,0,1,4B,D7,3,33; 8140 / 1,1,0,1,ZZ,D7,3,vgen_examples/exam_15.x6 644 143 12 4262 6116505060 10456 Q2; Q1; Q0; OUT2; OUT1; $ 0 0 0 0 0 0 100 0 1 0 0 0 200 0 0 1 0 0 300 0 1 1 0 0 400 1 0 0 0 0 500 1 1 0 0 1 600 1 0 1 1 0 700 1 1 1 0 0 800 0 0 0 0 0 900 0 1 0 0 0 1000 0 0 1 0 0 1100 0 1 1 0 0 1200 1 0 0 0 0 1300 1 1 0 0 1 1400 1 0 1 1 0 1500 1 1 1 0 0 1600 0 0 0 0 0 1700 0 1 0 0 0 1800 0 0 1 0 0 1900 0 1 1 0 0 2000 1 0 0 0 0 2100 1 1 0 0 1 2200 1 0 1 1 0 2300 1 1 1 0 0 2400 0 0 0 0 0 2500 0 1 0 0 0 2600 0 0 1 0 0 2700 0 1 1 0 0 2800 1 0 0 0 0 2900 1 1 0 0 1 3000 1 0 1 1 0 3100 1 1 1 0 0 3200 0 0 0 0 0 3300 0 1 0 0 0 3400 0 0 1 0 0 3500 0 1 1 0 0 3600 1 0 0 0 0 3700 1 1 0 0 1 3800 1 0 1 1 0 3900 1 1 1 0 0 4000 0 0 0 0 0 4100 0 1 0 0 0 4200 0 0 1 0 0 4300 0 1 1 0 0 4400 1 0 0 0 0 4500 1 1 0 0 1 4600 1 0 1 1 0 4700 1 1 1 0 0 4800 0 0 0 0 0 4900 0 1 0 0 0 5000 0 0 1 0 0 5100 0 1 1 0 0 5200 1 0 0 0 0 5300 1 1 0 0 1 5400 1 0 1 1 0 5500 1 1 1 0 0 5600 0 0 0 0 0 5700 0 1 0 0 0 5800 0 0 1 0 0 5900 0 1 1 0 0 6000 1 0 0 0 0 6100 1 1 0 0 1 6200 1 0 1 1 0 6300 1 1 1 0 0 6400 0 0 0 0 0 6500 0 1 0 0 0 6600 0 0 1 0 0 6700 0 1 1 0 0 6800 1 0 0 0 0 6900 1 1 0 0 1 7000 1 0 1 1 0 7100 1 1 1 0 0 7200 0 0 0 0 0 7300 0 1 0 0 0 7400 0 0 1 0 0 7500 0 1 1 0 0 7600 1 0 0 0 0 7700 1 1 0 0 1 7800 1 0 1 1 0 7900 1 1 1 0 0 8000 0 0 0 0 0 8100 0 1 0 0 0 8200 0 0 1 0 0 8300 0 1 1 0 0 8400 1 0 0 0 0 8500 1 1 0 0 1 8600 1 0 1 1 0 8700 1 1 1 0 0 8800 0 0 0 0 0 8900 0 1 0 0 0 9000 0 0 1 0 0 9100 0 1 1 0 0 9200 1 0 0 0 0 9300 1 1 0 0 1 9400 1 0 1 1 0 9500 1 1 1 0 0 9600 0 0 0 0 0 9700 0 1 0 0 0 9800 0 0 1 0 0 9900 0 1 1 0 0 vgen_examples/exam_16 644 143 12 1314 6116505060 10116 { FILE: exam_16 PURPOSE: Demonstrate use of WAVEFORM and PINTYPE for generating clocks. DEVICE: SIMULATOR: HILO NOTES: This code might be a part of a larger program. Also, the SYS_CLOCK use is illustrated - this is available on some interfaces. } INPUTS LCK LCK1 LCK2 LCK3 LCK4 ; SIMULATOR HILO; title "test11"; SYS_CLOCK CK 125 75 1; INT I; CYCLE 200; WAVEFORM LCK 350 50 1 100; WAVEFORM LCK1 299 99 0 100; PINTYPE RZ LCK2 @ 0 100, RO LCK3 @ 50 150, RC LCK4 @ 100 200; { INITIALIZE EVERYTHING } LCK LCK1 LCK3 LCK4 = LO; LCK2 = HI; VGEN; { Initiate timing } PINTIMING ON LCK2, LCK3, LCK4; { 50 cycles } VGEN(50); END vgen_examples/exam_2 644 143 12 4607 6116505060 10041 { FILE: EXAM_2 PURPOSE: Demonstrate the use of logic to model pin relationships. Uses the 'fork' command to generate two seperate timelines. DEVICE: Logic Chip SIMULATOR: SPICE The spice simulator accepts several parameters governing the analog model. See the stimulus interface guide for additional information. NOTES: There are two seperate time lines used in this simulation. } {Define the pin names} {in the spice simulator, node numbers can be assigned to the pins for use in the output stimulus. The following pin definition assigns node 3 to Q2, node 4 to Q1, node 5 to Q0, node 6 to the bus out[5:0], and node 7 to the bus ByteBus} INPUTS Q2 "3" Q1 "4" Q0 "5" OUT[5:0] "6" ; inputs ByteBus[8:0] "7"; {declare analog pins, these are specific to the spice simulator and can not be used with other simulators.} analog out vmax = 1.0 volts, vmin = -1.0 volts; analog ByteBus vmax = 3.0 volts, vmin = 0 volts; {cycle sets the time increment for each output vector} cycle 100; {define the simulator to be used} {the spice simulator accepts several parameters. These parameters can also be specified in a file, as some are in this example. The file is specified using the TechFile="exam_2.tech" parameter.} simulator spice UNITS = "NS", TechFile="exam_2.tech", trise = MAX, tfall = MAX, vih = TYP, vil = Typ , triz = max ; {Integer variables are declared. IN0,IN2 are used to hold pin states. i is used as a counter} int IN0 IN2, i; {String variable st is declared and initialized. st is used to hold pin states} string st[2]; {The main portion of the vector generation starts here First initialize pins} Q2 Q1 = LO; q0 = 'Z'; {generate startup vector} vgen; {model the logic chip} q0 = 0; for i = 0 until 19 BEGIN IN2 = Q2 ^ (Q0 & Q1); IN0 = Q1 ^ Q0; st[1] = Q2 & Q1 & ~Q0; { 6 } st[0] = Q2 & ~Q1 & Q0; { 5 } out = i ; {generate the appropriate vector} VGEN; Q0 = IN0; Q1 = ~Q1; Q2 = IN2 + i; END; {generate vectors for the bus, which has different timing.} {change to the alternate time line} fork b; {cycle sets the time increment for each output vector} cycle 10; for i=0 until 190 begin {set the bus state} ByteBus = i; {output the vector} vgen; end; END; e used with other simulators.} analog out vmax = 1.0 volts, vmin = -1.0 volts; analog ByteBus vmax = 3.0 volts, vmin = 0vgen_examples/exam_2.tec 644 143 12 605 6116505060 10565 * EXAM_D.TEC * Revision 1.0 * This file specifies some of the parameters for the spice simulator. These * parameters could also be specified as parameters to the simulator command. * MIN MAX UNIT * --- --- ---- trise = 1.0E+00 : 2.0E+00 : NS tfall = 1.0E+00 : 3.0E+00 : NS VIH = 2.0E+00 : 2.4E+00 : V VIL = 0.4E+00 : 8.0E-01 : V TriZ = 3.1E+00 : 3.5E+00 : V vgen_examples/exam_3 644 143 12 7607 6116505060 10045 { FILE: EXAM_3 PURPOSE: Demonstrate subroutines and loops. Buses output in binary instead of the default hex. DEVICE: SIO interface SIMULATOR: VIEWSIM_GEN Produces a vector file and a '.CMD' command file. The command file defines all of the pins as a single vector ('allpins') and reads in the vector file. ie: "vector allpins pin1 pin2 ... pinn bus1 bus2 ... busn" "wfm allpins < *.vec" NOTES: Timing is changed after the initialization vectors. } {Define the pin names} INPUTS SID TST_CLK TST_CLR AM IOM ADR<7..0>; outputs LCK; {cycle sets the time increment for each output vector} CYCLE 200; {define the simulator to be used} SIMULATOR viewsim; {* ViewLogic *} {Set the output for buses to binary radix} BUSFORMAT BIN; {place the pin names vertically as comments every 60 lines in the output file.} HEADER 60; {create string variables to hold pin states} STRING CMD LRC PARM '00'; STRING SYNC '00010110'B; STRING ADDRESS '00110011'B; STRING CMD1 '11000111'B; { WRITE TO REG 7 } STRING CMD2 '10000111'B; { WRITE TO REG 7 - ILLEGAL } STRING CMD3 0; { READ FROM REG 0 } {integer variable declared, used to count then shift all bits from a data byte} INT I; {Subroutine for clock cycle} SUBROUTINE CK_CYC BEGIN {Start of cycle vector} VGEN; {Clock HI and generate vector} TST_CLK=HI; VGEN; {Clock LO and generate vector} TST_CLK=LO; VGEN; END {Subroutine for Latch cycle - 9 pulses} SUBROUTINE LCK_CYC BEGIN REPEAT 9 BEGIN {LCK HI and generate vector} LCK=HI; VGEN; {LCK LO and generate vector} LCK=LO; VGEN; END END {Subroutine to input a byte} SUBROUTINE BYTE_IN(BYTE) BEGIN {for all 8 bits} FOR I = 7 UNTIL 0 BEGIN {Set Serial data to next bit} SID = BYTE > I; {Clock Cycle} CALL CK_CYC; END END {Subroutine to input all bytes} SUBROUTINE ALL_IN BEGIN {Read Sync Byte} CALL BYTE_IN(SYNC); {Read Address Byte} CALL BYTE_IN(ADDRESS); {Read Command Byte} CALL BYTE_IN(CMD); {Read Parameter Byte} CALL BYTE_IN(PARM); {Calculate LRC} LRC = SYNC ^ ADDRESS ^ CMD ^ PARM; {Input LRC Byte} CALL BYTE_IN(LRC); END {The main portion of the vector generation starts here First initialize pins } {Set all but SID to LO, SID to HI} LCK TST_CLK TST_CLR AM IOM ADR[7:0] = LO; SID = HI; {generate a vector} VGEN; {Pulse the TST_CLR pin HI-LO} TST_CLR=1; VGEN; TST_CLR=0; VGEN; {change the cycle time to spped up th interface} CYCLE 100; {Initialize pins for write operation} CMD=CMD1; SID=0; VGEN; {2 LCK Pulses} REPEAT 2 BEGIN LCK=HI; VGEN; LCK=LO; VGEN; END {Read All Bytes} CALL ALL_IN; SID = HI; VGEN; {Latch and read out serial data} CALL LCK_CYC; REPEAT 16 BEGIN CALL CK_CYC; END {Do a second write - illegal for this device} CMD=CMD2; SID=0; VGEN; {2 LCK Pulses} REPEAT 2 BEGIN LCK=HI; VGEN; LCK=LO; VGEN; END {Read All Bytes} CALL ALL_IN; {Latch and read out serial data} SID = HI; VGEN; CALL LCK_CYC; REPEAT 16 BEGIN CALL CK_CYC; END {Third transmission - read REG 0 } CMD=CMD3; SID=0; VGEN; {2 LCK Pulses} REPEAT 2 BEGIN LCK=HI; VGEN; LCK=LO; VGEN; END {Read All Bytes} CALL ALL_IN; {Latch and read out serial data} SID = HI; VGEN; CALL LCK_CYC; REPEAT 16 BEGIN CALL CK_CYC; END END vgen_examples/exam_4 644 143 12 10744 6116505060 10062 { FILE: EXAM_4 PURPOSE: Demonstrate basic pin timing using the 'pulse' and 'pintype' statements. DEVICE: Memory SIMULATOR: VERILOG Produces a stimulus module - input only. NOTES: } {Define the pin names: a[7:0] - input - the address bus (8 bits wide) ce* - input - chip enable (active low) db[7:0] - input - data bus oe* - input - output enable (active low) we* - input - write enable (active low) } inputs a[7:0] ce* db[7:0] oe* we*; {cycle sets the time increment for each output vector} cycle 200; {define the simulator to be used} simulator verilog; {String variables are declared and initialized. These variables will be used to set the state of the data bus} string word1 'AA'; string word2 '55'; string word3 '11'; string word4 '22'; string word5 '33'; string word6 '44'; string word7 '66'; string word8 '88'; string word9 '99'; string z 'zz'; {Integer variables are declared. These will be used as counters for addressing} int i j; {declare a subroutine. This subroutine is used for the write cycle of the memory} subroutine write(address, word) begin {Set the address bus 'a' to the parameter address} a=address; {chip enable low (active), output enable high (tri-state)} ce*=0; oe*=1; {enable a pulse in the write enable line} pulse on we*; {set the databus to the parameter word} db=word; {generate a vector, data write enable low} vgen; {disable the pulse on write enable (write cycle is over) } pulse off we*; {disable the chip} ce*=1; {generate chip disable vector} vgen; end; {declare a subroutine. This subroutine is used for the read cycle of the memory} subroutine read(address) begin {tri-state the databus} {when assigning data to a bus, if a single bit of data is provided, all pins in the bus are assigned the data} db = z; {generate a tri-state vector} vgen; {set the address bus to the address parameter} a=address; {enable the chip} ce*=0; {enable the outputs} oe*=0; {generate the read data vector} vgen; {tri-state outputs and disable chip} oe* ce* = hi; {generate chip disable vector} vgen; end; {The main portion of the vector generation starts here First initialize pins } {address bus to 0;chip disabled, write disabled, outputs disabled/tri-stated} a = lo; ce* oe* we* = hi; db = z; {generate startup vector} vgen; {The vectors are initially used to write data to memory} {By default ce* will be NRZ, changing at the start of the cycle} {the address requires 20ns setup time before ce* goes low} pintype nrz a @ -20; {when writing data, we* pulses low 10ns after ce*, with a 100 ns width} pulse we* 10 100 0; {the data bus requires a 50 ns setup prior to we* going high } pintype NRZ db @60; {enable all pintype timing } pintiming ON a, db; {use the write subroutine to write data into the device} call write(0, 0); call write(1, word1); call write(2, word2); call write(4, word3); call write(8, word4); call write(16, word5); call write(32, word6); call write(64, word7); call write(128, word8); call write(255, word9); {now read these locations} {tri-state the data bus} db=z; {generate tri-state vector} vgen; {the timing needs to be changed for the read cycle} {the address but setup time for read is 30 ns} pintype nrz a @ -30; {call the read subroutine to generate read the written locations.} call read(0); {the for loop uses the shift operator '<' to cycle through the addresses 1,2,4,8,16,32,64,128} for i=0 until 8 begin call read(1 ADR<7..0> MODE<3..0> R/W EXT REP* CLK ; {sets bus output to hex radix (hex is the default)} busformat hex; {cycle sets the time increment for each output vector} CYCLE 100; {define the simulator to be used} SIMULATOR advansim_1076; {create string variables to hold pin states} STRING Z 'ZZ'; STRING TEMP; {integer variable declared, used to count} INT I; STRING Value; {define a table. The table (TBL) is used as a lookup for the memory contents. The table is accessed as an array, with the starting index of zero (ie. the first location: TBL(0) = 0, the second: TBL(1) = 11} TABLE TBL BEGIN 0 11 22 33 44 55 66 77 88 99 'AA' 'BB' 'CC' 'DD' 'EE' 'FF' END; {Subroutine for clock cycle - takes as a parameter the number of clock pulses desired} SUBROUTINE CLOCK (N) BEGIN { pulse the clock pin 'N' times } REPEAT N BEGIN {CLK LO and generate a vector} CLK = LO; VGEN; {CLK HI and generate a vector} CLK = HI; VGEN; END END {Subroutine for write cycle - takes three parameters D - data bus, A - Address Bus, M - Mode} SUBROUTINE WRITE(D, A, M) BEGIN { Set DB, R/W, ADR, and MODE then generate a vector} DB = D; R/W = 0; ADR = A; MODE = M; VGEN; {Clock the device 1 time to latch the write data} CALL CLOCK(1); END {Subroutine for read cycle - takes the address (A) as a parameter} SUBROUTINE READ(A) BEGIN { set the R/W, ADR data and tri-state the databus - then generate a vector} R/W=HI; ADR = A; DB = Z; VGEN; {Clock twice to latch and output the data} CALL CLOCK(2); END {The main portion of the vector generation starts here First initialize pins } DB=Z; ADR=LO; MODE R/W EXT REP* = LO; CLK = HI; {generate a vector} VGEN; {Clock 4 times} CALL CLOCK (4); {Set the MODE pin HI and generate a vector} MODE=1; VGEN; {reduce all timing to 90% of original values (cycle 100 -> cycle 90 ...)} scale = 0.9; {for modes 1 through 15 write the data from th table into address 22h} FOR I=1 UNTIL 16 BEGIN EXT R/W = HI; {write the data, indexing the table by mode into address 22h} Value = TBL(I-1); CALL WRITE(Value, '22'h, I); {Read from location D7h} CALL READ('D7'); END {write 8 consecutive bytes of data} TEMP = 1; EXT = 0; REP* = 1; FOR I = 0 UNTIL 8 BEGIN CALL WRITE(TEMP, I, 4); {shift the data so TEMP is 2 to power of I} TEMP = TEMP < 1; END; {read the 8 consecutive bytes of data} FOR I = 0 UNTIL 8 BEGIN CALL READ(I); END; END vgen_examples/exam_5.vec 644 143 12 16627 6116505060 10645 $DATA_HEADER$ $TYPE$ I/O $FORMAT$ TIME_VALUE $TOTAL_COLUMNS$ 10 24 $BASE$ D B $FIELD$ 1 DB(7:0) 1-8 $FIELD$ 2 ADR(7:0) 9-16 $FIELD$ 3 MODE(3:0) 17-20 $FIELD$ 4 R/W 21 $FIELD$ 5 EXT 22 $FIELD$ 6 REP~ 23 $FIELD$ 7 CLK 24 $END$ 0 ZZZZZZZZ0000000000000001 100 ZZZZZZZZ0000000000000000 200 ZZZZZZZZ0000000000000001 300 ZZZZZZZZ0000000000000000 400 ZZZZZZZZ0000000000000001 500 ZZZZZZZZ0000000000000000 600 ZZZZZZZZ0000000000000001 700 ZZZZZZZZ0000000000000000 800 ZZZZZZZZ0000000000000001 900 ZZZZZZZZ0000000000010001 1000 000000000010001000010101 1090 000000000010001000010100 1180 000000000010001000010101 1270 ZZZZZZZZ1101011100011101 1360 ZZZZZZZZ1101011100011100 1450 ZZZZZZZZ1101011100011101 1540 ZZZZZZZZ1101011100011100 1630 ZZZZZZZZ1101011100011101 1720 000010110010001000100101 1810 000010110010001000100100 1900 000010110010001000100101 1990 ZZZZZZZZ1101011100101101 2080 ZZZZZZZZ1101011100101100 2170 ZZZZZZZZ1101011100101101 2260 ZZZZZZZZ1101011100101100 2350 ZZZZZZZZ1101011100101101 2440 000101100010001000110101 2530 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010000000000011001000011 14410 100000000000011101000011 14500 100000000000011101000010 14590 100000000000011101000011 14680 000000000000100001000011 14770 000000000000100001000010 14860 000000000000100001000011 14950 ZZZZZZZZ0000000001001011 15040 ZZZZZZZZ0000000001001010 15130 ZZZZZZZZ0000000001001011 15220 ZZZZZZZZ0000000001001010 15310 ZZZZZZZZ0000000001001011 15400 ZZZZZZZZ0000000101001011 15490 ZZZZZZZZ0000000101001010 15580 ZZZZZZZZ0000000101001011 15670 ZZZZZZZZ0000000101001010 15760 ZZZZZZZZ0000000101001011 15850 ZZZZZZZZ0000001001001011 15940 ZZZZZZZZ0000001001001010 16030 ZZZZZZZZ0000001001001011 16120 ZZZZZZZZ0000001001001010 16210 ZZZZZZZZ0000001001001011 16300 ZZZZZZZZ0000001101001011 16390 ZZZZZZZZ0000001101001010 16480 ZZZZZZZZ0000001101001011 16570 ZZZZZZZZ0000001101001010 16660 ZZZZZZZZ0000001101001011 16750 ZZZZZZZZ0000010001001011 16840 ZZZZZZZZ0000010001001010 16930 ZZZZZZZZ0000010001001011 17020 ZZZZZZZZ0000010001001010 17110 ZZZZZZZZ0000010001001011 17200 ZZZZZZZZ0000010101001011 17290 ZZZZZZZZ0000010101001010 17380 ZZZZZZZZ0000010101001011 17470 ZZZZZZZZ0000010101001010 17560 ZZZZZZZZ0000010101001011 17650 ZZZZZZZZ0000011001001011 17740 ZZZZZZZZ0000011001001010 17830 ZZZZZZZZ0000011001001011 17920 ZZZZZZZZ0000011001001010 18010 ZZZZZZZZ0000011001001011 18100 ZZZZZZZZ0000011101001011 18190 ZZZZZZZZ0000011101001010 18280 ZZZZZZZZ0000011101001011 18370 ZZZZZZZZ0000011101001010 18460 ZZZZZZZZ0000011101001011 18550 ZZZZZZZZ0000100001001011 18640 ZZZZZZZZ0000100001001010 18730 ZZZZZZZZ0000100001001011 18820 ZZZZZZZZ0000100001001010 18910 ZZZZZZZZ0000100001001011 vgen_examples/exam_6 644 143 12 4406 6116505060 10042 { FILE: EXAM_6 PURPOSE: demonstrate shift/logic operations DEVICE: 74164 8 bit parallel-out serial shift register SIMULATOR: TIMEMILL uses EPIC .vec format. Pin output order is as defined in this source file. NOTES: } {define the pin names} {data in} INPUTS INB, INA; {clear} INPUTS CLR; {Clock} INPUTS CLK; {Data Outputs} OUTPUTS OUT[7:0]; {setup counter variables} INT i,j; {output state} int OutVal; {FUNCTION TABLE CLR CLK INA INB OUT L X X X L H L X X Q H C H H Q[6:0],H H C L X Q[6:0],L H C X L Q[6:0],L } {cycle sets the time increment for each output vector} CYCLE 100; {define the simulator to be used} SIMULATOR TIMEMILL; {subroutine to generate a clock pulse - takes the expected output as a parameter} SUBROUTINE CLOCK(EXP) BEGIN {Clock Hi and generate vector} CLK = HI; VGEN; {set output state and clock lo} OutVal = EXP; OUT = OutVal; CLK = LO; VGEN; OUT = 'XX'; END {Subroutine to clear the device} SUBROUTINE CLEAR BEGIN {Clear LO} CLR = LO; VGEN; {Outputs go LO} OutVal = 0; OUT = OutVal; VGEN; {Clear HI} CLR = HI; VGEN; END {Subroutine to shift a one into the device} SUBROUTINE SHIFTONE BEGIN {Both inputs to HI} INA INB = HI; VGEN; {clk in} {output in current value - shifted left and bit0 set to 1} CALL CLOCK((OutVal<1)|1); END; {Subroutine to shift a zero into the device} SUBROUTINE SHIFTZERO BEGIN {One inputs to LO} INA = LO; VGEN; {clk in} {output in current value - shifted left and bit0 set to 0} CALL CLOCK((OutVal<1)); END; {The main portion of the vector generation starts here First initialize pins } INA INB CLK CLR = HI; OUT = 'XX'; VGEN; {Clear the device} call CLEAR; {shift a one through the device} {first bit to one} CALL SHIFTONE; {and shift through device} for i=0 until 7 BEGIN CALL SHIFTZERO END; {SHIFT ALL HIGHS in} for i=0 until 8 BEGIN CALL SHIFTONE; END; {Shift a zero through the device} {first bit to zero} CALL SHIFTZERO; {and shift through device} for i=0 until 7 BEGIN CALL SHIFTONE END; END vgen_examples/exam_7 644 143 12 7550 6116505060 10046 { FILE: EXAM_7 PURPOSE: demonstrate switch (Case) operations DEVICE: 74184 BCD to BINARY and 74185 BINARY to BCD Converter SIMULATOR: VHDL_TB Produces a VHDL test bench with stimulus and checks for expected output states. NOTES: } {define the pin names} {data in} INPUTS IN[4:0]; {enable} INPUTS EN; {Data Outputs} OUTPUTS OUT[7:0]; {setup counter variables} INT i; {FUNCTION TABLE 6 bit BCD -> BINARY MSD LSD IN[4] IN[3] IN[2] IN[1] IN[0] LSB | | | | | | \|/ \|/ \|/ \|/ \|/ \|/ OUT[4] OUT[3] OUT[2] OUT[1] OUT[0] 2^5 2^4 2^3 2^2 2^1 2^0 NOTE - LSB of output is equivilant to IN[0] and is not part of the output (EN = 0, with EN = 1, all outputs are H) BCD IN[4:0] OUT[4:0] 0-1 0 0 2-3 1 1 4-5 2 2 6-7 3 3 8-9 4 4 10-11 8 5 12-13 9 6 14-15 A 7 16-17 B 8 18-19 C 9 20-21 10 A 22-23 11 B 24-25 12 C 26-27 13 D 28-29 14 E 30-31 18 F 32-33 19 10 34-35 1A 11 36-37 1B 12 38-39 1C 13 6 bit BINARY to BCD 2^5 2^4 2^3 2^2 2^1 2^0 IN[4] IN[3] IN[2] IN[1] IN[0] LSB | | | | | | \|/ \|/ \|/ \|/ \|/ \|/ OUT[4] OUT[3] OUT[2] OUT[1] OUT[0] LSB MSD LSD BINARY IN[4:0] OUT[7:0] 0-1 0 C0 2-3 1 C1 4-5 2 C2 6-7 3 C3 8-9 4 C4 A-B 5 C8 C-D 6 C9 E-F 7 CA 10-11 8 CB 12-13 9 CC 14-15 A D0 16-17 B D1 18-19 C D2 1A-1B D D3 1C-1D E D4 1E-1F F D8 20-21 10 D9 22-23 11 DA 24-25 12 DB 26-27 13 DC 28-29 14 E0 2A-2B 15 E1 2C-2D 16 E2 2E-2F 17 E3 30-31 18 E4 32-33 19 E8 34-35 1A E9 36-37 1B EA 38-39 1C EB 3A-3B 1D EC 3C-3D 1E F0 3E-3F 1F F1 } {cycle sets the time increment for each output vector} CYCLE 100; {When to strobe outputs} pintype stb out @ 90; pintiming on out; {define the simulator to be used + parameters} SIMULATOR vhdl_tb architecture="beowolf"; {The main portion of the vector generation starts here First initialize pins } IN = LO; EN = HI; OUT = HI; VGEN; {Enable the device} EN = LO; VGEN; OUT = LO; VGEN; {count through BCD Numbers} {0 -> 1C} for i=0 until 29 BEGIN {check for BCD jump} if (i&7)\>\4 then i = i+3; {set inputs} IN = i; VGEN; {set lower value} OUT = I&7; {calculate MSD} {use i[4:3]} switch (i>3) BEGIN case 0: break; case 1: OUT = OUT + 5; break; case 2: OUT = OUT +10; break; case 3: OUT = OUT +15; break; END; {set outputs} VGEN; END; {count through BINARY Numbers} {0->1f} for i=0 until 31 BEGIN {set inputs} IN = i; VGEN; switch (i/5) BEGIN case 0: OUT = i; break; case 1: OUT = i + 3; break; case 2: OUT = i + 6; break; case 3: OUT = i + 9; break; case 4: OUT = i + 12; break; case 5: OUT = i + 15; break; case 6: OUT = i + 18; break; END; {set outputs} Out = Out | 'C0'h; VGEN; END; END vgen_examples/exam_7.vec 644 143 12 36325 6116505060 10644 -- DESIGN NAME: exam_7.vec -- FILE NAME: exam_7.vec -- COMPILATION DATE: Tue Aug 2 12:58:11 PDT 1994 ENTITY exam_7.vec_tb IS END exam_7.vec_tb; ARCHITECTURE beowolf OF exam_7.vec_tb IS -- *** Results Arrays to hold expected output states *** TYPE out_Vector2 IS ARRAY (7 DOWNTO 0) of BIT ; SIGNAL r_out2 : out_Vector2; -- *** Signal Declarations *** SIGNAL EN : BIT ; SIGNAL IN : BIT_VECTOR(4 DOWNTO 0); SIGNAL OUT : BIT_VECTOR(7 DOWNTO 0); -- *** Procedures for checking output states *** PROCEDURE i_check_out2 ( e_out2, r_out2, m_out2 : IN out_Vector2; sim_ok : INOUT BOOLEAN ) IS VARIABLE index : INTEGER; VARIABLE compare : BOOLEAN; BEGIN compare := TRUE; FOR index IN 7 DOWNTO 0 LOOP IF (m_out2(index) = '1') THEN IF (e_out2(index) /= r_out2(index)) THEN sim_ok := FALSE; compare := FALSE; EXIT; END IF; END IF; END LOOP; ASSERT (compare = TRUE) REPORT "INCORRECT RESPONSE FOR PRIMARY OUTPUTS" SEVERITY ERROR; END i_check_out2 ; -- *** Component Declaration *** COMPONENT exam_7.vec PORT ( IN : IN BIT_VECTOR(4 DOWNTO 0); EN : IN BIT; OUT : OUT BIT_VECTOR(7 DOWNTO 0)); END COMPONENT; BEGIN -- *** Process to map Output Signals to Results Arrays *** PROCESS ( OUT) BEGIN r_out2(7) <= OUT(7); r_out2(6) <= OUT(6); r_out2(5) <= OUT(5); r_out2(4) <= OUT(4); r_out2(3) <= OUT(3); r_out2(2) <= OUT(2); r_out2(1) <= OUT(1); r_out2(0) <= OUT(0); END PROCESS; -- *** Main Process for state assignments & checking *** PROCESS VARIABLE compare, sim_ok : BOOLEAN; VARIABLE e_out2, m_out2 : out_Vector2; begin sim_ok := TRUE; wait for 0 ns; -- 0 IN <= ('0','0','0','0','0'); EN <= ('1'); wait for 90 ns; -- 90 e_out2 := ('1','1','1','1','1','1','1','1'); m_out2 := ('1','1','1','1','1','1','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 100 EN <= ('0'); wait for 90 ns; -- 190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 290 e_out2 := ('0','0','0','0','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 490 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 500 IN <= ('0','0','0','0','1'); wait for 90 ns; -- 590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 690 e_out2 := ('0','0','0','0','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 700 IN <= ('0','0','0','1','0'); wait for 90 ns; -- 790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 890 e_out2 := ('0','0','0','0','0','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 900 IN <= ('0','0','0','1','1'); wait for 90 ns; -- 990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 1090 e_out2 := ('0','0','0','0','0','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 1100 IN <= ('0','0','1','0','0'); wait for 90 ns; -- 1190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 1290 e_out2 := ('0','0','0','0','0','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 1300 IN <= ('0','1','0','0','0'); wait for 90 ns; -- 1390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 1490 e_out2 := ('0','0','0','0','0','1','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 1500 IN <= ('0','1','0','0','1'); wait for 90 ns; -- 1590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 1690 e_out2 := ('0','0','0','0','0','1','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 1700 IN <= ('0','1','0','1','0'); wait for 90 ns; -- 1790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 1890 e_out2 := ('0','0','0','0','0','1','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 1900 IN <= ('0','1','0','1','1'); wait for 90 ns; -- 1990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 2090 e_out2 := ('0','0','0','0','1','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 2100 IN <= ('0','1','1','0','0'); wait for 90 ns; -- 2190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 2290 e_out2 := ('0','0','0','0','1','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 2300 IN <= ('1','0','0','0','0'); wait for 90 ns; -- 2390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 2490 e_out2 := ('0','0','0','0','1','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 2500 IN <= ('1','0','0','0','1'); wait for 90 ns; -- 2590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 2690 e_out2 := ('0','0','0','0','1','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 2700 IN <= ('1','0','0','1','0'); wait for 90 ns; -- 2790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 2890 e_out2 := ('0','0','0','0','1','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 2900 IN <= ('1','0','0','1','1'); wait for 90 ns; -- 2990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 3090 e_out2 := ('0','0','0','0','1','1','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 3100 IN <= ('1','0','1','0','0'); wait for 90 ns; -- 3190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 3290 e_out2 := ('0','0','0','0','1','1','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 3300 IN <= ('1','1','0','0','0'); wait for 90 ns; -- 3390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 3490 e_out2 := ('0','0','0','0','1','1','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 3500 IN <= ('1','1','0','0','1'); wait for 90 ns; -- 3590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 3690 e_out2 := ('0','0','0','1','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 3700 IN <= ('1','1','0','1','0'); wait for 90 ns; -- 3790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 3890 e_out2 := ('0','0','0','1','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 3900 IN <= ('1','1','0','1','1'); wait for 90 ns; -- 3990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4090 e_out2 := ('0','0','0','1','0','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 4100 IN <= ('1','1','1','0','0'); wait for 90 ns; -- 4190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4290 e_out2 := ('0','0','0','1','0','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 4300 IN <= ('0','0','0','0','0'); wait for 90 ns; -- 4390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4490 e_out2 := ('0','0','0','0','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4690 e_out2 := ('1','1','0','0','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 4700 IN <= ('0','0','0','0','1'); wait for 90 ns; -- 4790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4890 e_out2 := ('1','1','0','0','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 4900 IN <= ('0','0','0','1','0'); wait for 90 ns; -- 4990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 5090 e_out2 := ('1','1','0','0','0','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 5100 IN <= ('0','0','0','1','1'); wait for 90 ns; -- 5190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 5290 e_out2 := ('1','1','0','0','0','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 5300 IN <= ('0','0','1','0','0'); wait for 90 ns; -- 5390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 5490 e_out2 := ('1','1','0','0','0','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 5500 IN <= ('0','0','1','0','1'); wait for 90 ns; -- 5590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 5690 e_out2 := ('1','1','0','0','1','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 5700 IN <= ('0','0','1','1','0'); wait for 90 ns; -- 5790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 5890 e_out2 := ('1','1','0','0','1','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 5900 IN <= ('0','0','1','1','1'); wait for 90 ns; -- 5990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 6090 e_out2 := ('1','1','0','0','1','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 6100 IN <= ('0','1','0','0','0'); wait for 90 ns; -- 6190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 6290 e_out2 := ('1','1','0','0','1','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 6300 IN <= ('0','1','0','0','1'); wait for 90 ns; -- 6390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 6490 e_out2 := ('1','1','0','0','1','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 6500 IN <= ('0','1','0','1','0'); wait for 90 ns; -- 6590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 6690 e_out2 := ('1','1','0','1','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 6700 IN <= ('0','1','0','1','1'); wait for 90 ns; -- 6790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 6890 e_out2 := ('1','1','0','1','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 6900 IN <= ('0','1','1','0','0'); wait for 90 ns; -- 6990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 7090 e_out2 := ('1','1','0','1','0','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 7100 IN <= ('0','1','1','0','1'); wait for 90 ns; -- 7190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 7290 e_out2 := ('1','1','0','1','0','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 7300 IN <= ('0','1','1','1','0'); wait for 90 ns; -- 7390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 7490 e_out2 := ('1','1','0','1','0','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 7500 IN <= ('0','1','1','1','1'); wait for 90 ns; -- 7590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 7690 e_out2 := ('1','1','0','1','1','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 7700 IN <= ('1','0','0','0','0'); wait for 90 ns; -- 7790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 7890 e_out2 := ('1','1','0','1','1','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 7900 IN <= ('1','0','0','0','1'); wait for 90 ns; -- 7990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 8090 e_out2 := ('1','1','0','1','1','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 8100 IN <= ('1','0','0','1','0'); wait for 90 ns; -- 8190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 8290 e_out2 := ('1','1','0','1','1','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 8300 IN <= ('1','0','0','1','1'); wait for 90 ns; -- 8390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 8490 e_out2 := ('1','1','0','1','1','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 8500 IN <= ('1','0','1','0','0'); wait for 90 ns; -- 8590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 8690 e_out2 := ('1','1','1','0','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 8700 IN <= ('1','0','1','0','1'); wait for 90 ns; -- 8790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 8890 e_out2 := ('1','1','1','0','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 8900 IN <= ('1','0','1','1','0'); wait for 90 ns; -- 8990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 9090 e_out2 := ('1','1','1','0','0','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 9100 IN <= ('1','0','1','1','1'); wait for 90 ns; -- 9190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 9290 e_out2 := ('1','1','1','0','0','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 9300 IN <= ('1','1','0','0','0'); wait for 90 ns; -- 9390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 9490 e_out2 := ('1','1','1','0','0','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 9500 IN <= ('1','1','0','0','1'); wait for 90 ns; -- 9590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 9690 e_out2 := ('1','1','1','0','1','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 9700 IN <= ('1','1','0','1','0'); wait for 90 ns; -- 9790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 9890 e_out2 := ('1','1','1','0','1','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 9900 IN <= ('1','1','0','1','1'); wait for 90 ns; -- 9990 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 10090 e_out2 := ('1','1','1','0','1','0','1','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 10100 IN <= ('1','1','1','0','0'); wait for 90 ns; -- 10190 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 10290 e_out2 := ('1','1','1','0','1','0','1','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 10300 IN <= ('1','1','1','0','1'); wait for 90 ns; -- 10390 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 10490 e_out2 := ('1','1','1','0','1','1','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 10500 IN <= ('1','1','1','1','0'); wait for 90 ns; -- 10590 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 10690 e_out2 := ('1','1','1','1','0','0','0','0'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 10700 IN <= ('1','1','1','1','1'); wait for 90 ns; -- 10790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 10890 e_out2 := ('1','1','1','1','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); ASSERT (sim_ok = FALSE) REPORT "TEST COMPLETED WITH NO ERRORS" SEVERITY NOTE; WAIT; END PROCESS; -- *** Instantiation of Component *** U0 : exam_7.vec port map ( IN, EN, OUT) ; END beowolf; -- *** Declare Configuration *** CONFIGURATION exam_7.vec_ctl OF exam_7.vec_tb IS FOR beowolf FOR U0 : exam_7.vec USE ENTITY WORK.exam_7.vec (STRUCTURAL_VIEW); END FOR; END FOR; END exam_7.vec_ctl; 2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns; -- 4700 IN <= ('0','0','0','0','1'); wait for 90 ns; -- 4790 i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 100 ns; -- 4890 e_out2 := ('1','1','0','0','0','0','0','1'); i_check_out2(e_out2, r_out2, m_out2, sim_ok); wait for 10 ns;vgen_examples/exam_8 644 143 12 13003 6116505060 10055 { FILE: EXAM_8 PURPOSE: Demonstrate the use of multiple timelines using the 'fork' statement. Also demonstrates the use of an include file with VGEN commands. Uses the 'pintype' command to set pin formatting and timing. DEVICE: Memory SIMULATOR: MENTOR_FORCE Mentor's FORCe format. LOG format can be generated using "simulator mentor;" NOTES: The 'echo' command is used to place vector generation status on the use console. The 'Comment' command is used to place information on generation data into the output file. } {Define the pin names: a[7:0] - input - address but, 8 bits wide ce* - input - chip enable (active low) oe* - input - output enable (active low) we* - input - write enable (active low) db* - bidirect - databus syncpin - input - aysynchronous clk signal } inputs a[7:0] ce* oe* we*, syncpin; inputs db[7:0]; { only generate input section of bidirects } {cycle sets the time increment for each output vector} cycle 200; {define the simulator to be used} simulator mentor_force version="8.2"; {String variables are declared and initialized. These variables will be used to set the state of the data bus} string word1 'AA'; string word2 '55'; string word3 '11'; string word4 '22'; string word5 '33'; string word6 '44'; string word7 '66'; string word8 '88'; string word9 '99'; string z 'zz'; {Integer variables are declared. These will be used as counters for addressing} int i j; {declare a subroutine. This subroutine is used for the write cycle of the memory} subroutine write(address, word) begin {Set the address bus 'a' to the parameter address} a=address; {chip enable low (active), output enable high (tri-state)} ce*=0; oe*=1; {enable a pulse in the write enable line} pintiming on we*; {set the databus to the parameter word} db=word; {generate a vector, data write enable low} vgen; {disable the pulse on write enable (write cycle is over) } pintiming off we*; {disable the chip} ce*=1; {generate chip disable vector} vgen; end; {declare a subroutine. This subroutine is used for the read cycle of the memory} subroutine read(address) begin {tri-state the databus} db = z; {generate a tri-state vector} vgen; {set the address bus to the address parameter} a=address; {enable the chip} ce*=0; {enable the outputs} oe*=0; {generate the read data vector} vgen; {tri-state outputs and disable chip} oe* ce* = hi; {generate chip disable vector} vgen; end; {The main portion of the vector generation starts here First initialize pins } {address bus to 0;chip disabled, write disabled, outputs disabled/tri-stated} a = lo; ce* oe* we* = hi; db = z; {generate startup vector} vgen; {The vectors are initially used to write data to memory} {By default ce* will be NRZ, changing at the start of the cycle} {the address requires 20ns setup time before ce* goes low} pintype nrz a @ -20; {we* is return to one, 10 ns after ce*, with a 100 ns width 10ns-110ns in each period} pintype ro we* @ 10 110 ; {the data bus requires a 50 ns setup prior to we* going high, db is declared to be NRZ, starting at time 70 (we* goes high at 110ns, 110-50 = 60)} pintype nrz db @ 60; {enable the pintiming on the address bus and in the data bus} pintiming on a db; {use the write subroutine to write data into the device} call write(0, 0); call write(1, word1); call write(2, word2); call write(4, word3); call write(8, word4); call write(16, word5); call write(32, word6); call write(64, word7); call write(128, word8); call write(255, word9); {now read these locations} {tri-state the data bus} db=z; {generate tri-state vector} vgen; {the timing needs to be changed for the read cycle} {the address but setup time for read is 30 ns} pintype nrz a @ -30; {call the read subroutine to generate read the written locations.} call read(0); call read(1); call read(2); call read(4); call read(8); call read(16); call read(32); call read(64); call read(128; call read(255); {include a file, this processes the specified file as if it were part of the original command file} include "exam_8.inc"; {go back to read timing} pintype nrz a @ -30; { modify timing for read } {tri-state the databus} db = z; {generate tri-state vector} vgen; {use a for loop to decrement through the addresses we just wrote (see the include file)} for i = 248 until 0 step -18 begin call read(i); end; vgen(); {generate a 99ns clock pin to run in parallel with the above timeing.} {the 'fork' statement seperates the different timing branches up to five timelines are supported a,b,c,d,e at the end of the vector generation, all timelines are merged into a single file} fork b; {cycle sets the time increment for each output vector} cycle 99; {First initialize pins} syncpin = 0; {generate startup vector} vgen; {pulse syncpin high at 33ns for 33ns width} pulse syncpin 33 33 1; {enable the pulses} pulse on syncpin; {generate vectors while the timestamp is less than the current time stamp of all forks. If the '*' were replaced with 'n' (vgen(5)) n vectors would be generated} vgen(*); {restore the original cycle time} cycle 200; end; vgen_examples/exam_8.inc 644 143 12 1277 6116505060 10617 { now do more thorough test - every eighteenth location } {restore the write timing} pintype nrz a @ -20; {generate a vector} vgen(); {generate the write vectors} for i = 0 until 255 step 18 begin {the data in each location is set to the complement of the address} j = ~i; call write(i,j); end; {generate a vector} vgen(); {display the date and vector time along with current vector data on the user console} echo " $date$ "; echo " $time$ After write loop: db=$db$, a[0]=$a[0]$, i=$i$, I+13=$i+13$"; {display the vector time along with current vector data in the vector file} comment "# $timE$ After write loop: db=$db$, a[0]=$a[0]$, i=$i$, I+13=$i+13$"; vgen_examples/exam_9 644 143 12 6206 6116505060 10045 { FILE: EXAM_9 PURPOSE: Demonstrate the use of If/Then/Else conditionals DEVICE: Memory SIMULATOR: CUPL Only supports binary vector format. Outputs are identified by state ('H','L','Z'). To use the Clock state, the explicit binary radix designator must be used (CLK = 'C'b). No timing is supported. All statements are output as CUPL $MSG directives. NOTES: Since CUPL does not support timing, all vectors must be output (usually only changed vectors are output). This is accomplished using the 'cycle n all'. } {Define the pin names} INPUTS DB<7..0> ADR<7..0> clk ext MODE<3..0> R/W REP* ; outputs a b c; {place the pin names vertically every 50 lines as comments} header 50; {define the simulator to be used} SIMULATOR CUPL; {create string variables to hold pin states} STRING Z 'ZZ'; STRING TEMP; {integer variable declared, used to count} INT I; {cycle sets the time increment for each output vector, the time increment is not used for CUPL, but the 'ALL' is necessary. The 'ALL' forces all vectors to be output, the default is print on change.} cycle 100, all ; {Subroutine for clock cycle - takes as a parameter the number of clock pulses desired} SUBROUTINE CLOCK (N) BEGIN {use the binary designator to assign the 'C' to the Clock} CLK = 'C'b; {clock 'N' pulses} REPEAT N BEGIN VGEN; END; END {Subroutine for write cycle - takes three parameters D - data bus, A - Address Bus, M - Mode} SUBROUTINE WRITE(D, A, M) BEGIN { Set DB, R/W, ADR, and MODE then generate a vector} DB = D; R/W = 0; ADR = A; MODE = M; VGEN; {Clock the device 1 time to latch the write data} CALL CLOCK(1); END {Subroutine for read cycle - takes the address (A) as a parameter and expect data D as a parameter} SUBROUTINE READ(A,D) BEGIN { set the R/W, ADR data and tri-state the databus - then generate a vector} R/W=HI; ADR = A; DB = Z; VGEN; {Clock twice to latch and output the data} CALL CLOCK(1); {Set the expect data and clock to read} DB = D; CALL CLOCK(1); VGEN; END {The main portion of the vector generation starts here First initialize pins } DB=Z; ADR=LO; MODE R/W EXT REP* = LO; CLK = HI; a b c = hi; VGEN; {Clock 4 times} CALL CLOCK (4); {Set the MODE pin HI and generate a vector} MODE=1; VGEN; {for modes 1 through 15 write the data from the table into address 22h} FOR I=1 UNTIL 15 BEGIN EXT R/W = HI; {if I equals 1 the write A5h to location 22, mode 1} if i\==\1 then call write('A5', '22', 1); {if I equals 2 the write 5Ah to location 22, mode 2} else if i\==\2 then call write('5A', '22', 2); {if I equals 3 the write 5Ah to location 22, mode 3} else if i\==\3 then call write('C3', '22', 3); {if I is not 1,2, or 3 the write 3Ch to location 22, mode I} else call write('3C'h, '22'h, I); {Read from location D7h, the expect data is '96'} call read('D7','96'); END; END vgen_examples/exam_17 644 143 12 5620 6116505060 10123 { FILE: EXAM_17 PURPOSE: Demonstrate the use of If/Then/Else conditionals DEVICE: Memory SIMULATOR: ABEL NOTES: Since ABEL does not support timing, all vectors must be output (usually only changed vectors are output). This is accomplished using the 'cycle n all'. } {Define the pin names} INPUTS DB<7..0> ADR<7..0> clk ext MODE<3..0> R/W REP* ; outputs a b c; busformat db=hex; group outs a, b, c; {place the pin names vertically every 50 lines as comments} header 50; {define the simulator to be used} SIMULATOR ABEL; {create string variables to hold pin states} STRING Z 'ZZ'; STRING TEMP; {integer variable declared, used to count} INT I; {cycle sets the time increment for each output vector, the time increment is not used for CUPL, but the 'ALL' is necessary. The 'ALL' forces all vectors to be output, the default is print on change.} cycle 100, all ; {Subroutine for clock cycle - takes as a parameter the number of clock pulses desired} SUBROUTINE CLOCK (N) BEGIN {use the binary designator to assign the 'C' to the Clock} CLK = 'C'b; {clock 'N' pulses} REPEAT N BEGIN VGEN; END; CLK = 0; END {Subroutine for write cycle - takes three parameters D - data bus, A - Address Bus, M - Mode} SUBROUTINE WRITE(D, A, M) BEGIN { Set DB, R/W, ADR, and MODE then generate a vector} DB = D; R/W = 0; ADR = A; MODE = M; outs = A; VGEN; {Clock the device 1 time to latch the write data} CALL CLOCK(1); END {Subroutine for read cycle - takes the address (A) as a parameter and expect data D as a parameter} SUBROUTINE READ(A,D) BEGIN { set the R/W, ADR data and tri-state the databus - then generate a vector} R/W=HI; ADR = A; DB = Z; outs = ~A; VGEN; {Clock twice to latch and output the data} CALL CLOCK(1); {Set the expect data and clock to read} DB = D; CALL CLOCK(1); VGEN; END {The main portion of the vector generation starts here First initialize pins } DB=Z; ADR=LO; MODE R/W EXT REP* = LO; CLK = LO; a b c = hi; VGEN; {Clock 4 times} CALL CLOCK (4); {Set the MODE pin HI and generate a vector} MODE=1; VGEN; {for modes 1 through 15 write the data from the table into address 22h} FOR I=1 UNTIL 15 BEGIN EXT R/W = HI; {if I equals 1 the write A5h to location 22, mode 1} if i\==\1 then call write('A5', '22', 1); {if I equals 2 the write 5Ah to location 22, mode 2} else if i\==\2 then call write('5A', '22', 2); {if I equals 3 the write 5Ah to location 22, mode 3} else if i\==\3 then call write('C3', '22', 3); {if I is not 1,2, or 3 the write 3Ch to location 22, mode I} else call write('3C'h, '22'h, I); {Read from location D7h, the expect data is '96'} call read('D7','96'); END; END vgen_examples/README.EXM 644 143 12 23311 6116505060 10264 Several example files are provided with VGEN. These examples demonstrate a wide variety of the features of VGEN. To help identify what VGEN features are highlighted, the following tables list which feature types are demonstrated in each example file. SIMULATOR: VALID exam_1 TIMEMILL exam_6 CUPL exam_9 MAX-PLUS exam_10 ORCAD exam_15 SILOS exam_4 MASM (LSIM) exam_13 SPICE exam_2 ADVANSIM_1076 exam_5 UDF exam_12 VIEWSIM exam_3, exam_14 TSTL2 exam_0, exam_11 VHLD exam_7 MENTOR_FORCE exam_8 HILO exam_16 FEATURE: Pin Formatting exam_0, exam_8, exam_12, exam_13 Output Formatting exam_1, exam_3, exam_12 Timing & Waveforms exam_2, exam_4, exam_8, exam_12, exam_16 Flow Control exam_3, exam_7, exam_9, exam_10, exam_13, exam_15 File Operations exam_13, exam_14, exam_15 Math/Logical exam_1, exam_2, exam_10, exam_11 Tables exam_5, exam_12 Bit field Operations exam_14 Bidirectionals exam_0 The following is a list of the example files provided, along with a description of the features demonstrated. ---------------------------- FILE: exam_0 PURPOSE: Demonstrate basic features VGEN features. This example uses Subroutines, FOR loops, STATE_TRANS, Bidirect merging, pin timing and many more features. DEVICE: Simple IC SIMULATOR: TSTL2 Toshiba format with both input stimulus and expected output state data. NOTES: Illustrates the required setup for generating TSTL2 files. ---------------------------- FILE: exam_1 PURPOSE: Demonstrate basic features VGEN features. This example uses the 'group' command to group pins under a single name. Boolean logic is used to simulate the functioning of the device. The state_trans command is also used. DEVICE: Simple PCB SIMULATOR: VALID_PRIM Valid primary I/O tabular format. No timing is used since this is a simply a set of combinational logic. NOTES: With no pin formatting defined, all pins are NRZ changing at the start of each cycle. ---------------------------- FILE: exam_2 PURPOSE: Demonstrate the use of logic to model pin relationships. Uses the 'fork' command to generate two seperate timelines. DEVICE: Logic Chip SIMULATOR: SPICE The spice simulator accepts several parameters governing the analog model. See the stimulus interface guide for additional information. NOTES: There are two seperate time lines used in this simulation. ---------------------------- FILE: exam_3 PURPOSE: Demonstrate subroutines and loops. Buses output in binary instead of the default hex. DEVICE: SIO interface SIMULATOR: VIEWSIM_GEN Produces a vector file and a '.CMD' command file. The command file defines all of the pins as a single vector ('allpins') and reads in the vector file. ie: "vector allpins pin1 pin2 ... pinn bus1 bus2 ... busn" "wfm allpins < *.vec" NOTES: Timing is changed after the initialization vectors. ---------------------------- FILE: exam_4 PURPOSE: Demonstrate basic pin timing using the 'pulse' and 'pintype' statements. DEVICE: Memory SIMULATOR: VERILOG Produces a stimulus module - input only. NOTES: For a test-bench format use verilog_tb. ---------------------------- FILE: exam_5 PURPOSE: Demonstrate the use of Tables DEVICE: Memory SIMULATOR: ADVANSIM_1097 Intergraph Electronics (DAZIX) VALIF format. NOTES: The 'Scale' command is used to change the timing. 'Scale' multiplies timing statements by a specified factor. ---------------------------- FILE: exam_6 PURPOSE: demonstrate shift/logic operations DEVICE: 74164 8 bit parallel-out serial shift register SIMULATOR: TIMEMILL uses EPIC .vec data format. Pin output order is as defined in this source file. NOTES: ---------------------------- FILE: exam_7 PURPOSE: demonstrate switch (Case) operations DEVICE: 74184 BCD to BINARY and 74185 BINARY to BCD Converter SIMULATOR: VHDL_TB Produces a VHDL test bench with stimulus and checks for expected output states. NOTES: ---------------------------- FILE: exam_8 PURPOSE: Demonstrate the use of multiple timelines using the 'fork' statement. Also demonstrates the use of an include file with VGEN commands. Uses the 'pintype' command to set pin formatting and timing. DEVICE: Memory SIMULATOR: MENTOR_FORCE Mentor's FORCe format. LOG format can be generated using "simulator mentor;" NOTES: The 'echo' command is used to place vector generation status on the use console. The 'Comment' command is used to place information on generation data into the output file. ---------------------------- FILE: exam_9 PURPOSE: Demonstrate the use of If/Then/Else conditionals DEVICE: Memory SIMULATOR: CUPL Only supports binary vector format. Outputs are identified by state ('H','L','Z'). To use the Clock state, the explicit binary radix designator must be used (CLK = 'C'b). No timing is supported. All statements are output as CUPL $MSG directives. NOTES: Since CUPL does not support timing, all vectors must be output (usually only changed vectors are output). This is accomplished using the 'cycle n all'. ---------------------------- FILE: exam_10 PURPOSE: demonstrate math/logic operations - switch statement DEVICE: 74S281 4-bit parallel binary accumulator SIMULATOR: MAXPLUS creates inputs and (optionally) expected outputs. The Maxplus "Group Create" command is used by VGEN to define buses. Absolute timestamps are used. NOTES: the propogate and generate outputs are used for look ahead carry generators (74S182) and are not used in this simulation ---------------------------- FILE: exam_11 PURPOSE: demonstrate switch (Case) operations and conditionals DEVICE: State Machine SIMULATOR: TSTL2 Toshiba TSTL2 format with stimulus and expected output states. NOTES: ---------------------------- FILE: exam_12 PURPOSE: demonstrate 'state_trans' and 'merge_bidirects'. demonstrate the use of 'bidirects' and 'pintype'. DEVICE: 2Kx8 Prom SIMULATOR: UDF User defined tabular format. Invoked via: 'SIMULATOR UDF "Format string" [,bit_sep='c'] [,include_bi_outs] See the manual for specifics regarding the parameters. NOTES: uses pin timing to define pin waveforms. Timing is set up seperately for the input and output portion of 'BIDIRECTS' ---------------------------- FILE: exam_13 PURPOSE: Demonstrate the use of the pintype command to define pin waveforms. Also demonstrates the use of file I/O to input vectors. DEVICE: microcomputer interface bus SIMULATOR: MASM This is the LSIM format using both input stimulus and expected output states. NOTES: uses a while loop to process the vector file. Conditionals are used to break out of the while loop when end of file (EOF) is reached ---------------------------- FILE: exam_14 PURPOSE: demonstrate basic file i/o , bit ranges, and local variables DEVICE: Memory SIMULATOR: VIEWSIM_GEN Produces a vector file and a '.CMD' command file. The command file defines all of the pins as a single vector ('allpins') and reads in the vector file. ie: "vector allpins pin1 pin2 ... pinn bus1 bus2 ... busn" "wfm allpins < *.vec" NOTES: loads output states from a file. ---------------------------- FILE: exam_15 PURPOSE: demonstrate file I/O - used to merge 2 vector files. DEVICE: N/A SIMULATOR: ORCAD Time field begins in column 1 and is 10 digits wide. The first vector starts in column 13. Individual pins have a space between columns, but there are no spaces between bus pins. NOTES: ---------------------------- FILE: exam_16 PURPOSE: Demonstrate use of WAVEFORM and PINTYPE for generating clocks. DEVICE: SIMULATOR: HILO NOTES: This code might be a part of a larger program. Also, the SYS_CLOCK use is illustrated - this is available on some interfaces. exam_1 PURPOSE: Demonstrate basic features VGEN features. This example uses the 'group' command to group pins under a single name. Boolean logic is used to simulate the functioning of the device. The state_trans command is also used. DEVICE: Simplevgen_examples/README3.7 644 143 12 10501 6125646377 10102 Release Notes For VGEN 3.6/3.7 March 1996 The following features are recent additions to VGEN 3.6/3.7 which may not have yet been incorporated into the VGEN USER'S MANUAL. ECHO and COMMENT enhancements ----------------------------- Added escape character in ECHO and COMMENT commands. The \ character (backslash) can now be used in front of the special characters $, % and " to inhibit their special meaning and cause them to be treated as any other printable character. In addition, both of these commands now support the printing of formatted variable values within the quoted character strings. Some examples are: ECHO "The current bus value is %b, at time %dnS", databus, $time; ECHO "Counter value offset is %x", (counter-base); COMMENT "Reg1 = %x, Reg2 = %d, Reg3 = %b", reg1, reg2, reg3; The legal formats are: %[-][n]d decimal - up to 32 bits %x, %h Hex %o Octal %b Binary - should be used for strings if characters other than 1 and 0 are included. ADVANSIM_1076 (DAZIX) ------------- For the ADVANSIM_1076 interface, active low pins and busses can now be specified with the * suffix. The mapping of these names from the VGEN source file to the VLAIF vector file is as follows: VGEN Source file VLAIF file ---------------- ---------- pin* -> pin~ bus*[5] -> bus(5)~ bus*[7:0] -> bus(7:0)~ MENTOR Version 8.x ------------------ Added parameter options to Mentor_force interface. These are: SIMULATOR mentor_force VERSION = "value", VHDL ; The optinal VERSION parameter value can be set to "8.x" for the 8.0 version of Quicksim II. Also, the VHDL parameter specifies that the Mentor VHDL simulator will be reading the Force file instead of Quicksim II. In each of these cases, there are some minor changes to the Force file syntax. Added use of pin attributes to specify Strength_Type for pins in FORCe file. Pin attributes are quoted text strings which follow pin names in the INPUTS, OUTPUTS and BIDIRECTS statements. For example: INPUTS pin1 "-Fixed", pin2 "-Wired", pin3; This statement declares 3 pins. The first two have Strength_Type attributes defined, the third does not. These will be printed in the output FORCe file as follows: FORCe pin1 1S 225 -Fixed -A FORCe pin2 1S 225 -Wired -A FORCe pin3 1S 225 -A LDS Simulator Interface ----------------------- Modified the interface to LSI Logic's simulation tools so the time stamp in the file defaults to 1 NS units instead of 100 PS units. QSIM Interface -------------- Added QSIM interface to Compass Design Automation's simulator. Invoked as: SIMULATOR qsim; This interface handles both input stimulus and expected output data. VHDL_TB_TIO Interface --------------------- This interface was modified to correct some bugs. Two new parameters were added: RESULT_VECTOR the type for result vectors COMPONENT the component name VIEWSIM Interface ----------------- A VIEWSIM1 interface was added to force a NS time units with the time stamp in the vector file. This is necessary if your default units in the simulation environment is not NS. Other than this, the format is the same as the VIEWSIM interface. Also, some modifications were made to the VIEWSIM_GEN format to accommodate Viewsim's new 5.X release. The new format is compatible with both 4.X and 5.X. SYSTEM_CALL Command ------------------- A SYSTEM_CALL command has been added to VGEN which has the following syntax: SYSTEM_CALL " .. text .. "; Where the text between the quotes is passed to the system upon completion of the VGEN compilation. PINTIMING Command ------------------ The PINTIMING command has been enhanced to support the following forms: PINTIMING ON; or PINTIMING OFF; This form causes all pins which have been defined with a PINTYPE command to be either enabled or disabled, without the need to list them all. EPIC/TIMEMILL Interface Parameter (Version 3.7.2 or later) --------------------------------- Added the following optional parameter to EPIC / TIMEMILL interface: BUS_NOTATION="LrR"; Where L is the desired left bus delimeter, r is the bus range character(s) and R is the right bus delimeter. For example: SIMULATOR epic bus_notation="<:>"; would result in busses in the .cmd file (and .out file) being listed as bus. The bus range may be 1 or 2 characters (e.g. bus_notation="<..>") The default bus notation is "[-]". Several example files are provided with VGEN. These examples demonstrate a wide variety of the features of VGEN. To help identify what VGEN features are highlighted, the following tables list which feature types are demonstrated in each example file. SIMULATOR: VALID exam_1 TIMEMILL exam_6 CUPL exam_9 MAX-PLUS exam_10 ORCAD exam_15 SILOS exam_4 MASM (LSIM) exam_13 SPICE exam_2 ADVANSIM_1076 exam_5 UDF exam_12 VIEWSIM exam_3, exam_14 TSTL2 exam_0, exam_11 VHLD exam_7 MENTOR_FORCE exam_8 HILO exam_16 FEATURE: Pin Formatting exam_0, exam_8, exam_12, exam_13 Output Formatting exam_1, exam_3, exam_12 Timing & Waveforms exam_2, exam_4, exam_8, exam_12, exam_16 Flow Control exam_3, exam_7, exam_9, exam_10, exam_13, exam_15 File Operations exam_13, exam_14, exam_15 Math/Logical exam_1, exam_2, exam_10, exam_11 Tables exam_5, exam_12 Bit field Operations exam_14 Bidirectionals exam_0 The following is a list of the example files provided, along with a description of the features demonstrated. ---------------------------- FILE: exam_0 PURPOSE: Demonstrate basic features VGEN features. This example uses Subroutines, FOR loops, STATE_TRANS, Bidirect merging, pin timing and many more features. DEVICE: Simple IC SIMULATOR: TSTL2