solaris32/0000755000175000017510000000000011633515101013121 5ustar jcosleysourceiiisolaris32/README2.20000644000175000017510000004203011633506654014237 0ustar jcosleysourceiii VCAP Release 2.2 Sept. 12, 2011 The following notes summarize new features and feature enhancements that are included in this release of vcap. ----------------------- 1) COMPARE_WINDOW - COMPARE_BLOCK only. This new command is intended to be used with Bidirectional Comparisons (COMPARE_TYPE bidirectional;) for a simple way to window-in on where within each cycle to do comparisons of states between two files. This can be somewhat simpler than having to do different ALIGNment processes while reading in the data from source and reference files. It also has the added advantage that it will do the verification for the entire window time(s) instead of just at a single strobe point. The primary criteria for using this feature, however, is that the two data files have identical cycle times throughout the files. The syntax is: COMPARE_WINDOW [INPUTS | OUTPUTS | pinlist | *] @ t1 - t2 [,t3 - t4] ; or COMPARE_WINDOW [INPUTS | OUTPUTS | pinlist | *] @ CONDITION expr = state ; In the first form, the comparison of states for the specified signals is only performed between the times specified - between t1 and t2, and between t3 and t4 if specified. Note that these are time windows relative to the cycle boundaries so a CYCLE time must be specified also. If no pinlist (or INPUT/OUTPUT/*) is listed, then the COMPARE_WINDOW applies to all pins by default. The second form defines a comapre window which is true when the expression "expr" evaluates to the "state" specified. For example: COMPARE_WINDOW outputs @ CONDITION DBout_enb = 1; would define the compare window for all output pins to be when DBout_enb is in a '1' state. Using the this command, a typical vcap command file which comapres the simulation results of two print-on-change Mentor LSIM runs, might look like: SRC_BLOCK begin source_file = "design1.lsima"; tabular_format LSIM; end; REF_BLOCK begin reference_file = "design1.lsim"; tabular_format LSIM; end; COMAPRE_BLOCK begin cycle = 225; compare_type bidirectional -REPORT_DELTA_DELAYS; compare_window outputs @ 185 - 220; report_file = "design1.rpt"; end; Here, all pins common to both simulation data bases will be compared. All output pins will be compared only during the window between 185 and 220 ns in each cycle. 2) STABILITY_CHECK - ANALYSIS_BLOCK only. This command is used to check for output pin stability within one or two windows in each cycle, or during any time in which a specified logic expression is true. The syntax is: STABILITY_CHECK [OUTPUTS | pinlist] @ t1 - t2 [,t3 - t4] ; or STABILITY_CHECK [OUTPUTS | pinlist] @ CONDITION expr = state ; Any number of these stability checking statements can be used in the analysis block, but only one check can be specified for any single pin. In the first form, any transitions on the specified pins are reported which occur during the window between t1 and t2 of each cycle, and between t3 and t4 (if specified) of each cycle. All of the times t1 thru t4 must be within the cycle time, and the CYCLE must be defined. Some examples are: STABILITY_CHECK outputs @ 85 - 100; STABILITY_CHECK dbus.O, adr, planetH @ 40 - 50, 90 - 100; In the second form, any state transitions on the specified pins are reported if they occur when the logic expression "expr = state" is TRUE. Some examples are: STABILITY_CHECK dbus @ CONDITION dbenb = 1 ; STABILITY_CHECK adr_out[15:8], db_out @ CONDITION (out_enb & ~CLK) = 1; For both forms, the report of detected transitions is limited to the first 1000 in the report file. 3) Improved DONT_CARE Handling - COMPARE_BLOCK The new DONT_CARE command syntax (a superset of existing syntax) is : DONT_CARE [-INPUTS | -OUTPUTS] 'abc'; If neither -INPUTS nor -OUTPUTS is specified, then the dont_care characters apply to both inputs and outputs. Thus, the first new feature of this new syntax is that it allows for the specifying of different dont_care characters for input pins vs. output pins. A second improvement in the handling of dont_care state characters is that the application of dont_care characters is only to the Reference file. Previously, the don_care characters applied to both the ref and src files. For example, if 'X' was the dont_care character, in previous versions of vcap none of the following situations would be flagged as a miscompare: REF SRC 1/0 X X 1/0 X X In vcap 2.1, the first case would be flagged as a miscompare since the REF state is not a dont_care and is not equal to the SRC state. The DONT_CARE character also does not default to 'X' any longer - if you want X to be dont_care for both input and outputs in Ref file, use "DONT_CARE X;". Be sure to set any STATE_TRANS commands to give desired effects during comparisons with DONT_CARE states. It may also be necessary to match the BIDIRECT_CONTROL and BIDIRECT_STATES default_input and default_output states to be consistent with the dont_care states. For example if we declared: DONT_CARE '-'; then we may also want to specify: BIDIRECT_CONTROL pins = input when ctrl=1, default_output = '-'; This will ensure that when the reference file's bidirect pins are in an input mode, the state forced on their output versions matches the dont_care state. 4) DYNAMIC_TIMING - ANALYSIS_BLOCK only. (BETA VERSION) Part of the standard simulation data analysis performed by vcap on all input pins is to characterize the activity of the pins into one of the standard behavior formats (NRZ, RZ, RO, etc.). Previously, this analysis would only handle static timing - i.e. it could only resolve a single timing behavior for a given pin. If a pin's behavior changed within a simulation file, this was noted and then further behavior analysis was terminated. This new DYNAMIC_TIMING feature in vcap enhances this input pin timing behavior analysis to handle dynamically changing timing behavior. The syntax for telling vcap to perform dynamic timing behavior analysis on input pins is thru the DYNAMIC_TIMING command: DYNAMIC_TIMING [=] "fname1" [, "fname2"] [-VERBOSE] ([-FORMAT format]); Where "fname1" is the name of the file to which the results of the dynamic timing analysis is written. The information placed in this file consists of two parts. First is the timing information for each pin, grouped into TIMESETS. These TIMESETS are named, with the first being TSET1, the second is TSET2, etc. Within each TIMESET block, the CYCLE time is listed and each pin is listed with its timing behavior format for that timeset. An example of the TIMESET information written in generic format might be: TIMESET: TSET1, CYCLE: 200.000 A SBC 25.000 50.000 0.000 0.000 B SBC 25.000 50.000 0.000 0.000 C SBC 25.000 50.000 0.000 0.000 CLK RO 0.000 60.000 0.000 0.000 IBUS[7] NRZ 0.000 0.000 0.000 0.000 IBUS[6] NRZ 0.000 0.000 0.000 0.000 IBUS[5] NRZ 0.000 0.000 0.000 0.000 IBUS[4] NRZ 0.000 0.000 0.000 0.000 IBUS[3] NRZ 0.000 0.000 0.000 0.000 IBUS[2] NRZ 0.000 0.000 0.000 0.000 IBUS[1] NRZ 0.000 0.000 0.000 0.000 IBUS[0] NRZ 0.000 0.000 0.000 0.000 TIMESET: TSET2, CYCLE: 200.000 A SBC 35.000 75.000 0.000 0.000 B SBC 35.000 75.000 0.000 0.000 C SBC 35.000 75.000 0.000 0.000 CLK RO 0.000 90.000 0.000 0.000 IBUS[7] NRZ 87.000 0.000 0.000 0.000 IBUS[6] NRZ 87.000 0.000 0.000 0.000 IBUS[5] NRZ 87.000 0.000 0.000 0.000 IBUS[4] NRZ 87.000 0.000 0.000 0.000 IBUS[3] NRZ 87.000 0.000 0.000 0.000 IBUS[2] NRZ 87.000 0.000 0.000 0.000 IBUS[1] NRZ 87.000 0.000 0.000 0.000 IBUS[0] NRZ 87.000 0.000 0.000 0.000 When generating the TIMESET blocks, vcap will normally list the timing behavior format for all input pins in the first TIMESET (TSET1), and then only list those pins which differ from TSET1 in the other TSETs. The optional -VERBOSE flag can be used to force vcap to list all pins in each TIMESET block. The second part of the information written during dynamic timing analysis is a TIMESET TRACE, which essentially lists the ordering of the TIMESETs within the data file. An example of this would be: TSET1 CYCLE=0 TIME=0.000 TSET2 CYCLE=4 TIME=800.000 TSET3 CYCLE=9 TIME=1800.000 TSET2 CYCLE=12 TIME=2400.000 TSET1 CYCLE=16 TIME=3200.000 TSET2 CYCLE=20 TIME=4000.000 TSET3 CYCLE=25 TIME=5000.000 TSET2 CYCLE=28 TIME=5600.000 . . . In this section, vcap maps the extracted TIMESETs to the actual cycle number and simulation time in the simulation data. The TIMESET information and TIMESET TRACE information together represent a cycle-based equivalent to the original event-driven (print-on-change) simulation data. Normally, this TIMESET TRACE information is added to the end of the "fname1" file, after all of the TIMESET definitions. If an "fname2" file is specified, however, the TIMESET TRACE information will be written to it instead. The format of the TIMESET and TIMESET TRACE information is a generic format which is specific to vcap. The optional parameter "-FORMAT format" provide for a choice of output formats for this data. Currently the only option for this is "-FORMAT VTRAN" which generates a TIMESET format that can be used directly by vtran's TEMPLATE_CYCLIZATION process. The basic goal of this feature in vcap is to extract a cycle-based equivalent, with ordered timesets, from a print-on-change simulation data file which accurately reflects the timing behavior of input pins. This cycle-based version of the input pin behavior is in a format which is typically applicable to testers and some standard simulation data formats. In order to help vcap optimize the definition of TIMESETs, the user can also specify RESOURCE_GROUPs which correspond to groups of pins which undergo the same timing changes at the same time. In real simulations, if a group of pins has its timing change (say from NRZ @ 50 in cycle n to NRZ @ 60 in cycle n+1), it is not necessarily the case that all of the pins will make a transition in the very next cycle (n+1) to show this new timing behavior. Some of the pins may not transition until several cycles later. As vcap is analyzing the data in cycle n+1, it would only be able to determine the new timing for those pins which made a transition in the cycle, even though all of the pins in the group actually had their timing change. This would then cause vcap to create additional TIMESETs where the group of pins have a mixture of the old and new timing (those that transitioned in cycle n+1 would become NRZ @ 60, while those pins that had no transition in the cycle would still be NRZ @ 50). RESOURCE_GROUP commands can be used when the DYNAMIC_TIMING command is present (dynamic timing analysis enabled) to help vcap optimize TIMESET assignments. This command has the following syntax: RESOURCE_GROUP group_name pinlist; Use as many of these RESOURCE_GROUP statements as necessary to group the pins with common timing. This will typically greatly reduce the number of TIMESETs produced. 5) CYCLE_BOUNDARY Dynamic Timing - COMPARE or ANALYSIS_BLOCK (BETA VERSION). When doing analysis or bidirectional comparisons of simulation data files with dynamic timing, this new command specifies that vcap should try to determine the cycle time using a pin transition for the cycle boundaries. The syntax is: CYCLE_BOUNDARY [WHEN] pin a->b ; Where "pin" is the name of a pin (usually a clock pin) and the states a and b are the from/to state transition characters which are to be used to define the cycle boundary. In order to use this feature, it is necessary to have a pin which makes the specified transition every cycle. Vcap will dynamically change the CYCLE time depending upon the time between these transitions. 6) Improved DELTA_DELAYS analysis Improvements have been made in the algorithms used to determine delta delays - the maximum difference in output pin transition times between two simulation data files. 7) Transition Statistics In addition to the current signal transition data that is accumulated and reported in the vcap summary sections, additional transition statistics can be gathered on select signals. The goal of this is to better profile the behavior of the signal as an aid to identifying its behavior. The command: Transition_Statistics [-ignore "a->b, c->d, .."] [pinlist] ; or Transition_Statistics [-mark "a->b, c->d, .."] [pinlist] ; The -ignore option provides for a way to tell vcap to ignore certain transitions while accumulating the statistics. The -ignore flag can be optionally replaced with a -mark flag which will simply mark the specified transitions in the report file by enclosing them in ()'s. The * character can be used as a wildcard state character. For example "*->X" would mean anystate-to-X transitions. Keep in mind that this processing occurs after state translations defined by the STATE_TRANS process occur. If there is no pinlist, then transition statistics are generated only for those signals which vcap is unable to determine it's PINTYPE. Otherwise the histogram is generated for all signals in the pinlist. The global signal group names ALL_INPUTS, BIDIR_INPUTS, ALL_OUTPUTS, BIDIR_OUTPUTS and * (all signals) can be used for the pinlist. Use he optional Resolution statement to define how finely the Time slots are set for collecting the transition information. For example, if a Resolution of 0.1 is set then a 0->1 transition happening at 55.21, one at 55.25 and one happening at 55.28 would all be counted as a transition at 55.2 since decimal numbers get truncated. An example use of this command would be: Transition_Statistics -ignore "*->Z, Z->*", Pin1, Pin2; INPUT PIN TRANSITION REPORT Signal: Pin1 -ignore "*->Z, Z->*" Trans Time Count First Occured 0->1: 5.05 33 70.00 1->0: 12.70 33 77.65 0->X: 5.15 355 1004.15 X->0: 6.15 355 1015.05 Signal: Pin2 -ignore "*->Z, Z->*" Trans Time Count First Occured 0->1: 8.15 33 74.15 1->0: 8.12 34 74.12 0->X: 5.15 355 10 X->0: 6.15 355 10 8) Integration with VTRAN (for single timeset case) After performing timing analysis on a simulation vector file, vcap reports the PINTYPE behaviors it has determined for all of the signals in the file. This information is included in a section of the report file. In order to better integrate this with vtran, a switch has been added that tells vcap to output the PINTYPE information to a file which in in the format required by vtran to cyclize the data. This then provides a seamless flow between vcap and vtran where the timing analysis performed by vcap is used to direct vtran in the cyclization task. The syntax is: Create_Timing_File "filename" ; Once generated and verified, this file can be directly copied (later Included) into the PROC_BLOCK of a vtran command file to be used for cyclization of the vectors during translation. 9) Enhancements to MASK The MASK statement can now be applied to signals during analysis using both the time range and logic expression criteria. 10) New MASK_PINS FEATURE Added new MASK_PINS option which is a super-set of the old MASK statement. This new feature can be used in both Analysis mode and Compare mode and has the following syntax: MASK_PINS [mask_character=C] pinlist @ [NOT] t1, t2 [-CYCLE]; MASK_PINS [mask_character=C] pinlist @ [NOT] CONDITION logic_expr; MASK_PINS [mask_character=C] pinlist @ [NOT] TRANSITION a->b [n1, [n2]]; MASK_PINS [mask_character=C] pinlist @ [NOT] CONTROL_TRANSITION ctlpin, a->b [n1, [n2]]; where the states used for the logic_expr, transition and control_transition are derived from the Reference File. n1 is a number representing the start of the mask and can have a value >=0 (0 starts masking on the current vector) and n2 represents the stop vector and can have a value >=0 also (default is = n1). The number of vectors that will be masked by this is n2-n1+1 and is derived from the vectors in the Reference file. Note that these vectors may not be the same as cycles if the Reference file is a print-on-change file. The NOT option masks the vectors outside the defined region for all variants of MASK_PINS. 11) This version of vcap has a single consistent way for user's to determine the hostid of a machine on which the software is running: vcap -hostid this will generate the hex code needed for generation of the license key. 12) Fixed bug in vcd reader. solaris32/vread.bin0000755000175000017510000000211111633515100014711 0ustar jcosleysourceiii# Updated 7/20/2011 - release 9.3 # vread1.bin VERILOG_VCD 1 VERILOG_VCD_F 1 VERILOG_VCD_FQ 1 SYNTEST 1 DAZIX_TV 1 DAZIX_SV 1 MENTOR_LOG 1 TSTL2 1 TDS 1 # vread2.bin EPIC_OUT 2 NANOSIM_OUT 2 IMS_MEM 2 TDL_91 2 TDL_91_CYCLE 2 LSIM 2 MENTOR_LSIM 2 QSIM 2 COMPASS_QSIM 2 # vread3.bin PIE 3 CBC 3 QUEST 3 WGL 3 WGL_CYCLE 3 # vread4.bin VALID 4 FTDL 4 MEF 4 EPIC_VEC 4 NANOSIM_VEC 4 PCF 4 # vread5.bin STIL 5 # vread6.bin HP93000 6 HP83000 6 AGILENT_93000 6 AGILENT_83000 6 VERIGY93000 6 VERIGY83000 6 SWAV 6 CREDENCE 6 J750 6 J973 6 CATALYST 6 FLEX 6 J750+ 6 T6600 6 T3300 6 T2000 6 LTX 6 # vreadN.bin NOVAS_FSDB N NOVAS_FSDB_F N NOVAS_FSDB_FQ N # vreadw.bin WIF w WIF -KEEP_SIGNALS w VSS w # vrwq.bin QVBF q # vreadm.bin MENTOR_FORCE m XMENF m solaris32/sdmt.preview0000644000175000017510000000020411633507041015473 0ustar jcosleysourceiiivtran 9.3 [RW] PREVIEW 7/20/2011 12/31/2011 617A6900AD8413FB576560AC vcap 2.2 PREVIEW 7/20/2011 12/31/2011 177FB96F27FFD8CE9A4D7807 solaris32/vcap0000755000175000017510000113361011633515101014005 0ustar jcosleysourceiiiELFDH4P4 (44C}C}CC=DD/usr/lib/ld.so.1 !"$()*-.0234579:;<=>@BCDFHIKMNQRSUWYZ[\]^_`abcefghijklmnoqtvwyz{|}~  "#$%'*+-./13478:<>@ABDGIMNPSXZ[\^_abcdeghjlmnopswxyz{}~  #%&'+,/168?AEGJLOPTVXdprsux    !&(),02569;=?CEFHJKLOQRTUVWY]`fikqrtuv| [\ GX%Dh,44ڰ P ;EOx XEa`8@iCpIxF~xd [i@ D"ј x G ] HXxDGD%C,Fx98DD OHpXG bGd l[|QH  G0{ H, eP z8_@  a  JH (Gx4P ;DBh L! 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'd, ?  m?d, $, ? $ 'd, ?  ?@ &?d, $ '@@p@X@s@d@@a@ @ 'OO@X/dX@Z@!# d/`$O,c@ܐ (!!䀤|'d@@@0@X@@3@d@@!@ @ 'OO@X/dX@@OOO$`?'㿈'D'H'L'P'T'XL D-X@L$ '`D-L$ '# '?D-%-o'X@h'`D-'!# @G 'PL/O`H 1/`L 0/$ ?@0 'H!# %L/ &O`0 1/`1 0/`U D/`H L /`L H/`D U/?D-$L$ OT,  '㿈'D'H'L'P'T'XL 'D, X@L$ '`'D, L$ '& '?D,%', ~'X@w'`'D, '?D,%', @ 'PL /뀥?D,%', ``/!# %@ ?@m 'H!# %L/ &O뀤`0 1/뀤`1 0/뀤`U D/뀤`H L /뀤`L H/뀤`D U/?D, $ 'L$ OT,  '㿘. :`@.`? *`:  H 1*`:  L 0*`:  U 1*`:  D 0/ :``H 1`L  0`U 1`D 0 /`:1/ ?`/ :``10`0 0  X0 /`:0/ ?`/ :``01`1 1  X . :`.`: @ 1 0/`: '㿐`/ @ `/ @ ? ??@r '?/ && &` 㿀'D '!!䀤2@ː !#!"L/O瀤 ; b`@ !#!"L/O瀤 : bԔ`@  c@ O O瀥 ~ ?D/`$` (  '?D/`$` ) $ '?D/`$` & ?D/`$` | ?D/`$` =D@,??$?D/`$`~@O /'1# 3bʒ@ %n ` %d ` %Z `( %P '?D/`%@`/`%@`$ %3 ?D/`%@` L /`%@`$ % M ' "?D/`%@`!#L /`%@`#b$ $b`4 @<#b $b!!䀤D/`$ c8`@' 㿀!!䀤_@ !#!"L.<  =N`c@ O.=  ~?/`&6` ( ?/`&-` )' ?/`&$` &?/`&` |?/`&`!#䀢 '@h U/`&`#b$ $b#b $b!!䀤/`& @ؐ &#b$b!#L='@D Q@= !#+bL'"% $!#L.` $.`b %b㿠  L#@W @ @Ws?㿠rL#@WoM 0@WiM h@WcM @W]M @WWM @WQ}M! @WKwM!(@WEqM!P@W?kM!@W9eM!@W3_M!@W-YM"D@W'SM"p!@W #LM"@WFM"@W@M"@W:M# @W4M#$@W.M#\@V(M#@V"M#@VM#@V!N @V@V !N `@Vܐ@Vڐ $N @VN @VN!@VN!D@V @Ւ @V?N!h@VN!@VN!@VN!@VN" @V @ @V?N"P@V!N"h@V@V 0N"@VN"@VN"@VzN# @VtN#P@VnN#@VhN#@VbN#@V\"N#@VVO @VP|O 4@VJvO L@VDpO d@V>jO @V8dO @V2^O @V,XO!@V&RO!D@V LO!\!@V#EO!!@V#>O!!@V #7O!@V1?# ,!; 2 )$2 , !;!$$? !, !;!TO"!@U#ؐ @ @U?,D\t4Ld(@Xx $<Tl0H`x 8Ph㿠QO"@U{ @ @Uj?nO"$@UphO"<@UjbO"`@Ud\O"@U^VO"@UXPO"@URJO#$@ULDO#`@UF>O#@U@8!O#@U:@U8 00P $@U2*        $ , !< P %s CHECK DURING WINDOW: %s -> %s CHECK DURING CONDITION: %s PIN INSTABILITY TRANSITIONS DETECTED ------------------------------------ ww -- TIMESETS -- TIMESET: TSET%d, CYCLE: %.3f %s %s %.3f %.3f %.3f %.3f %s %s %.3f %.3f %.3f %.3f TEMEPLATE_CYCLIZATION CYCLIZATION_SKEW="0.01" ; TIMESET TSET%d CYCLE %s; PINTYPE UNK NRZ NRZ -PRIMARY RZ -PRIMARY RO RX SBC -PRIMARY RZ2X -PRIMARY RO2X %s @ %s ; %s ; %s, %s ; %s, %s, %s, %s ; PINTYPE STB %s %s %s %s @ %s ; ENDTIMESET; -- TIMESET TRACE --- TSET%d CYCLE=%d TIME=%.3f ***** PCAP %s ANALYSIS BLOCK REPORT ***** ***** VCAP %s ANALYSIS BLOCK REPORT ***** Date: %s Source File: %s Cycle Time: %s OUTPUT PIN DELAY SUMMARY (R=Rise, F=Fall, *=No Transition) ======================== TOTAL CHECK PIN NAME: MIN DELAYS @TIME MAX DELAYS @TIME TRANS %-17s (Delay from cycle boundary) (Delay from transition on pin: %s) %s (Delay from cycle boundary) (Delay from transition on pin: %s) R: %-10sR: * %-13s R: %-10sR: * %-13s %d F: %-10s F: * %-13s F: %-10sF: * %-13s WARNING** Pin: %s made no positive transitions in data file. WARNING** Pin: %s made no negative transitions in data file. MAX OUTPUT DELAYS VS. SPEC. DELAYS ---------------------------------- WARNING** MAX RISE DELAY EXCEEDED - Pin: %s, max delay = %s; spec delay = %s WARNING** MAX FALL DELAY EXCEEDED - Pin: %s, max delay = %s; spec delay = %s **** ALL OUTPUT PIN DELAYS WERE WITHIN SPEC. ALL OTHER OUTPUT PIN DELAYS WERE WITHIN SPEC. OUTPUT PIN STROBE SUMMARY ========================= STROBE # STROBE TIME PIN LIST MAX DELAY(1) %3d %-10s %-18s %-9s (1) MAX DELAY WITH RESPECT TO START OF CYCLE WARNING** Pin: %s delay too late in cycle for strobe parameters. OUTPUT PIN SIMULTANEOUS TRANSITIONS SUMMARY =========================================== TRANSITION WINDOW WIDTH = %s 1 -> 0 TRANSITIONS 0 -> 1 TRANSITIONS NUMBER OF PINS @TIME NUMBER OF PINS @TIME %3d %-12s %3d %-12s The Maximum allowed number of 1->0 pin transitions in a window is : %d This was exceeded %d times. The Maximum allowed number of 0->1 pin transitions in a window is : %d This was exceeded %d times. w { Created by vcap %s on %s } CYCLE %s ; INPUT PIN SUMMARY ================= GROUP PINTYPE PINS TRANSITIONS %2d PINTYPE UNK NRZ NRZ RZ RO RX SBC RZ2X RO2X %s @ UNK * ; NRZ T1= %-6s %s ; UNK * ; NRZ T1= %-6s %s ; NRZ T1= %-6s %s ; RO T1= %-6s T2= %-6s %s, %s ; RZ T1= %-6s T2= %-6s %s, %s ; RX T1= %-6s T2= %-6s %s, %s ; SBC T1= %-6s T2= %-6s %s, %s ; RO2X T1= %-6s T2= %-6s T3= %-6s T4= %-6s %s, %s, %s, %s ; RZ2X T1= %-6s T2= %-6s T3= %-6s T4= %-6s %s, %s, %s, %s ; %-23s %-12d %-23s 0 state=%c %-23s %-12d %-23s 0 state=%c PINTYPE STB %s %s %s %s @ %s ; AUTO_ALIGN %s ; WARNING** Near time %s Input Pin: %s changed its cycle timing behavior in simulation data. WARNING** Input Pin: %s made no state transitions in the sim data file. ** No Glitches found. ** No Illegal States found. ** No Instabilities found. PIN TRANSITION STATISTICS REPORT ================================ ** Only signals with inconsistent timing behavior ** Signal: %s -ignore %c->%c %c->%c Trans Time Count First Occured %c->%c %-8s %-8d %s (%c->%c %-8s %-8d %s) *** no transitions: state = %c %d --VCAP %s (C) 2011 Source III, Inc. **** Intel Site License **** rsdmt.enabler --VCAP %s (C) 2011 Source III, Inc. Unable to open sdmt.enable file %f%f%d.%d.%d.%drError: Unsuccessful in verifying Network License for IP Address %s Error: Unsuccessful in verifying Network License for IP Address %s %x%d/%d/%d%d/%d/%d%8x%8x%8x --VCAP-PREVIEW %s (C) 2011 Source III, Inc. **** Limited to %d Vectors **** --VCAP %s (C) 2011 Source III, Inc. No valid VCAP key found. Key not valid for current VCAP %s version. This version of VCAP is not licensed for this node. VCAP license period has expired. VCAP license period has not commenced. Key file has been corrupted. ---VCAP-PREVIEW %s (C) Copyright 2011 Source III, Inc. **** Limited to %d Vectors **** ** I don't appear to have WRITE permission to files. %d/%d/%d ** I don't appear to have WRITE permission to files. ** VCAP %s Program Terminated. rUnable to write to temp file. Check write access. %xInsufficient Memory. Analysis Terminated. Insufficient Memory. Analysis Terminated. Insufficient Memory. Analysis Terminated. Insufficient Memory. Analysis Terminated. Insufficient Memory. Analysis Terminated. ***** PCAP %s COMPARE BLOCK REPORT ***** ***** VCAP %s COMPARE BLOCK REPORT ***** Date: %s Source File: %s Reference File: %s DON'T CARE STATES: INPUTS = '%s', OUTPUTS = '%s' DON'T CARE STATES = '%s' CYCLE = %s NS MAXIMUM NUMBER OF MISCOMPARES = %d COMPARE TYPE = TRAN, TRAN TRAN, STATE STATE, STATE BIDIRECTIONAL CHECK PIN NAME SKEW TOLERANCE MASK/COMPARE REGION -------------- -------------- ----------- ******* NO COMMON PINS WERE FOUND BETWEEN THE SOURCE AND REFERENCE FILE ******* VCAP TERMINATING SINCE NO COMPARISONS POSSIBLE ******* NO COMMON PINS WERE FOUND BETWEEN THE SOURCE AND REFERENCE FILE ******* VCAP TERMINATING SINCE NO COMPARISONS POSSIBLE %-21s +%6s nS, +%6.2f %% , -%6s nS -%6.2f %% %s-%s %s-END %s-%s %s-END%s %s-%s %s-END %s-%s %s-END -COMPARE_WINDOW %s ***** NOTE: THERE WERE %d PINS IN ***** NOTE: THERE WERE %d INPUT PINS IN ***** NOTE: THERE WERE %d OUTPUT PINS IN THE SOURCE FILE WHICH WERE NOT IN THE REFERENCE FILE: %s ***** NOTE: THERE WERE %d PINS IN ***** NOTE: THERE WERE %d INPUT PINS IN ***** NOTE: THERE WERE %d OUTPUT PINS IN THE REFERENCE FILE WHICH WERE NOT IN THE SOURCE FILE: %s == PIN MISCOMPARE SUMMARY: MISCOMPARE# PIN NAME REF TIME REF STATE SRC STATE ---------- -------- -------- --------- --------- VECTOR MISCOMPARE SUMMARY: Error: Unable to open temp file: %s. Error: Unable to open temp file: %s. ******* NO MISCOMPARES WERE FOUND DURING FILE COMPARISON Comparison Terminated Normally at : %s Comparison Terminated at : %s Ending Simulation Time different in two files ============================================== DELAY DELTAS: The following chart summarizes the Minimum and Maximum delay differences between transitions in the Reference and Source files. _______________ REF |__________________ _______________________ SRC |___________ ----->| Delta |<---- %-20s Delta Min= %-8s At Time: %s Delta Max= %-8s At Time: %s Comparison complete. Report in file: %s ******* NO MISCOMPARES WERE FOUND DURING FILE COMPARISON Comparison Terminated Normally at : %s Comparison complete. Report in file: %s *****%s *****%s %d%lfWarning: too many vectors between cycle boundaries unable to determine cycle period. Warning: too many vectors between cycle boundaries unable to determine cycle period. Warning: too many vectors between cycle boundaries unable to determine cycle period. %-11s REF: SRC: ******** MAX NUMBER OF MISMATCHES EXCEEDED ******** COMPARISON RUN TERMINATED ******** MAX NUMBER OF MISMATCHES EXCEEDED Comparison results in Report File: %s %-10d %-19s %-14s %c->%c %c %c %c %c %c %-11s REF: SRC: ******** MAX NUMBER OF MISMATCHES EXCEEDED ******** COMPARISON RUN TERMINATED ******** MAX NUMBER OF MISMATCHES EXCEEDED Comparison results in Report File: %s END MISCOMPR %-19s %-14s %c %c %-10d %-19s %-14s %c %c %sPIN NAME: %s TIME: %-12s GLITCH_WIDTH: %-10s STATE SEQUENCE: %c-%c-%c PIN NAME: %s TIME: %-12s ILLEGAL STATE : %c *** LISTING LIMIT OF 1000 EXCEEDED PIN NAME : %s TRANSITION : %c -> %c TRANSITION TIME: %s (%s into cycle) TRANSITION TIME: %s (while condition is true) Resolution = %lf. %.0lf%.1lf%.2lf%.3lf%d%d%c %d****** %s %lf****** %s ****** %s %d****** %s %dInsufficient memory available. Unballanced comment terminators beginning on line Looking for signal name but encountered EOF on line Bus vector not terminated properly on line Illegal number on line Illegal vector range indicator on line Found EOF before proper statement termination on line Illegal time units on line Illegal time (cannot be <= 0) on line Syntax error; statement terminator not found when expected on line Illegal number on line A vectored pin and a non-vectored pin both have same name - line A vectored pin has been declared with the same vector number more than once - line Unrecognizable or undeclared item - line Pin vector for '%s' has not been defined - line Group name cannot be a vector - line Malformed statement on line Error in string syntax on line Illegal radix - line Vectored pin listed twice in INPUTS statement - line Expected " or ' around text string - line EOF encountered before end of text string - line Illegal syntax in Terminate Command - line EOF encountered before end of file name - line Illegal syntax in SOURCE_FILE or REFERENCE_FILE Command - line Illegal syntax in TABULAR_FORMAT, SCRIPT_FORMAT or WAVE_FORMAT Command - line Illegal syntax in STATE_TRANS Command - line Illegal syntax in STATE_TRANS Command - line Too many state translations specified - line No REPORT file name specified. Unable to find beginning line number - line Illegal $ keyword in format description - line EOF found while loading states - line EOF found while skipping whitespaces - line Unable to find BEGIN_STRING in Vector file String too long - line INPUTS or OUTPUTS statement must occur before BUSFORMAT - line BEGIN_LINE, illegal value - line Illegal group number in $GSTATES - line Illegal number after $SKIP - line Illegal group number in GROUP command - line $pins keyword illegal in TABULAR_FORMAT - line Illegal Step time - line Expression too complex - line Max bidirect_control statements is %d - line Expected '=' character - line Expected 'input' or 'output' - line Expected 'when' - line Illegal syntax - line Expected control pin name - line BIDIRECT_STATES defined, can't have both - line BIDIRECT_CONTROL defined, can't have both - line Too many states, max = 13 - line Syntax error, expected INPUT or OUTPUT - line Syntax error - line %s : Command is only valid for ANALYSIS_BLOCK - line %s : Command is only valid for COMPARE_BLOCK - line Syntax error : '%s' - line Error number %d - line %d Command file too large Illegal number - line Syntax error in IVF file - line Maximum number of GROUPS exceeded - line Maximum Program buffer size exceeded. - line The first item in this statement is unrecognizable. - line Pin name is too long (63 char max)- line BUSFORMAT syntax error, possibly missing '=' sign - line BUSFORMAT syntax error, unrecognizable bus name - line Maximum number of pins exceeded - line ALIAS pin name not found in Reference File. Syntax is: "ALIAS ref_name = new_ref_name;" - line Error number %d - line %d XMENF run was unsuccessful Syntax error in ALLIGN_TO_CYCLE - line ALLIGN_TO_CYCLE illegal strobe time - line This Version only supports XMENF - line Pin in CHECK_PINS not in both vector files - line Illegal COMPARE_TYPE - line Expected @ after pinlist - line Empty vector file. ****** %s Syntax Error - line For Reference File PCAP requires: TABULAR_FORMAT PiE; - line ****** %s Unsupported Vector format. - line MAX Number of TIMESETS (%d) exceeded in Analysis. Illegal UNITS/RESOLUTION, only .1, .01 & .001 allowed - line Illegal syntax in control expression : line Illegal syntax in control expression - line Error number %d - line %d Insufficient Memory available. Ref. line - %d %s %s - line Error number %d - line %d %d %d Warning: %s %s D00<0H0T0`0l0x00000000000000 0,080D0P0\0  0 9 o{oBo8CB\ ooCD/'?? , ;>]<[B?;=@d* , :.- ,;<[=&|; ,=;() &|??R@RDRHRLRPRTRXR\R`RhRpRxRRR2.2.4dd?@bM___vdate-hostidS3_ROOTvread.bin 2>&1) >> _vread.ver_vread.verx_xmenf.errSDMTCASE_SENSITIVETRUEFALSETEMP_FILE_SUFFIX.INPUTSOUTPUTSBIDIRECTSWHITESPACEBEGIN_LINEBEGIN_STRINGBUSFORMATCYCLETERMINATETABULAR_FORMATSCRIPT_FORMATWAVE_FORMATSOURCE_FILEAUX_FILEREFERENCE_FILETIME_OFFSETSTATE_TRANSSCALEMAX_UNMATCHEDALLIGN_TO_STEPALIGN_TO_STEPALLIGN_TO_CYCLEALIGN_TO_CYCLEGROUPBIDIRECT_CONTROLBIDIRECT_STATESBEGINKEEP_IVFGEN_STATUSSAMEREF_BLOCKSRC_BLOCKANALYSIS_BLOCKCOMPARE_BLOCKEND_vread1.vec_vread1.cmd_vread1.sts.vcap.sts__src.vec__ref.vec__ref.vecCYCLE may be required for selected options - none is specifiedThe default CYCLE will be 100.0 nsHOMES3_ROOTvread.bin USE_CYCLE_FILETITLEUSE_TRACE_FILEUSE_AUX_FILEUSE_TIMING_FILEUNITSABSOLUTE_TIMEPINS[]COMPARE_BLOCKANALYSIS_BLOCKCHECK_PINSRESOURCE_GROUPALIASRESOLUTIONCHECK_MAX_DELAYSGLITCH_CHECKILLEGAL_STATE_CHECKLEGAL_STATE_CHECKDELAY_TRIGGERDEFINE_STROBESSIMUL_TRANSTRANSITION_STATISTICSCREATE_TIMING_FILECYCLEUNITSREPORT_FILETIMING_FILEDYNAMIC_TIMINGCYCLE_BOUNDARYIGNORE_INPUTSCOMPARE_TYPEDONT_CAREMAX_MISMATCHESMAX_MISCOMPARESMISMATCH_DISPLAYMISCOMPARE_DISPLAYMASKMASK_PINSCOMPARE_WINDOWSTABILITY_CHECKSKEW_TOLERANCEBEGINENDvcap.rptwCYCLE may be required for selected options - none is specifiedThe default CYCLE will be 100.0 nsNo CYCLE has been defined - default will be 100.0 ns AUTOTIMEAITIMEARTIMEATIMEDITIMEDRTIMEDTIMESTATESISTATESOSTATESSKIPEOLPINSPINGSTATESNEWLINESKIPSKIPTO_OTIMEOUTPUTINPUTWHENDEFAULT_INPUTDEFAULT_OUTPUTPIECBCQUESTIVFKEEP_SIGNALSWIF -KEEP_SIGNALSCYCLECYCLE_DATA HEXOCTBINDECNOCOMPACT-NOCOMPACTINPUTS-INPUTSOUTPUTS-OUTPUTSWHEN-VERBOSE-FORMATVTRANOUTPUTOUTPUTSINPUTINPUTSDEFAULTINPUTINPUTSOUTPUTOUTPUTSDEFAULT[][][]STROBESWIDTHMARGINOFF_TIMEWINDOWMAX_1_TRANSMAX_0_TRANSrb.gl.il.sta.glr.ilr.star]IGNORE_STATESMAX_WIDTHPIN_LIST*INPUTS-INPUTSOUTPUTS-OUTPUTSSTATESMIN_WIDTHPIN_LIST*INPUTS-INPUTSOUTPUTS-OUTPUTS-IGNORE-MARKSyntax Error, expected '->' NRZNRZNRZRZRORCSBCRXBIDRSHIFTRO2XRZ2XUNKUNINITSTBS3_LICENSES3_ROOT/sdmt.enablevcapPREVIEWDEMOping -s 64 1 > 1 packets transmitted, 1 received, 0%1 packets transmitted, 1 packets received, 0% packet lossdate +%D > rdate > rsysdef -h > rbrbBY_VECTORVERBOSEBY_PINENDMISCOMPAREOUTPUTSINPUTS-INPUTSOUTPUTS-OUTPUTSREPORT_DELTA_DELAYS-REPORT_DELTA_DELAYS-INPUTS-OUTPUTSINPUTS-INPUTSOUTPUTS-OUTPUTSTIMECONDITION-ABSOLUTEMASK_CHARACTERError: MASK_CHARACTER not used in vcap maskingOUTPUTSINPUTSNOTTIMECONDITIONTRANSITIONCONTROL_TRANSITIONLAST_VECTOR-ABSOLUTE-CYCLEError: Unrecognized keyword: -10 TIME rm erase ALL_INPUTSINPUTSThere are no INPUTS In file.ALL_OUTPUTSOUTPUTSThere are no OUTPUTS In file.PURE_OUTPUTSThere are no PURE_OUTPUTS In file.PURE_INPUTSThere are no PURE_INPUTS In file.BIDIR_INPUTSThere are no BIDIR_INPUTS In file.BIDIR_OUTPUTSThere are no BIDIR_OUTPUTS In file.*There are no signals In file.Error: Illegal expressionError: Illegal expressionDEFAULT_INPUTDEFAULT_OUTPUTDEFAULTOTHERWISEError in syntax: Error: Illegal expression0BBBCDH    h CCDEHWX E1EDER^ mtWX}G^p tWX}GL^ tWX}E^ tWX}H0^ tWX}HX^ tWX}Hx^ tWX}H^  tWX}H^h tWX}E^  [\ GXDh4ڰ P (2x ;ED`8@LCSI[Faxd p[yi@ D"ј x G ] HXxDGDCFx8'D 2Hp;G EGd O[_QH  gG0u{ H, eP z8_@  a  JH  GxP D%h /! 7t C0h HLQzWh  f[pHdwh Wxx   FH@ [ x  F$@ ǀ F` FG(Wp13  :F8EVE`Z` u` }h D۠< FFH\޸l FC} G@< `-  G4{dd#E0F8HT A`KH UGb`kDs4 }\ H(W CFz0_x HFX[C%40\ 5WS<0 JFLSH_Wd[m`\ t HtͰ8H0PFFP[ոGG(L WXzp GDW L * 3W8@EICOlZE^Y` iG<pǬ`H x  -@ G<cz{H `VWtPGTD G5   FHx*cX 7y=FGQHTWGg u!P %@ z8 D `X  ` G, AE!H , d8 ` F   ǰ (xX 0W 54 A@ KQ [W `F iF sF ~D  II\  D  E@ ! E 8 `@  D  x xP @ \8X  Gh F  ) 5W >| K YH _y eE r {X H F հ w@ ` 3X G | 8 8| Dt  p`8 `x@  8d W  E +F  3F ) @C HSp ZDH  VF` aG8 g rE z F0 L P  h F\ t  D, D մ z F F,   ~p F D\ x $W )  4 @ ;9 H E$ P0| [u ef  s ~͠ | Xh  ` x h ͨ G`    (| ` D8  H( H<IT x@ ( +G 5` 8 =F Cs JC TX Y=` b {  p F   nؐ p HP  F W[DP X G| d PT L FG&X+P3  @F@Gx\VGg qDŽ  Ҁ@ q xHXǤ @ İ  F< FT( [DX FDG\ `@ % 2Gp5W. = FD0MWhZG(e@qFzG\ @@ @l F( ?yC*HHHDG$[8, Ft 7`  E wFhW( #LH 0 T  D ѰC0JD NF4U cEh kxHshW\ ~@ *D@ GGPP x Ș8 {G\ F ǨHh P# $Hl,H@7xB Mt X<_zXeoA $ {WS4FD GWlz[CG,DG FWX\HL DH8Fz WH  D xX E 4SO $Fp2H<0 D[@L  Rdl `WeX nG{ 0 H`:p x@!<R@ DDFzH$x W vcapcrti.scrt1.s__get_exit_frame_monitor_ptr__do_exit_code_ptr__crt_scratchvalues-Xa.cDrodata.rodatavcap.cBbss.bssDdata.datavcap0.cvcap1.cvcap3.cvcap4.cvcap5.cvcapform.cvcaputil.cerrors.ccrtn.s_END__START_stboutgroup_pinsdblltnum_strobessscanfpin_chkget_bctim_file1tim_file2pin_valsABSOLUTEvrsts_fatexit__vdateaddspcheck_timesetsbus_sizebictrl_blkget_alias_get_exit_frame_monitorinit_comp_varslinecntstren_charNUMPINSget_bsDOUBLE_ERRORvcntcmdlinenew_cycle_startsleepfprintfkeep_ivfget_check_listget_stransmask_ptritem_term.st_llongmin_rdelay_timeget_nlnpin_alloc_cntphys_linebi_cmptr_stat_ignoretget_itemmis_msgtnum1vrcmd_fget_svnumtest_intbs_outppin_grouppin_mask_cnttime_offsetpass_linesget_boundaryspec_rdelayappendstrcatgethostidset_mischeck_stateccmpipin_vecmask4process_vectorkeep_vgenENDMISrelink_bidirsibufdmin_timeupdaterrorabc_flagerrorbtrigger_charerrorcerrordno_ref_block__ctypemax_rdelay_timeget_spec_delayscunitsdo_terminatecheck_delay_flagst_compnew_get_maskspan_lines__fsr_init_valuecmd_stateget_resource_grplog_timesetis_int__dtouevaluatecyclesteppin_nam_termget_comp_typenew_control_exprtoff_last_etextcomp_time_ptrmask_exprfstatusuncheck_inputsgroup_alloc_cntmis_itemlargest_timenum_unmmake_keynext_lbufVtranLinkcombdir_flagcyclevalpin_maxget_scaledelta_minfile_rmtr_stat_ignoreffcmdcomp_time_PROCEDURE_LINKAGE_TABLE_oltimetlastdelta_maxget_ref_statestr_stat_pinsrvfmin_fdelay_time_GLOBAL_OFFSET_TABLE_doing_pinscopy_edataget_dont_carebs_flagipin_nam__filbufaux_filedbllteget_pin_nummask_trans_flagosrc_fileipin_cntboundary_timepin_valvec_strtnocompactcurrent_trcreftimeboundary_pinGLITCHfinptime_tollbptrpin_cmps3_RESYNCVprocloadlinesskip_sepmbuf__xargv_environ_exitmin_rdelayONEskip_whitelookupmax_fdelay_timedelay_start.st_float_foreffwrite_vgenDVERBOSEmis_codeget_illegal_infonext_timestrobe_flagpstrobeWarningmax_timeset_ptrget_stepsave_pintypeverboselast_cycleflush_eventscomp4toff_flagbus_charsdebugmax_tran1_allowreport_glitchpin_allocis_vectim_formatcheck_strobesget_pin_namdont_care_in.st_intBUFDEPTHfix_inamesspaces__xargcbdrctlis_groupstrobe_groupfirstvec_outreport_illegalterm_stringstrt_pcferrinsert_compmask_timeget_timing_filefsrccode_cntseparatorautot_flaggetenvget_opmainuutimefgetc__cg92_usedslashdoing_outsvsrc_fcheck_terminatetab_formipin_typestepvalmin_fdelayget_group_initstrobe_margincomplprint_headertrans_timeoref_filebegin_stringdo_analysisILLEGALblinetimestepnew_get_exoplstate.st_double_foreffbusformatsrc_timeo_out_stateis_pinget_unmstmt_termget_strobesTcomparefreeget_tr_statread_pinvrvec_fclear_pinfrefget_date1__environ_lockunm_cntsig_nam_termsprintfget_orig_fileline_startDELTApinlst_cntBUFSIZEdelay_endget_a2cupcdbleq_resget_inputsgen_statusrpt_mismatchsystemstrcpylastcharsbptrsiglist_terma2sconform_groupswhich_vptrvec_rngereallocnew_check_ctlsbufsplit_bidrvref_fget_cyclei_in_statemake_groupanal_varscomp3s_statesbegin_linemain_bufscript_load_ovfanal_inputswr_vecprocess_svectorreal_timestrobe_widtherrornum_transmodulogl_datafcloseget_word.st_doublepintype_flag__iobtab_load_ovf.st_floatlicenseotimesetup_delaysget_skewget_busf__1cG__CrunMdo_exit_code6F_v_mask_transbus_flatwv1delay_end2tr_stat_recordbs_inpnumbvecsdmax_time.ld_doubleftimpin_formspec_fdelayv_formatwave_load_ovflengthpin_wtimetimeset_flagtnumbstringload_sstatespin_ldmask_ctl_statelast_timeset_ptrget_unitsdate_fmask_flaggroup_cntnam_cmpcompact_formatnew_check_maskget_glitch_infocase_sensitiveget_signamloc_ptrterm_valtime_offsstrlenget_resbictrl_cntdblgteget_pin_list_lib_versionstrobe_offput_itemungetcdelay_start2Check_Casefile_formatvec_termmax_tran0_allowoptimize_timesetsvtiming_filedo_keepvload_struse_vread1dbleqgetpidboundary_statesdisplayget_src_statesneed_cycleget_date.ld_llongwhitespaceget_tim_filereport_instabilitydo_comparetrans2dont_care_out.ld_intsrc_bufmax_rdelayprtimeo_in_stateunlinksave_timesetwindowforce_pintypeget_max_misprint_misload_statesdelay_triggerSILENTdblgtnewstatesget_rpt_filegroup_nammismatch_cntsrc_ptrminpw_flagtiming_trcs3_getlinewrite_wavepin_rdstatsterm_typestate_transfrptsecond_ti_out_state.ld_floatset_pintypeckeyfoutpskew_typeresolutionsyncfopenpassunits_scaleparamswr_statfputcfirstvecvtime_DYNAMICskip2eol___Argvanalysis_flagSTABILITYrm_filevcsts_f_finicomp3r_statesnewvpin_masktr_stat_flagget_rnummismatch_maxdo_hdrmax_fdelaypin_statemallocabs_timetraceTIM_VERBOSEalloc_timesetlast_pin_cnteoffconcat@(#)ctype.h 1.35 04/09/28 SMI@(#)ctype_iso.h 1.3 04/09/28 SMI@(#)feature_tests.h 1.24 04/09/28 SMI@(#)ccompile.h 1.2 04/11/08 SMI@(#)isa_defs.h 1.27 04/10/01 SMI@(#)ctype_c99.h 1.2 04/09/28 SMI@(#)stdlib.h 1.51 04/06/30 SMI@(#)stdlib_iso.h 1.9 04/09/28 SMI@(#)stdlib_c99.h 1.2 04/03/29 SMI@(#)stdio.h 1.84 04/09/28 SMI@(#)stdio_iso.h 1.8 05/08/16 SMI@(#)va_list.h 1.15 04/11/19 SMI@(#)stdio_tag.h 1.4 04/09/28 SMI@(#)stdio_impl.h 1.14 04/06/17 SMI@(#)stdio_c99.h 1.2 04/03/29 SMI@(#)malloc.h 1.11 97/08/23 SMI@(#)types.h 1.85 05/04/11 SMI@(#)machtypes.h 1.13 99/05/04 SMI@(#)int_types.h 1.10 04/09/28 SMI@(#)select.h 1.19 04/01/28 SMI@(#)time_impl.h 1.11 05/05/19 SMI@(#)time.h 2.76 05/06/14 SMI@(#)time.h 1.44 04/09/28 SMI@(#)time_iso.h 1.4 04/09/07 SMIacomp: Sun C 5.8 2005/10/13@(#)stdio.h 1.84 04/09/28 SMI@(#)feature_tests.h 1.24 04/09/28 SMI@(#)ccompile.h 1.2 04/11/08 SMI@(#)isa_defs.h 1.27 04/10/01 SMI@(#)stdio_iso.h 1.8 05/08/16 SMI@(#)va_list.h 1.15 04/11/19 SMI@(#)stdio_tag.h 1.4 04/09/28 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04/01/28 SMI@(#)time_impl.h 1.11 05/05/19 SMI@(#)time.h 2.76 05/06/14 SMI@(#)time.h 1.44 04/09/28 SMI@(#)time_iso.h 1.4 04/09/07 SMI@(#)ctype.h 1.35 04/09/28 SMI@(#)ctype_iso.h 1.3 04/09/28 SMI@(#)ctype_c99.h 1.2 04/09/28 SMI@(#)stdlib.h 1.51 04/06/30 SMI@(#)stdlib_iso.h 1.9 04/09/28 SMI@(#)stdlib_c99.h 1.2 04/03/29 SMIacomp: Sun C 5.8 2005/10/13@(#)stdio.h 1.84 04/09/28 SMI@(#)feature_tests.h 1.24 04/09/28 SMI@(#)ccompile.h 1.2 04/11/08 SMI@(#)isa_defs.h 1.27 04/10/01 SMI@(#)stdio_iso.h 1.8 05/08/16 SMI@(#)va_list.h 1.15 04/11/19 SMI@(#)stdio_tag.h 1.4 04/09/28 SMI@(#)stdio_impl.h 1.14 04/06/17 SMI@(#)stdio_c99.h 1.2 04/03/29 SMI@(#)malloc.h 1.11 97/08/23 SMI@(#)types.h 1.85 05/04/11 SMI@(#)machtypes.h 1.13 99/05/04 SMI@(#)int_types.h 1.10 04/09/28 SMI@(#)select.h 1.19 04/01/28 SMI@(#)time_impl.h 1.11 05/05/19 SMI@(#)time.h 2.76 05/06/14 SMI@(#)time.h 1.44 04/09/28 SMI@(#)time_iso.h 1.4 04/09/07 SMI@(#)ctype.h 1.35 04/09/28 SMI@(#)ctype_iso.h 1.3 04/09/28 SMI@(#)ctype_c99.h 1.2 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VECTORDATA_END 0 %lf%lf%d%lf%u%lf%dFLEXJ750+T2000r---> %s G%dEntering ReadSignals() ---> %s [%d]<%d>[%d]<%d>Leaving ReadSignals() E0E1EMEXWCW0W1WMFNZE0E1EMEXFNZWCW0W1WMEQUATIONSPer%lf%lf%lf%lfTimeList: %.1lf %.1lf signal %s in TimeSet %swTNAMS TNAM 0 %s TIMESET %s CYCLE %lf %s[%d] %d X %.3lf %.3lf %.3lf %.3lf %s %d X %.3lf %.3lf %.3lf %.3lf TIMESET_END TNAM_END TNAMS_END FORMAT %s %s[%d]; R%-10d %-*s ; Entering vHP93000() rwVECTORDATA %s %d%d>>%d SQPG RPTV %d,%d; %d%d>>%d SQPG RPTV %d,%d; VCD %.3lf 0 %d %lf %d %d >>0 SQPG PADDING; ---> %s %dVCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 %dTSET %.3lf %s VCT %.3lf 0 %d %lf %d %d )>%d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 %c Chain%dChain%dwVECTORDATA %c VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d SCAN %.3f %s %d %s %s ; %d>>%d %d>>%d VCD %.3lf 0 %d %lf %d %d >>0 TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d VCI %.3lf 0 0 _basic_ts.txt_tsets.txt_esets.txtrrrwVECTORDATA %c %c %dVCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 TSET %.3lf TS%s TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d VCD %.3lf 0 %d %lf %d %d >>0 %d%d>>%d %d>>%d VCI %.3lf 0 0 wTNAMS TNAM 0 %s TIMESET %s TIMESET TS%s CYCLE %lf %s[%d] %d X %.3lf %.3lf %.3lf %.3lf %s %d X %.3lf %.3lf %.3lf %.3lf TIMESET_END TNAM_END TNAMS_END %lfns%dRLRHRLRHNRRLRHNRRLRH%s_tsets.txtr%s_esets.txtrNR%dNROffRLRHOff%s_basic_ts.txtrrDFF 1.1NRNROffRLRHOffrWarning: '%s' - unrecognized keyword in lvmadr file. Warning: '%s' - unrecognized syntax in lvmadr file. %d%d%lfns%lfnsrrrwVECTORDATA %c %dVCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 TSET %.3lf TS%s VCT %.3lf 0 %d %lf %d %d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d VCD %.3lf 0 %d %lf %d %d >>0 %d%d>>%d %d>>%d VCI %.3lf 0 0 %lf%lf%lfs3_getline #%d: %s ms3_getline #%d: %s [%d]<%d> %s ***** Error: Error in Memory Allocation '%s' Unable to open tmp file for write. %s '%s' Unable to open ovf_file. %s ***** Near line %d. '%s' Unable to open cmd file. '%s': Scan chain not found for scan signal: ***** Near line %d in Vec File. Error during write - check disk space '%s': Error in Memory Allocation '%s': %s '%s': Unexpected EOF ***** Near line %d in Vec File. '%s': Undeclared Signal Name ***** Near line %d in timing File. %s %s ***** Near line %d in Vec File. '%s': Undefined TimeSet ***** Near line %d in Vec File. '%s': Undefined keyword ***** Near line %d in Vec File. '%s': Undefined Signal Name ***** Near line %d. '%s': Syntax error, unknown keyword. ***** Near line %d. '%s': Error reading header: ***** Near line %d in timing File. '%s': Pin in command file not found in ovf_file ***** Near line %d. Error code %d 1 ***** Error: %s ***** %s ***** Near line %d. ***** Warning: %s ***** Near line %d. Timing file name indicates possible wrong format (%s-type timing file) '%s': Undeclared Signal Name ***** Near line %d in timing File. '%s': Unexpected value in timing line: ***** Near line %d in timing File. '%s': Unexpected number of fields in timing line: ***** Near line %d in timing File. '%s': Unrecognized time field in timing line ***** Near line %d in timing File. '%s': TimeSet not found for edge set number ***** Near line %d in esets Timing File. Possibly unable to map Timing to static waveform for %s Incompatible edge times for %s Unsupported multi-clock value; using return format for %s Warning code %d @%15.3lf - ; for: '%s' for: '%s[%d]' for: '%s'[%d]<%d>USE_AUX_FILE %s USE_TRACE_FILE %s ABSOLUTE_TIME UNITS 1.000000 PINS %c%s %c%s[%d] ; 0%dChain%dChain%dChain%dChain%d%s[%d])>%d %dSCAN %.3f %s %d %s %s %s %s ; )>%d SCAN %.3f %s %d %s %s %s %s ; )>%d SCAN %.3f %s %d %s %s %s %s ; SCANCHAIN %s SCANLENGTH %d SCANIN %s SCANOUT %s SCANCHAIN_END %lgUser-defined AC Specs Category %s not found; using Category %sTypMinMax%s_acspecs.txtrTypMinMax#NUndefined ACSpecs variable %sACSpecs variable %s selected (%s) value in Category %s undefined#N/AI/O%s_pinmap.txtr%s.tdl%s.sockrwTNAMS TNAM 0 %s TIMESET %s CYCLE %lf %s[%d] %d X %.3lf %.3lf %.3lf %.3lf %s %d X %.3lf %.3lf %.3lf %.3lf TIMESET_END TNAM_END TNAMS_END ReadProgTimeVal: ibuf = %s TGCD*%lfNRZCLK%dSTRB%dWSTRB%dDRE%dT%d%lfNSRATRATERAT%d%dD%dTS%d%cA%dTS%dB%dTS%dC%dTS%dS%dTS%dW%dTS%d%c%d%lfnS_signaltimingT%dNRZT%d%s.progr%dChain%dVCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d >>%d >>%d VCD %.3lf 0 %d %lf %d %d >>0 TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d SCAN %.3f %s %d %s %s ; rrwVECTORDATA %s %d%dTSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 }[%d]<%d>%s.pin%s.pinrT2000 %d TIMING MAPS: %s %s %s END T2000 TIMING MAPS: %c@%lf%cS%lf%cS%c@%lf*%*sTimeTimePer_per_TimPinFormatPeriodTablePinPinLHTXxlhtZLHTXZxlhtsignal %s in TimeSet %swTNAMS TNAM 0 %s TIMESET %s CYCLE %lf %s[%d] %d X %.3lf %.3lf %.3lf %.3lf %s %d X %.3lf %.3lf %.3lf %.3lf TIMESET_END TNAM_END TNAMS_END %s.tmap%s.tmapr%s.usrv%s.usrvr%s.tim%s.timr} for: '%s' for: '%s'TSET %.3lf %s VCT %.3lf 0 %d %lf %d %d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d >>%d >>%d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d SCAN %.3f %s %d %s %s ; Chain%d%s.patrwVECTORDATA %s _TimTSET %.3lf %s VCT %.3lf 0 %d %lf %d %d %d%dVCI %.3lf 0 0 }[%d]<%d>}Chain%dPreFillPostFillLTX MX %d SPEC MAPS: %s %s %lf END LTX MX SPEC MAPS: Category.TypExprString}evPinConfig}Row}evPins[%d]<%d>evDirectionInputOutputBidirectevDrvFormatNRZRZROevCmpFormatEdgeWindow%lf%lfDriveLowDriveHighDriveDataDriveOffCompareDataSDSDUSUDSDSDUSUSU0/1L/H/XWFMDriveCompareDataColorPeriodCellsignal %s in TimeSet %sNRZRZRONRZRZROSignal %s format mismatch in PatternSetup and TimeSet blocks evEdgeOnDataReturnEdgeWindowEdgeevEdgeOffDataReturnevPinsevDriveevCompareevT0RowwTNAMS TNAM 0 %s TIMESET %s CYCLE %lf %s[%d] %d X %.3lf %.3lf %.3lf %.3lf %s %d X %.3lf %.3lf %.3lf %.3lf TIMESET_END TNAM_END TNAMS_END %s.evarrPatternSetup.evor %c Scan1Scan1VCT %.3lf 0 %d %lf %d %d VCT %.3lf 0 %d %lf %d %d for: '%s'TSET %.3lf %s TSET %.3lf %s VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d VCD %.3lf 0 %d %lf %d %d VCI %.3lf 0 0 VCI %.3lf 0 1 )>%d SCAN %.3f %s %d %s %s ; %s.evorwVECTORDATA %c %c %c enVisionPatternDefault SignalHeaderTypeDefault WaveformTableDefault BackgroundBackground BVVCI %.3lf 0 0 SIGNALS: %d: %s[%d] - %d TIMESETS %s %lf Signal %d format %d timelines %d TIMELINES: %c %s@%lf SCAN CHAINS: %s num cells %d scanin signal %d scanout signal %d TIMESETS %s %lf Signal %d format %d Time1 %lf Time2 %lf Time3 %lf  00<0H0T0`0l0x00000000000000 0,080D0P0\0h0t000000000 \ hX Ah oXoo oo 4 >Ab d?? ;,:=)( =>]<[/^?h% CmgNC k&4BmAeA.@@??PbM>>. &֕=q-<V<2r]CEPTGMksmunpfaC|CCCD$D0EdExEEEFF,FPF`FlGtVERILOG-XL 1.6.0.1regwireregvread6.bin 9.3_vread1.cmd_vread1.sts_vread1.vec_vread1.aux_vread1.trc.dftvUnable to open temp file - check permissionsInvalid KeyT2000LTXstdingzip -dc HP93000HP83000VERIGY83000VERIGY93000AGILENT_93000AGILENT_83000CREDENCESWAVJ750J750+J973CATALYSTFLEXT3300T6600T2000LTXUnsupported FormatT2000LTXOVF_FILENAMETVF_FILENAMESTART_TIMEEND_TIMETMPDIR/AUX_FILENAMEDVC_FILENAMEPIN_FILENAMESCAN_PADCASE_SENSITIVEPINS_ONLYSCANSEPARATE_BIDIRSINTERSPERSE_BIDIRSENB_LOOPSENB_REPSDISABLE_LOOPSDISABLE_REPSPASS_LABELSINHIBIT_COMMENTSCYCLE_DATADFTVIEWVMASTERSIDE_FILE_ASCIIVECTOR_COUNTCATALYSTFLEXJ750J750+LTXSWAVT2000T3300T6600HP93000HP83000VERIGY83000VERIGY93000AGILENT_93000AGILENT_83000-VECTOR_COUNT not supported; will be ignored.DEBUG_ONSCALEKEYCYCLEFILE_FORMATSPECS_CATEGORYSPECS_SELECTORTRACE_ONSILENTUSE_DOUBLEUSE_ABSOLUTE_TIMEBASIC_TIMINGBASIC_TIMING_FORMULASFUSIONCOMPACT_OFFPINS.OENDLEFT_EXTENDTIMESCALEUnexpected EOF in pin fileDFGPSyntax Error in pin fileSyntax error in pin fileSyntax error in Pin fileReadSignalsSyntax Error in VEC fileReadSignalSyntax Error in VEC fileReadSignalFORMATReadSignalsReadSignalsReadSignalsReadSignalsReadSignalsReadSignalsSyntax Error in VEC fileReadDVCSyntax Error in DVC file SPECS blockSyntax Error in DVC file SPECS blockSyntax Error in DVC file SPECS blockSyntax Error in DVC time valueReadDVCReadDVCReadDVCSyntax Error in DVC fileSPECSDVCSyntax Error in DVC filePERIODSyntax Error in DVC filePINSReadDVCReadDVC10ZXSyntax Error in DVC fileReadSignalsRead DVC FileReadSignalsReadSignalsReadSignals.OSyntax Error in VEC fileProcess VectorsSyntax Error in VEC fileSQPGSyntax Error in VEC fileRPTVloop vector countloop repeat countInvalid loop value.loop vector countloop repeat countInvalid loop value.Insufficient MemoryVectorsSQPGVectorsPADDINGRPTVInsufficient MemoryVectorsPADDINGReadVecReadVecHORIZONTAL_SCANSCAN_TYPESyntax Error in VEC fileSTANDARDOnly 'SCAN_TYPE STANDARD' supportedSCAN_TEMPLATESyntax Error in VEC fileSyntax Error in VEC fileSCAN_PORTSyntax Error in VEC fileSCAN_PORT must match a SCAN_TEMPLATE name: Syntax Error in VEC fileINOUTSyntax Error in VEC fileBidirSignalsBidirSignalsSCAN_FRAMEReadVecSyntax Error in VEC fileError in Signal StatesSCANSyntax Error in VEC fileUndefined SCAN_TEMPLATE name: Syntax Error in VEC fileError in Signal StatesPINMissing SCAN before PIN statementSyntax Error in VEC fileSignal not a SCAN_PORT: Syntax Error in VEC fileSyntax Error in VEC fileUnrecognized Statement: Syntax Error in SWAV fileReadHeaderVectorsReadHeaderVERSIONReadHeaderReadHeaderDESTINATIONReadHeaderReadHeaderDESIGNReadHeaderReadHeaderTIMESCALETimescaleReadHeaderReadHeaderSIGNALSignalSignalINPUTOUTPUTBIDIRBIDIR1SCAN_INPUTSCAN_OUTPUT.OSyntax Error in SWAV fileReadSignalReadSignalSignalSCAN_INPUTSCAN_OUTPUTSyntax Error in SWAV fileSyntax Error in SWAV fileReadSignalReadSignalSyntax Error in SWAV fileReadSignalReadSignalReadSignalSET.OsetSyntax Error in SWAV fileSyntax Error in SWAV fileSyntax Error in SWAV fileSyntax Error in SWAV fileSyntax Error in SWAV filesetPERIODAPPLYsetFORCESENSEFORMATsetNRZRZR1STARTSTOPSyntax Error in SWAV fileReadSignalPATTERNSyntax Error in SWAV filePattern.OSyntax Error in SWAV fileSyntax Error in SWAV fileVectorsVectorsCONTROLcontrolUnexpected EOFSCAN_STARTSyntax Error in SWAV filePatternSyntax Error in SWAV fileSCAN_DATAVectorsSyntax Error in SWAV fileInsufficient MemoryUnexpected EOFInsufficient MemorySCAN_ENDLOOPloop countInvalid loop value.loop countInvalid loop value.Insufficient MemoryVectorsENDLOOPLOOPInsufficient MemoryVectorsENDLOOPIllegal ENDLOOP - no matching LOOPPATTERN_ENDPattern > test(A)Syntax Error in SWAV filePattern > cy(B)Syntax Error in SWAV fileSyntax Error in SWAV vector lineSyntax Error in SWAV vector line(A)Number of states in vector != number of signalsFLEXJ750+Unexpected EOF (1)ReadVecvectorvectorPinsDataReadVecReadVec$tsetbasic timingFLEX or J750+FLEX or J750+Syntax Error in J750 fileVectorsVectorsscan_pinsUnexpected EOF (2)Unexpected EOF (3)Unexpected EOF (4)Unexpected EOF (5)vectorReadVechaltvectorReadVecscan_setupimportReadVecReadVecscanReadVecReadScansiReadScanUnexpected EOFScanDataScanDataReadVecReadScanDataReadVecUnexpected EOF (6)Signal not found for source columnSyntax Error in J750 vector lineNumber of states in vector != number of signalsrepeatloop countloopAloop countloop countInsufficient MemoryVectorsVectorsend_loopAloopAInsufficient Memoryend_loopAVectorsend_loopAUnexpected EOF in Timing FileSyntax Error in Timing filemaskSet TimesetSyntax Error in Timing fileperiodperiodcmpmasknrzrzrocmppatnrz.OnrzrzroReadTimingsetReadTimingpinSyntax Error in Timing fileSyntax Error in Timing fileReadTiming - SignalSyntax Error in Timing fileReadTiminghsdvoidReadTimingtiming_setupfloatReadTimingSyntax Error in Timing fileReadTimingedge_setSyntax Error in Timing fileReadTimingd0d1d2d3r1r2format_drvSyntax Error in Timing fileReadTimingformat_rcvSyntax Error in Timing fileReadTiming.O.O**Error: no timing file (aux_file) specified. Required for Read-Back.Syntax Error in J973 fileVectorsRead VectorsuseVectorsimportVectorsexportVectorslvmsetVectorsvector-formVectorsVectorsVectorsRead Vectors:eVectors:opRead VectorsrepRead VectorsRead Vectors:scanRead VectorsRead VectorsRead VectorsRead VectorsRead Vectors:si:so:soRead Scan-outScanDataReadScanDataScanDataUnrecognized keyword.VectorsSyntax Error in J973 vector lineNumber of states in vector != number of signalsSyntax Error in Timing fileSyntax Error in Timing fileReadTimingusepinseqsetReadTimingdefaultpins-form:pinReadTimingReadTimingonReadTimingReadTimingondvar-formdefaultequation-form.O:edgeset:perReadTimingSyntax Error in Timing fileUndefined signal name in timing file.ReadTimingnrrlrhrcnilReadTimingd0d1d2d3c1c2Syntax Error in Timing fileUnexpected EOFReadVecvectorReadVecSyntax Error in Catalyst fileVectorsfiletypefiletypevectorReadVecscan_chainReadScanReadScanReadScanReadScanReadScanscan_pinsReadScanscan_templateReadScanReadScanReadScanscan_in_pinReadScanReadScanscan_out_pinReadScanReadScan}ReadScanSCAN_SETUPSCANReadVecReadScanReadScan>ReadScanScanDataReadScanSyntax Error in VEC fileTSETReadVecUnexpected EOFSyntax Error in Catalyst vector lineNumber of states in vector != number of signalsIllegal ENDLOOP - no matching LOOPREPEATrepeat countLOOPloop countSyntax Error in Catalyst vector lineloop countInsufficient MemorySyntax Error in Catalyst vector lineVectorsVectorsEND_LOOPLOOPInsufficient MemoryVectorsEND_LOOPVectorsSyntax Error in Timing fileReadTimingSyntax Error in SWAV fileSyntax Error in SWAV fileSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetSet TimesetInsufficient MemoryInsufficient MemoryInsufficient Memoryrm Write Error - disk full?Write Error - disk full?10ZF1F0FZFN1FN0FNZF1NF0NFZNE0E1EMEXW0W1WMWXWCCcDdState Character ' ' in Vec line undefined in DVCIllegal event in DVC: State Character ' ' in Vec line undefined in DVCIllegal event in DVC: ReadSignalReadSignalsReadSignalsReadSignalsUnexpected EOFUnexpected EOFScanPinsUnexpected EOFScanPinsInvalid scan_pins directionUnexpected EOFUnexpected EOFInvalid scan_pins directionReadVecReadScansiReadScanUnexpected EOFReadVecReadScanDataNumber of scan states not equal to scan lengthReadVecReadScanReadScan>ReadScanReadScanSyntax Error in VEC fileSyntax Error in VEC filescan state direction not knownSyntax Error in VEC fileReadACSpecsReadACSpecsReadACSpecsMAXTIMESyntax Error in ACSpecs file [Category names]Variable definition not found Syntax Error in ACSpecs file [Variable name]Syntax Error in ACSpecs file [Selector name]Syntax Error in ACSpecs file [Selector value]TypMinMaxUNDEFSyntax Error in ACSpecs file [expression]No LHS for binary opDivide by 0ReadPinmapReadPinmapSyntax Error in Pinmap fileSyntax Error in Pinmap fileSyntax Error in Pinmap fileSyntax Error in Pinmap fileUnexpected EOF (TDL file)ReadTdlPinUnexpected EOF (TDL file)Unexpected EOFReadTdlPinListUnexpected EOFUnexpected EOF (TDL file)Unexpected EOFReadTdlPinListUnexpected EOFReadTdlSignalsint SetupPins()ReadSignalsintDPINPINLISTPINLISTTBLSOCKET ADVENDSignalReadTiming0NSUnexpected EOFReadProgPinListReadProgPinListReadProgGroupAssigmentsIN1OUT1RZO/RZOXOR.OSyntax Error in timing fileENDTGCDTIMINGPINLISTpinlistkindtimingwavekindT1T2STBL.OSTBTReadTdlTimingSyntax Error in timing fileintrate_defsrateUnknown timeset reference in rate statementSIGNAL_TIMINGUnknown timing group reference in signaltiming statementUnknown timing group reference in pinlist statementINOUTIOUnknown timeset reference in wavekind statementRZORZZINVXORUnknown timeset reference in timing statementVectorsCHANNELInvalid DBM CHANNEL valueInvalid loop value.Invalid loop value.Insufficient MemoryVectorsJNISTIInsufficient MemoryIllegal ENDLOOP - no matching LOOPSyntax error in scan vectorUnexpected EOF (Vector file)Insufficient MemoryUnexpected EOF (Vector file)Insufficient MemoryUnexpected EOFSyntax Error in vector fileENDDBMSTPSIDXISTIJNIUnexpected EOF (Vector file)T3300ReadSignalsUnexpected EOF (.pin file)Unexpected EOF (.pin file)Unexpected EOF (.pin file)ReadPinReadSignalsReadSignalsReadSignalsUnexpected EOFT2000ReadGroupUnexpected EOF (pin file)Unexpected EOFT2000ReadGroupUnexpected EOFReadT2000SignalsDomainResourceGroupRead TmapRead TmapReadDVCReadDVCReadDVCReadDVCReadDVCReadDVCReadDVCReadDVCReadDVCSyntax Error in TimingMap fileSyntax Error in UserVars fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in TimingMap fileSyntax Error in Timing fileToo many waveforms for signal Syntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileReadTimingSyntax Error in TimingMap fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileSyntax Error in Timing fileUDZLHXlhxReadDVCReadSignalsReadSignalsReadSignals.O}Expected ';'Expected V open-braceALLPINSExpected ';'Expected V close-braceState Character ' ' in Vec line undefined in DVCIllegal event in DVC: State Character ' ' in pattern line undefined in Timing waveformsIllegal event in Timing waveforms: No WaveformTable reference on first vectorInvalid loop value.Invalid loop value.Insufficient MemoryVectorsJNISTIInsufficient MemoryDomainSyntax error in scan vectorEXITSCSHExpected SH (horizontal scan required)Insufficient MemoryUnexpected EOFInsufficient MemorySyntax Error in vector fileExpected W open-braceALLPINSExpected W close-braceExpected W close-braceEXITIDXISTIJNIJSCEXITSCSHSTSSNOPUnrecognized Vector typeSyntax Error in vector fileSyntax Error in Signals dataSyntax Error in WaveformTable blockSyntax Error in TimeSet blockReadSignalsReadSignalsReadSignals.OReadSignalsReadScanSignalScan Pad CharsRead SpecRead SpecSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileSyntax Error in PatternSetup fileReadPatternSetupSyntax Error in PatternSetup blockSyntax Error in time valueReadDriveBlockToo many waveforms for signal ReadCompareBlockToo many waveforms for signal ReadCellBlockReadWFTUnrecognized WaveformChar: ReadRowBlockReadTimeSetReadEvaSignalHeaderWaveformTableenVisionObjectSpecPatternSetupTimeSetBackground VectorsBackground VectorsExpected Scan1Expected BVExpected semicolonState Character ' ' in Vec line undefined in DVCStatic Scan StatesScan StatesReadPatternhX! \ h t x  0 4  G|8  7 J Xdt s|$| G@G(GGHHHHw  @ (     &( 8 EĀ Y@( lW {\ @p  `    $ t@   `8 x t 0@ DL T@ d$ r@ P x x` l@x | X T `   ` #` . ;  FR ^pk{P  (  hΠ Р  x @   ڀ| `  *, 6 < A` Oa߀t pd |  D       0 ' D 3 ? S | _ q`h !  t -  .@ .8 / < /`x / 40 H4`< X: h; w> E` J@\ L  W  m p  q s ,044x Bz L{ `<l@ `, 8   T   (    @  ` "`4 :t L  _ o     @  P ` P ( "@ d #&@ 8p B,@ QT \X j\ }/  / 2 R| S`& z  D h p  @ +D ;`0 K ^l i0 ~| @     | t x `  # 4` >@ P _ m ~ ˀ  ͠ @ `  G  / : %D`( <wp S j  h x8 ' Wh dP 0 "@ 9` P gx@ ~L p ( X ; X F N XH 6`  Mlx d { X   Έ x h  3/ J> as xy(  (    ,  z80 p 0 G ^ȸ uG@s@ @ s T T !  / 7` (`0  43 :CJU_e8j!  qozo 8p  l a T k|,D  %CP 0kp58=0CL Q *L [Xcxih  o7 ( sr@ }0  H ! 0X` \ 8D    #  `$ H  s@  !* 0 7k`<PF N(T `f/D m t  :P ~  x< @kt kl 8 }@8  T F k >8s@!#`,8: @ =5 H0R [ f H keQJ , l   ƀ0 kh"@  `  # 0*X39L :@AE`` KU] Z f(p'/ v  9X ,%` 8 0 $6  D    :i | Bd  v &<\ A\  G!` P X "pkxu  \k4 3 rN  0  HHt4|x9 h | , #q  *s4=xC . Jkd8 d OX:@ ^ Tev@ ru@  {/ @ d `  |@ K d`  <X T  $@  d  '-5 <G,Q{Z  pa= d t vread6.bincrti.scrt1.s__get_exit_frame_monitor_ptr__do_exit_code_ptr__crt_scratchvalues-Xa.cDrodata.rodatavread6.cget_dateVersionInput_varOutput_varBidir_varptmpchggplstPinGroupsJLT2000FindTimelineFormatJLT2000FindSignalFormatFindHP93000FormatJLReadDvcSpecsJLReadDvcTimeFindHP93000TimingvHPgenAuxTimWriteVmasterSignalsWriteVmasterVectorvJ750genAuxTimSkipTimingCommentvJ750edgeTime_flexNRtimeSetmodulo_flexRtnTimeSet_flexOtherTimeSetJLCheckForBidirsvFlex_timCurrFieldSepvJ750_basic_timGetFlexTimeSetvJ750createScanChainsvHPcreateScanChainsvJ750genTrcScanvHPgenTrcStatesvHPgenTrcScanvJ750genAuxScanis_dbleqFindCategoryCategoriesAddCategoryCurrCategoryFindVariableVariablesAddVariableSetVariableValueSetVariableDefFindVariableDefReadHeaderReadItemSkipHeaderReadDefFieldReadVarDefIsFirstPassReadACSpecsCurrSelectorFoundForwardRefGetOperatorTypeIsFieldSepIsTimeUnitsNumPrefixs3_Eng_Prefixs3_Eng_ExpReadOperandGetExprValueFindGroupAddGroupAddPinReadPinHeaderReadGroupDefReadPinItemReadPinmapGetFirstPinGetNextPinJLAddAdvGroupJLadvTimingGroupsJLFindAdvGroupJLAddAdvPinJLGetFirstAdvPinJLGetNextAdvPinJLReadTdlPinJLReadTdlPinListJLReadTdlSignalsJLReadSockSignalsJLReadAdvSignalsJLAllocTimingDataJLnumTimeSetsAllocJLtgTimesJLnumTGsJLSetPinDirJLGenAuxTimJLReadProgTimeValueJLSetTgTimeJLReadProgPinListJLReadProgGroupAssignmentsJLProgToReaderTimingJLnumTimeSetsJLReadProgTimingJLAddTdlVarJLtdlVarsJLGetTdlVarValueJLTdlTimesetIDJLTdlEdgeStrToValJLStripSignalSuffixJLSignalTimingAttributeJLTdlToReaderTimingJLReadTdlTimingJLReadAdvTimingJLReadScanPinsJLWriteVecJLReadAdvLoopJLEndAdvLoopJLReadScanVectorJLReadAdvVectorsJLT2000ReadPinsJLT2000ReadGroupJLT2000ReadPinFileJLAddTmapEntryJLtimingMapsJLnumTimingMapsJLnumTimingMapsAllocJLAddTimelineJLGetTimeJLT2000ReadUserVarsJLuseParamsJLT2000ReadTimingMapJLT2000ReadEventsJLpinListJLT2000ReadPinWaveformsJLT2000ReadTimingJLT2000FindFormatJLT2000FindTimingJLT2000GenAuxTimJLAddBidirectsJLT2000ReadTimingFilesJLT2000ReadPerPinStatesJLT2000ReadStatesJLT2000WriteVectorJLT2000WriteVecJLT2000ReadAdvLoopJLT2000SkipVecHdrJLFindScanChainJLGenFlatScanVecJLGenScanVecJLT2000ReadScanVectorJLT2000ReadVectorsJLSkipBlockJLLtxAddBidirectJLLtxReadSignalssigErrMsgJLLtxReadScanSignalsJLpadCharJLAddSpecEntryJLspecMapsJLnumSpecMapsJLnumSpecMapsAllocJLFindSpecEntryJLLtxReadSpecJLSkipToValueJLReadQuotedValueJLLtxReadPatternSetupJLGetLtxTimeJLReadEventtimingErrMsgJLReadDriveBlockJLReadCompareBlockJLReadCellBlockJLLtxReadTimingJLLtxFindTimingJLReadEvDriveBlocktsetErrMsgJLReadEvCompareBlockJLReadRowBlockJLLtxReadTimeSetJLLtxGenAuxTimJLLtxReadEvaJLisMXJLAddBkgndVecJLnumBkgndVecsAllocJLbkgndVecsJLnumBkgndVecsJLReadTimesetRefJLfusionPrevVecTimeJLfusionPrevTsetvecErrMsgJLReadRepeatCountJLReadScanRefsJLLtxMapEventJLLtxWriteVectorJLprevTsetJLLtxWriteVecJLfusionPrevRptCtJLGenScanVecsJLLtxReadStatesJLLtxReadPatternJLltxDebugBbss.bssDdata.data___const_seg_900000901___const_seg_900001101___const_seg_900001201___const_seg_900001702___const_seg_900002301___const_seg_900002601___const_seg_900002701___const_seg_900003001___const_seg_900003401___const_seg_900003701___const_seg_900004101___const_seg_900004301___const_seg_900004501___const_seg_900004701___const_seg_900004801___const_seg_900004902___const_seg_900005101___const_seg_900005301___const_seg_900006101___const_seg_900006301___const_seg_900006501___const_seg_900008801___const_seg_900009301___const_seg_900009501___const_seg_900009601___const_seg_900009701___const_seg_900009801___const_seg_900011901___const_seg_900012101___const_seg_900012201___const_seg_900012301___const_seg_900012601___const_seg_900013301___const_seg_900013401___const_seg_900015601___const_seg_900016101___const_seg_900016701___const_seg_900017501___const_seg_900018501___const_seg_900018801___const_seg_900019102___const_seg_900019701___const_seg_900020201___const_seg_900020301___const_seg_900022301___const_seg_900023401___const_seg_900024201___const_seg_900024501___const_seg_900025201___const_seg_900025301crtn.s_END__START__edataslashLoopCycleTimeKey_abus_flatJLT2000WriteCycVectorKey_bPrintTimeITSet__xargv_environFindChainstrtodvSWAVTestDirget_name_PROCEDURE_LINKAGE_TABLE_fcloses3TmpDirSILENTJLisFUSIONvcd_scaleQSTAR_end_startpin_filevec_strtDBLTERMmeoffdebugDOUBLE_ERRORsbufcallocDFT_sidefileseparate_bidirssprintfJLMapEventWriteSWVec__filbufLoopPtrread_cmdSigAllocCntInsertTimeTLinePtrgenWarningfrptvrvec_fVtimeLbufLenctimevCatalyst__xargcfoutp_finiupcpin_allocIsSignalJLLtxWriteCycVector__ctype_GLOBAL_OFFSET_TABLE_LoopReturnCcompare__environ_lockfprintfdftv_fmake_groupvT2000LoopCnt__iobSignalCnt_lib_versionvrstat_ffputcsetbuffauxcompactedfopen64TLine__cg92_usedlbptrlengthsscanfvJ973_timstrstrfreeterminatescan_chainftrc___ArgvfinpIsTimeSetvrcmd_fJLisSideFileASCIIs3_acspecs_selmake_keyrewindPins_OnlyVMASTERWriteEventpidCycleDFTVIEWKEEPSCANfile_formatmaincheck_gzipTimescaleget_times3_getline__1cG__CrunMdo_exit_code6F_v_ovf_fileccmpVLineCntisBasicTimingTLineCntSetTimeSetWriteCycVecReadDVCatofvHP93000LeftExtendfdvcdblgt__fsr_init_valueat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J `@*` J ``@ *`J ` *` O 㻐7ᜀ "@% N @Ц 9}!x  `@H}`@@J`O,'M@`'`K`@@ ``'K`  2O`H@O!x`@ @ K `O ,@L`2H,`@'N!ހ@O!x G`'I@@`K`GJ`"@,,,N `@ /O    @  , O   2O,+1@GŒ""`"@   ;〦`@ !MK`@/K` @ (`K`(` O@{@ a2Hᜁ ᜀ6@f " ``O΀` ,6@Y M  O>``HZ/, "@ᜁ $@> ᠰ O    O `@/ O `@ -O  -O O @+`=`@,`: @ @H@H@@.`:`@`/ < Oᜀ OŘ  `@ ,1!`;a`L@/L``@ /`L`/` O@ݐ"@ᜁ  $@ΰ ;!ޤax!}9ް  `@ K @'/ K `@ *K  *O O5H`@/`H` @ + H` `+ `O`O@O@"@-a @H `@ (8@)`=@@uMM@ @jHHOL!} L!} @)M@`H` O L!}M@LM@Oax`GM @H`GJ@5L!} @+M@@ @ J O@ "M!M@@@Oax`GM @J G @I 2Hᜁ ᜀ OA`  㿠N `2@N` @#ށ b`@ /-9!@ HL@?@?.:@+ <  @ @v`L@L@@@ -ޮ`@iM`N@O`-M}`@,7N}x @L`O !M}N@`N@NxG`L@@ L `G H`@ M}"@0 N@9ި}!x@ M O N`wN@@@O!xGM@`M` G@L2` 1p?    㿠/@E@E@E@@E|@@Eo @Ex@Ex@Eu@ErL@N/ 6`@ @, N6`@O4+`@2 *`@ 1 ( 7 -5`@EJ@-  㿠㿠.%dwrrHOME*** Invalid KEY rrwbUSE_AUX_FILE %s USE_TRACE_FILE %s < < %s file successfully read. 0 %lf%lf%u%d%d%dWarning: (is=CLK) being ignored (not implemented in reader). r%d%u%c%u%lf%lf%d%d%s %lf ---> %s wUSE_TIMING_FILE %s %lf>TIME %d TIMESET TSET1 CYCLE %d %s %d X %d %d %d %d %d %d%d%d%d%d%d%d%s< Warning: Input Pin State character does not match pin direction. (%s-%d) Pin: %s; State = %c; First occurrence on Line # %d Warning: Output Pin State character does not match pin direction. (%s-%d) Pin: %s; State = %c; First occurrence on Line # %d Warning: No vectors were read by VREAD.BIN reader. (%s-%d) %drr %s %d--> %s %lfUNITS 1 UNITS .1 UNITS .01 UNITS .001 PINS %c%s %c%s%c%d%c ; Error: '%s' ; Cannot open vread command file. %s Unable to open vread intermediate file. Check for access rights and/or disk full. %s Cannot open Vector File '%s'. %s Max of 8 mux pins supported.'%s' Unsupported Vector file format.Insufficient memory available.Unable to process syntax on line %d of Vector File '%s'.No pins defined & no aux_file .Cannot open AUX file '%s'. %s '%s' Unsupported VLAIF format or type.'%s' Unrecognizable statement on line %d.'%s' Undefined pin identifier on line %d.Pin count >= %d Maximum number of pins exceeded.No WAVEFORM statement found in WGL file.Encountered End-of-File unexpectedly - line %d.Cannot open INCLUDE file '%s'. %s Unsupported format: %s No valid ports in vector file: %s.Syntax error: %s. Cannot continue due to fatal error(s). EPIC_VEC reader error - %s EPIC_VEC reader error - conflict of .vec file names. EPIC_VEC - number of pins defined by 'radix' does not match pin count.EPIC_VEC - no pins defined for this file.EPIC_VEC reader error - too many .vec files (10 max). Unsupported TDL_91 construct - %s Line #: %d WGL reader error - Vector entry length error near line %dUndeclared POWER pin name: %s. Line #: %d Undeclared pin name: %s. Line #: %d Unrecognized syntax - %s Line #: %d Illegal signal name character: '%c' Line #: %d Error writing to temp file. File possibly too large or disk full. %s Vector line contains too many states. Line #: %d Undeclared TIMING: %s. Line #: %d Use -cycle option for TIMING support Line #: %d WGL reader error - Pattern header length error near line %dScan chain with undefined edge pin near line %dIllegal syntax in STATE_TRANS Command Line #: %d Too many state translations specified Line #: %d Max Number of state-trans exceeded Line #: %d (%s-%d) 1 %c %s %d Error: '%s' ; Cannot open vread command file. %s Unable to open vread intermediate file. Check for access rights and/or disk full. %s Cannot open Vector File '%s'. %s Max of 8 mux pins supported.'%s' Unsupported Vector file format.Insufficient memory available.Unable to process syntax on line %d of Vector File '%s'.No pins defined & no aux_file .Cannot open AUX file '%s'. %s '%s' Unsupported VLAIF format or type.'%s' Unrecognizable statement on line %d.'%s' Undefined pin identifier on line %d.Pin count >= %d Maximum number of pins exceeded.No WAVEFORM statement found in WGL file.Encountered End-of-File unexpectedly - line %d.Cannot open INCLUDE file '%s'. %s Unsupported format: %s No valid ports in vector file: %s.Syntax error: %s. Cannot continue due to fatal error(s). EPIC_VEC reader error - %s EPIC_VEC reader error - conflict of .vec file names. EPIC_VEC - number of pins defined by 'radix' does not match pin count.EPIC_VEC - no pins defined for this file.EPIC_VEC reader error - too many .vec files (10 max). Unsupported TDL_91 construct - %s Line #: %d WGL reader error - Vector entry length error near line %dUndeclared POWER pin name: %s. Line #: %d Undeclared pin name: %s. Line #: %d Unrecognized syntax - %s Line #: %d Illegal signal name character: '%c' Line #: %d Error writing to temp file. File possibly too large or disk full. %s Vector line contains too many states. Line #: %d Undeclared TIMING: %s. Line #: %d Use -cycle option for TIMING support Line #: %d WGL reader error - Pattern header length error near line %dScan chain with undefined edge pin near line %dIllegal syntax in STATE_TRANS Command Line #: %d Too many state translations specified Line #: %d Max Number of state-trans exceeded Line #: %d . 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'M'Ю@'/* <  `! 0@- -  ''  D @ , '@@< '  '㿘ߐ  @Z!#$'`@N  ! 0,`,` @p'D! ,@1oﭐ  h @Ւc %@i$" @$L ] 'D!#,@ j'$,`$`$L :   $ !#$L :%$ c@h   l @$,`$`$L [   $ !#$L [%$,$ c@h ` p @`@h$#$ @T##c\  ?@?c\@ !#$ @=˲@h$ $ +bL/`$ eА"@?@w?# !#$ @# ''@ha% $ bL/`$@hW$  !"!"<+c\, !@eD#$@!!c\, $8 < `@  '!"Lc\, $ m!"H/`, !#|  @Β@ !$#!!.$ @'뎐 '㿘#a̠ $à !#Xc!#@!@d#!#!#,L %', $L !#!#,L -L  C  @㿈N N` N  'N``@ː N N`  @㿘@M L`) `*$L` `* ֒ `@㿈'$M` 'M` B)`O "O 01O .  `U u.   `!#$ !@ޒĴ O @ O0M`, #ct$ O #O 07,#c  @d !#$ !@@  O @ H`M` 0  9, #ct!#$L  A  F, #cX !#$ !@h!#$ O 6O 09,#c  @cO AF,#c  @c !#$ !@N4@  O +@M` D!@c` @ , %`` 1.   0.  .`%@ @㿘'DD@  "@h0% *'D&` #bL 0+bH-D, @, L / = @ #b0 $b0bH, , D$  'D7% 3'D&` #bL`0 s`1 t z+bH-D, @, L / = @ #b0 $b0bH, , D$  'Dx'D'HDH??!"(!#P!!XD !$"0@6!<#P pt؁ !"0 ! ,!#@!"("p"t!<#P!"(!"H@, M``L  -`#b0 $b0!#P@``,  P TD?$p$t`\!##c $cbX'b`%`!#@#c $cbx@#bpbt!$"(@"x"p"t "x"x"p"t "x'bx$!"("p"t!#PDx!#P@$#P$#T 㿐!#\!T#  !#@^!",`! ` ,: !@RF#T'!?#@< / : #@R8cT/ : @R3cT< / : #@R*cT> / : @R$cT/ : @RcT!"H, L !@R#T '!#\@#cT@R  ! / : @RcT! !?#@/ : !@Q#T!#T@Q    'č!#DD?x!# !#Tc@Q#cT%! ;X[X0p @QcT@Q   !#\@t!!@, d`` !#T`@Q!"`@`!#,/ <   㿘!#!#,L/`: c@T /`<``!L @?/`<`` 6 /!L @  !#c, $c,!#!#,L/`: c@/`<``!L @ 㿐N` @J`'. :`@ J 㿐  4!#!#,L/`: c"/`<  /`<`!#$, #c, $c,!#L/`: c/`<  !#$, 㿀N` `N@ N.:.@' ` 'N.:.@' `'㿈 @,N @)N`/`<`* < @/`<   @NN@ '@/`<`* < @㿘. :  a z" . : '㿘N `N @'㿈  !#\@!#V'%d >>%d >>0 %d)>%d Warning: Unable to find MACRO: %s w SCANCHAIN %s SCANLENGTH %d SCANIN %s SCANOUT %s SCANCHAIN_END %dSCAN %.3f %s %d %s SCAN %.3f %s %d %s ; VECTORDATA_END rw>TIME 0 TIMESET IMS_SET CYCLE %f %s %d X %.3lf %.3lf %.3lf %.3lf %d < USE_TIMING_FILE %s %d%d)>%d %d%d%lf%d%lf%d%di(I(di/dt%d%d %d%lf%lf %d )%d%d:%d%i]w(%d)%ir Loading file "%s"... Loaded %d lines from "%s". %i%itime=%ftime=%15.3lf, clock-phases=%d, clock-cycles=%d%d%d%d%d%s:%d %s %c%s %s Warning: a total of %d errors and %d warnings encountered. Error: pin "%s" in command file is not defined in ovf_file "%s". Warning: syntax error in file "%s" near character %d of line %d. Skipping: "%s" Warning: illegal first character on line %d in file "%s". Skipping: "%s" Error: decreasing time of "%s" encountered at line %d in file "%s". Warning: duplicate id "%s" follows .INDEX on line %d in file "%s". Warning: duplicate name "%s" follows .INDEX on line %d in file "%s". Error: missing %d state value%s on line %d in file "%s". Warning: skipping %d extra state value%s on line %d in file "%s". Error: duplicate definition for pin "%s" on line %d in file "%s". Warning: time offset for pin "%s" exceeds next time at line %d. Warning: missing "END" keyword on line %d in file "%s". Warning: first appearance of pin "%s" after time=0 on line %d in file "%s", causes two passes through input. Starting second pass through "%s". Error: while rewinding file "%s". Error: Unable to replace alias "%s" on line %d in file "%s". Warning: "%s" on line %d is ambiguous, skipping line. Warning: "ALIAS %s" on line %d of file "%s" cannot replace existing command. Warning: Alias "%s" on line %d of file "%s" cannot be removed. Error: syntax error on line %d of file "%s", skipping line. Warning: %d command(s) not recognized and placed in file "%s". Error: clock "%s" exceeds maximum number of phases (%d), on line %d in file "%s". Warning: second declaration of "CLOCK (PRIMARY)" on line %d in file "%s" ignored. Error: cannot define clock "%s" at time>0 on line %d in file "%s". Error: invalid CLOCK name "%s" on line %d in file "%s". Error: bus "%s" on line %d in file "%s" exceeds internal limit of %d. Error: bus "%s" on line %d in file "%s" is a duplicate name. Error: %d nodes do not match VECTOR %s bounds on line %d in file "%s". Error: unrecognized radix on line %d in file "%s". Error: illegal vector value "%s" on line %d in file "%s". Error: vector value on line %d in file "%s" cannot exceed %d bit(s). Error: invalid STEP time value on line %d in file "%s". Error: CYCLE/PHASE on line %d in file "%s" impossible if no CLOCK. Warning: "%s" on line %d in file "%s" is not a CLOCK. Error: RENAME/EQUIV on line %d in file "%s" impossible after time>0. Error: name "%s" on line %d in file "%s" not found. Error: new_name "%s" on line %d in file "%s" is invalid. Warning: EQUIV on line %d in file "%s" will override previous name. Warning: pin "%s" from command file not defined in ovf_file before time advances. Error: pin "%s" on line %d in file "%s" is doubly defined. Error: direction of pin "%s" does not match in command and ovf files. Warning: reached the %dth occurance of the prior message. No more messages of this type will be listed. --> %s %lfUNITS 1 UNITS .1 UNITS .01 UNITS .001 PINS %c%s %c%s%c%d%c ; Error: '%s' ; Cannot open vread command file. %s Unable to open vread intermediate file. Check for access rights and/or disk full. %s Cannot open Vector File '%s'. %s Max of 8 mux pins supported.'%s' Unsupported Vector file format.Insufficient memory available.Unable to process syntax on line %d of Vector File '%s'.No pins defined & no aux_file .Cannot open AUX file '%s'. %s '%s' Unsupported VLAIF format or type.'%s' Unrecognizable statement on line %d.'%s' Undefined pin identifier on line %d.Pin count >= %d Maximum number of pins exceeded.No WAVEFORM statement found in WGL file.Encountered End-of-File unexpectedly - line %d.Cannot open INCLUDE file '%s'. %s Unsupported format: %s No valid ports in vector file: %s.Syntax error: %s. Cannot continue due to fatal error(s). EPIC_VEC reader error - %s EPIC_VEC reader error - conflict of .vec file names. EPIC_VEC - number of pins defined by 'radix' does not match pin count.EPIC_VEC - no pins defined for this file.EPIC_VEC reader error - too many .vec files (10 max). Unsupported TDL_91 construct - %s Line #: %d WGL reader error - Vector entry length error near line %dUndeclared POWER pin name: %s. Line #: %d Undeclared pin name: %s. Line #: %d Unrecognized syntax - %s Line #: %d Illegal signal name character: '%c' Line #: %d Error writing to temp file. File possibly too large or disk full. %s Vector line contains too many states. Line #: %d Undeclared TIMING: %s. Line #: %d Use -cycle option for TIMING support Line #: %d WGL reader error - Pattern header length error near line %dScan chain with undefined edge pin near line %dIllegal syntax in STATE_TRANS Command Line #: %d Too many state translations specified Line #: %d Max Number of state-trans exceeded Line #: %d (%s-%d) 1 %c %s %d Error: '%s' ; Cannot open vread command file. %s Unable to open vread intermediate file. Check for access rights and/or disk full. %s Cannot open Vector File '%s'. %s Max of 8 mux pins supported.'%s' Unsupported Vector file format.Insufficient memory available.Unable to process syntax on line %d of Vector File '%s'.No pins defined & no aux_file .Cannot open AUX file '%s'. %s '%s' Unsupported VLAIF format or type.'%s' Unrecognizable statement on line %d.'%s' Undefined pin identifier on line %d.Pin count >= %d Maximum number of pins exceeded.No WAVEFORM statement found in WGL file.Encountered End-of-File unexpectedly - line %d.Cannot open INCLUDE file '%s'. %s Unsupported format: %s No valid ports in vector file: %s.Syntax error: %s. Cannot continue due to fatal error(s). EPIC_VEC reader error - %s EPIC_VEC reader error - conflict of .vec file names. EPIC_VEC - number of pins defined by 'radix' does not match pin count.EPIC_VEC - no pins defined for this file.EPIC_VEC reader error - too many .vec files (10 max). Unsupported TDL_91 construct - %s Line #: %d WGL reader error - Vector entry length error near line %dUndeclared POWER pin name: %s. Line #: %d Undeclared pin name: %s. Line #: %d Unrecognized syntax - %s Line #: %d Illegal signal name character: '%c' Line #: %d Error writing to temp file. File possibly too large or disk full. %s Vector line contains too many states. Line #: %d Undeclared TIMING: %s. Line #: %d Use -cycle option for TIMING support Line #: %d WGL reader error - Pattern header length error near line %dScan chain with undefined edge pin near line %dIllegal syntax in STATE_TRANS Command Line #: %d Too many state translations specified Line #: %d Max Number of state-trans exceeded Line #: %d . (%s-%d) )>%d )>%d @%15.0lf - @%15.3lf - ; ABSOLUTE_TIME UNITS %lf PINS %c%s%c%d%c %c%s ; 0Warning: Line %d had NULL character - line skipped s3_getline #%d: %s %d(00<0H0T0`0l0x00000000000000 0,080D0P0\0h0t0000 0 @0  o:o*@ot**p oo?@bM01ULHZNTY?X?@Y ,)= Ab <[>] ?<>[] (08*$Header: /export/home/chewie/Source3/Vtran/Src/Readers/RCS/vread2.c,v 1.16 2010/07/26 08:22:08 chewie Exp chewie $vread2.bin 9.3_vread1.sts_vread1.cmd_vread1.vec_vread1.tim_vread1.aux_vread1.trc_qsim.misVTRANVREADTDL_91TDL_91_CYCLEstdingzip -dc EPIC_OUTNANOSIM_OUTIMS_MEMTDL_91TDL_91_CYCLELSIMMENTOR_LSIMQSIMCOMPASS_QSIMOVF_FILENAMEAUX_FILENAMECASE_SENSITIVEPINS_ONLYCYCLE_DATASCANSCALECYCLEKEYFILE_FORMATTRACE_ONSILENTUSE_DOUBLEUSE_ABSOLUTE_TIMECOMPACT_OFFINHIBIT_COMMENTSENB_LOOPSENB_REPSDISABLE_LOOPSDISABLE_REPSPINS END;PSNSUSMSS(*$*)*)(**)*)=;(*$*)*)(**)*)TDL_VERSIONINCLUDE;CONNECT=VAR=DEFPIN);INOUTINOUT);.O.OTIMING;END_TIMINGSET_TIMING;PERIODCLOCK=VAR=HOLD0HOLD1PATTERN;010GROUP=VARDELAY=VAR=OFFSETSTROBE=VAR=OFFSETSETRTPL1SETREPEAT;END_REPEAT;END_REPEATSETRENDEND_REPEATRUNPTPL1FORMACRO;END_MACROEND_MACROCALL;MACRO;PATH=VAR=VAR=SCANTPL1FORSCAN_INSCAN_OUTSCAN_IN:=END_SCANENDASIC_TITLEASIC_TESTASIC_IGNOREASIC_ANNOTASIC_ANALOGTADJUST_SIM_VALUEIOMODE;ASIC_BIDI_CTRLDEFINE_IOMODETHRU_CURRENT,=VAR:=SETENDCLKInternalTESCALRESRADPOLFORSAMMASSeqAllREMENDIniSetMEMBINOCTHEXDECEND#TXTHALTREPLOOENDLOOCOM[]NRZDNRZRZR1RXIRCSBCSBIEDGEWINDOWTIMINGNSPSUSMSBINOCTHEXDECOFFPOSNEGPOWERRESOURCEFORCECOMPARE#TXTRESEND.O.O#TXTEND.TIME_RESOLUTION.HIGH_THRESHOLD.LOW_THRESHOLD.INDEXCODEFILEUNITSpsnsusINPUTSOUTPUTSCODING(ROM)END.O[].O.xXzZ.xXzZAALIASBUSCHARGEDCLOCKCYCLEECHOEQUIVEXITEXTERNALFORCEDHINPUTSLLOADPHASEPOPPREFIXQUITRENAMESSETSIVSTEPSVTTESTTIMEUVECTORZ01ULOWHIGHUNKNOWN(PRIMARY)INPUTOUTPUTBIDIRECTIONAL01ULOWHIGHUNKNOWNTTYSIMCSM(TOP)(DEFER-CLOCKS)ssrm erase 0000000100100011010001010110011110001001101010111100110111101111 0*@*p*|*, 0 @ P Ѱ |(t@ h 7 JXdP s|PdѰ sX 0*  cX E ! ,  Y  & 3 ;DM(VX^p hrw| $8P 6xD  P < ` /  l  0 1AD <D/4 NDW^<f4(< pPt;  M È0 ( 8L 1\ . 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