Application Notes:
VTRAN Template Cyclization Feature

After that, VTRAN cyclizes the source data, the user verifies cyclization and if not satisfied, repeats the process with different controls

Now lets look at some of the critical elements of cyclization. After collecting the required POC data, VTRAN is called with required commands and options to cyclize the data. The cyclization keywords and commands are focused on the following issues:

    Timesets
    Clock specification
    IO specification
    Conflict resolution in case of multiple Timeset matching
    Default behavior
    Debugging

Prior to the cyclization process, VTRAN uses the timing specified in each Timeset to compute the appropriate sample point within each cycle for each signal. For example, an input with a PINTYPE NRZ at 1.0 will be sampled at 1.0 ns into the cycle. A clock with PINTYPE RZ at (3.0,4.0) will be sampled at 3.5 ns into the cycle, and likewise outputs with a PINTYPE STB at (6.1, 6.2) will be sampled at 6.1 ns into the cycle. Once the sample times for all signals is computed, the cyclization process begins. This process continues sequentially thru the POC vectors, identifying the different cycles, sampling state data at the computed times and generating the cyclized vectors with their appropriate Timeset tags. Once the TEMPLATE CYCLIZATION process is complete, the timing specified in the TIMESET blocks is then used to specify the Timesets for the cycle-based output file. Note that all the conditions, flags and parameters specified in a Timeset need to be true within a section section of the POC data to construe a matched-cycle. Refer to VTRAN Users Guide for complete Cycle-Matching process description and algorithm.

The TEMPLATE CYCLIZATION feature is invoked in the PROC_BLOCK by specifying a TEMPLATE_CYCLIZATION command. All global parameters influencing cyclization are defined as options to the TEMPLATE_CYCLIZATION command as shown below:

PROC_BLOCK
   begin
   TEMPLATE_CYCLIZATION
     CYCLIZATION_SKEW = "0.5",
     TERMINATE_ON_DEFAULTS = "-1", {disable messages}
     MATCH_REPORT = "addr_2to4.matches",
     MATCH_TRACE_START = 1,
     MATCH_TRACE_END = 100;

Lets look at these global parameters in some more detail. Before we start talking about Timesets and cycles, it is important to note that VTRAN uses the time unit of ns for all timings specified in the Timesets.

CYCLIZATION SKEW
This option allows the user to specify a SKEW tolerance to be used during waveform matching. If this parameter is not specified, the tolerance defaults to .5 fs (very small). Setting it to 0.5ns, for example, means that primary clock signal edges can make a transition within +-0.5ns of the PINTYPE timing specified and still be considered as a match.

TERMINATE_ON_DEFAULTS
This option influences VTRAN's behavior when it cannot match the IO activity, for a section of the POC data, to any of the user-specified Timesets. In those cases, it needs to fall back on the default Timeset. The user can explicitly define a default Timeset, as will be explained later. If none is defined, the very first Timeset definition VTRAN encounters becomes the default Timeset. Each time there is a -DEFAULT cycle used, a warning is sent to the screen (stderr).

Different values for the TERMINATE_ON_DEFAULTS parameter will affect the cyclization process as follows:

  -1   Cyclization will not terminate due to default matches.
       Also, no warning is issued when default is used.
   0   Cyclization will not terminate due to default matches.
       Warnings will be generated when default is used.
   n   Cyclization terminates when default used n times (n>0)
       Warnings are generated when default Timeset is used.

MATCH REPORT
Cyclizing vectors with multiple cycle-types is a difficult task. To aid translation, VTRAN provides a window into its efforts by generating a detailed report of all its cycle matching. The parameters MATCH_REPORT and MATCH_TRACE direct VTRAN to print cycle matching results in a given range. The match report contains a wealth of information useful in debugging the cyclization process and adjusting the matching criteria. The MATCH_REPORT parameter specifies a file name and directs vtran to place cycle matching statistics in this file. The range specified between MATCH_TRACE_START and MATCH_TRACE_END parameters controls the length of this trace. The syntax for these is:

    MATCH_TRACE_START = nn;
    MATCH_TRACE_STOP = mm;

Where nn and mm are the cycle numbers for starting and stopping the trace. A sample match report is shown for an example later in this note. VTRAN will not check validity of the start and stop values or the range specified therein.

TIMESETS
The Timesets provide the main control of the cyclization process. TIMESETs are blocks of statements, which specify a cycle time (CYCLE command) and the signal behavior/timing (using PINTYPE commands). VTRAN allows the user to specify a number of TIMESETs that are included in the POC vector data, and then performs cyclization on the data by matching the different TIMESET waveforms with the waveforms found in the POC data. Using this feature, for example, VTRAN can cyclize a VCD file that included several different cycle types (with different cycle times and signal timing) such as say a scan_cycle, a capture_cycle and a run_cycle. In addition to being used to determine MATCHing and establish the sample point for all signals, the timing specified is also used directly as timing in the output file. Timesets start and end with TIMESET <NAME> and ENDTIMESET respectively as shown in the following example.

   TIMESET run
     CYCLE = 50;
     PINTYPE NRZ * @ 0;
     PINTYPE NRZ se @ 20;
     PINTYPE NRZ scan_mode @ 20;
     PINTYPE -PRIMARY RZ clk @ 25, 50;
     PINTYPE STB * @ 35;
     WEIGHT 2;
   ENDTIMESET;

The unique name of this Timeset is run, with a period of 50ns. Note that the implicit time unit is ns. If the desired cycle time is 50 ps, then the above period should be defined as: CYCLE = 0.050.

The Input Sampling Time is derived from the standard VTRAN PINTYPE commands, which define the timing and behavior of all pins. The input sampling times used in this example are explained below:

     PINTYPE NRZ * @ 0; - sample all inputs at start of cycle
     PINTYPE NRZ se @ 20;    - sample se 20ns into cycle
     PINTYPE NRZ scan_mode @ 20; - sample se 20ns into cycle
     PINTYPE RZ clk @ 20, 50;  - sample clk 37.5ns into cycle

The Output Strobe Time is also specified using standard VTRAN commands as shown below:

     PINTYPE STB * @ 35; - sample all outputs 35ns into cycle

CLOCK SPECIFICATION
A given Timeset can have 1 or more signals defined as clocks, as shown below:

     PINTYPE -PRIMARY RZ clkA @ 25, 50;
     PINTYPE -PRIMARY -ACTIVE_ONLY RZ clkB @ 25, 50;

Clocks can be declared as -PRIMARY signals for matching the Timeset. This means that their PINTYPE waveform and timing behavior will be used as criteria in the cycle-mathcing process. In a given TIMESET, if multiple signals have a -PRIMARY flag set in their PINTYPE statements, then they become a logical AND operation from a cycle matching perspective. The -ACTIVE_ONLY flag allows a match only when the clock does a full pulse. Default behavior is passive match, which means that the clock pulse is not needed and a Timeset will match as long as at least one other condition matches. Note that there is no such option as: -PASSIVE_ONLY - it is implicit default. Care should be taken while using -ACTIVE_ONLY flag. If during scan shifting process, there are dead cycles, VTRAN will not match scan-load-unload clocks and instead match the defaults if the -ACTIVE_ONLY flag is set.

In addition, an IDENTIFIER statement can be included in the TIMESET block to provide logical information that can be used as an alternative to the -PRIMARY signals (or in conjunction with them) during the cycle identification process. Note that the logic state values used in the IDENTIFIER statements are those state characters coming directly from the file being read, and are determined at the sample time in the cycle (as computed from the PINTYPE timing specified). The load_unload Timeset example below with a period of 100ns illustrates use of IDENTIFIER statement.

   TIMESET load_unload -DEFAULT
     CYCLE = 100;
     PINTYPE NRZ * @ 0;
     PINTYPE NRZ se @ 20;
     PINTYPE NRZ scan_mode @ 20;
     PINTYPE -PRIMARY RZ clk @ 50, 100;
     PINTYPE STB * @ 60;
     IDENTIFIER (se=1)&(scan_mode=1);
   ENDTIMESET;

The IDENTIFIER statement is optional, but can be a very effective way to accurately accomplish cycle-matching. It can be any complex logical equation constructed using the signals specified in the vector source. It can be used in lieu of, or in addition to the -PRIMARY flag for the clock specification. If both an IDENTIFIER statement and -PRIMARY flags are specified, a Timeset can match if and only if the -PRIMARY clock activity matches AND the IDENTIFIER equation is also true. The use of IDENTIFIER criteria for cycle identification & matching is strongly recommended. Since the matching algorithm produces a MISMATCH whenever any of the -PRIMARY or IDENTIFIER criteria fails, the strategy for specifying these criteria in the TIMESET blocks should focus on identifying criteria which, collectively, uniquely identify the TIMESET. Note that only one IDENTIFIER is allowed per TIMESET. IDENTIFIER statements are local to a TIMESET. They are capable of not allowing their parent Timeset to match, but in no way do they affect matching of any other Timeset.

Currently, VTRAN will not cyclize Timesets with overlapping clock boundaries. Clock glitches also require special attention. Glitches need to be handled on case-by-case basis. User should evaluate the source vector-data and identify glitches and their timings. Then a Sink_Timeset should be created for VTRAN to match during clock glitches. Such Sink_Timesets can then be filtered out during post processing through filters outside VTRAN.

Sometimes, more than 1 TIMESET will match a certain cyclical activity. In order to provide further guidance to the cyclization process, a WEIGHT parameter can be specified for each matched TIMESET, which will be used to resolve cycles where more than one TIMESET has a match. The WEIGHT parameter gives a Timeset extra weight during cycle matching. A matched TIMESET with no WEIGHT will loose during a conflict with a weighted matched TIMESET. VTRAN has the facility to specify a default TIMESET (the -DEFAULT flag after the TIMESET name). If none is specified, VTRAN chooses the first defined TIMESET as the default.

Select Range
For cases where the user knows the exact times where a particular timeset or timesets should be selected, this information can be used by vtran to make the selection.  The cyclization process can be made more efficient by using time ranges in which a specific timeset should be selected.  One example of a case where this feature can greatly improve efficiency is when TIMESET blocks used with TEMPLATE_CYCLIZATION  have cycle lengths that differ from each other by orders of magnitude. The SELECT_RANGE statement in the TIMESET block allows the user to specify the time ranges where the TIMESET is to be selected.  The syntax for this is:

   SELECT_RANGE start_time end_time ;

for example:

   SELECT_RANGE 2000.0 12000.0 ;

The start time value of the SELECT_RANGE statement is included in the time sequence in which the timeset should be selected. The end time of the SELECT_RANGE statement is excluded; it is the time at which normal template cyclization should resume, or at which a different SELECT_RANGE statement may start. The SELECT_RANGE statement is optional. A TIMESET block may have multiple SELECT_RANGE statements. Active ranges may be defined for multiple timesets, but must not overlap. When the selected timeset for a cycle is defined by a SELECT_RANGE statement, the normal template cyclization checks of PRIMARY signals and IDENTIFIERs for all TIMESETs are skipped, i.e. the SELECT_RANGE criteria , when met, overrides any other selection criteria.

TIMESET Selection for Cyclized Vectors
As well as cyclization of POC vector data, TEMPLATE_CYCLIZATION supports the assignment of timesets to cyclized vectors. This mode is selected with the CYCLIZED_VECTORS statement in the TEMPLATE_CYCLIZATION block:

   TEMPLATE_CYCLIZATION
     ...
     CYCLIZED_VECTORS = "ON";

In the CYCLIZED_VECTORS mode, only the logic expression in the IDENTIFIER statement is used for timeset matching. Each TIMESET other than the DEFAULT must have an IDENTIFIER statement.

The CYCLIZED_VECTORS mode can be used for user-defined tabular formats, and also with Vtran canned readers that support the -cycle flag. Any timeset or timeplate or WaveformTable assignments in the source data will be replaced with the TIMESETS in the PROC_BLOCK.

Simple Address Decoder Example
For purpose of explaining template cyclization, we will consider a simple 2-to-4-address decoder circuit. Full verilog RTL, its TestBench and the associated VTRAN command file are provided. Perform the following steps to create complete data set for cyclization:

    Run verilog simulation on test_2to4.v
    Make sure you get the vcd file: addr_2to4.vcd
    Check the log file to ensure correct behavior
    Obtain VTRAN version 6.5 or above
    Execute VTRAN: VTRAN addr_2to4.cmd

Description of the test procedure to create POC or VCD file is as follows:

    Run normal decoder functionality with fast clock at 50ns periodd
    Switch to scan mode
    Perform scan shifting with slow clock at 100ns period
    Run fast capture clocks at 50ns period
    Switch to scan mode
    Perform scan shifting with slow clock at 100ns period

Address Decoder Testbench and Logic Instance

`timescale 1ns/1ps
module test_2to4;
  reg clk, scan_clk_in;
  wire clk_in;
  reg[1:0] a_in;
  wire[3:0] a_out;
  wire   so_out;
  reg si_in, se_in, rst_in, scan_mode_in;
  integer i;
  assign clk_in = scan_mode_in ? scan_clk_in : clk;
  decoder_2to4 inst1 (
    .a1(a_in[1]),
    .a2(a_in[0]),
    .clk(cli_in),
    .si(si_in),
    .se(se_in),
    .so(so_out),
    .reset(rst_in),
    .scan_mode(scan_mode_in),
    .decoded_addr_out(a_out)
    );
  always @(clk) begin
   #25;
   clk <= ~clk;
  end
  always @(scan_clk_in) begin
   #50;
   scan_clk_in <= ~scan_clk_in;
  end
  always @(si_in) begin
   #40;
   si_in = ~si_in;
   #60;
  end
  initial begin
   #0;
   $dumpfile("addr_2to4. vcd");
   $dumpvars;
   clk = 0;
   scan_clk_in = 0;
   a_in = 2'b00;
   si_in = 0;
   se_in = 0;
   rst_in = 0;
   scan_mode_in = 0;
   //
   for (i = 0; i <= 5; i = i+1) begin
    #20;
    a_in = a_in + 1'b1;
    #50;
   end
   $display ("Scan Testing Begins");
   $display ("Shifting 1s through scan chain");
   scan_mode_in = 1; // begin scan testing
   se_in= 1; // begin scan testing
   for (i = 0; i <= 5; i = i+1) begin
    #20;
    a_in = a_in + 1'b1;
    #50;
   end
   #15;
   force si_in = 0;
   $display ("Shifting 0s through scan chain");
   for (i = 0; i <= 5; i = i+1) begin
    #20;
    a_in = a_in + 1'b1;
    #50;
   end
   //
   #40; // wait for scan_clk to fall
   $display ("Capture");
   scan_mode_in = 0; // capture
   se_in = 0; // capture
   #90;
   scan_mode_in = 1; // shift out
   se_in = 1; // shift out
   $display ("Shift Out");
   for (i = 0; i <= 5; i = i+1) begin
    #20;
    a_in = a_in + 1'b1;
    #50;
   end
   #10;
   //
   $finish;
   end // initial begin
   
  always @(clk_in or scan_mode_in or se_in) begin
  $display("Time:%t,clk=%b,se=%b,smode=%b,a_in=%b, si=%b,se=%b",$stime,clk_in,se_in,scan_mode_in,a_in,si_in,se_in);
  end
  
  always @(a_out or so_out) begin
  $display("Time:%t   a_out=%b, SO=%b",$stime,a_out,so_out);
  end
  endmodule // test_2to4
  
  module decoder_2to4 (a1, a2, clk, si, se, so, reset, scan_mode, decoded_addr_out);
  input a1, a2, clk, si, se, reset, scan_mode;
  output so;
  output [3:0] decoded_addr_out;
  reg [3:0] decoded_addr_out;
  wire gated_reset = reset & ~scan_mode;
  assign so = decoded_addr_out[0];
  always @(posedge clk or posedge gated_reset) begin
   if (gated_reset)
    decoded_addr_out <= 4'h0;
   else if (clk) begin
    if (se) begin
     decoded_addr_out[3] <= #1 si;
     decoded_addr_out[2] <= #1 decoded_addr_out[3];
     decoded_addr_out[1] <= #1 decoded_addr_out[2];
     decoded_addr_out[0] <= #1 decoded_addr_out[1];
    end
    else begin
     decoded_addr_out[0] <= #1 !a1 & !a2; //00
     decoded_addr_out[1] <= #1 !a1 & a2; //01
     decoded_addr_out[2] <= #1 a1 & !a2; //10
     decoded_addr_out[3] <= #1 a1 & a2; //11
    end
   end
   end // always @ (posedge clk or posedge gated_reset)
 endmodule // decoder_2to4

The VTAN command file to translate VCD->STIL using TEMPLATE CYCLIZATION

 ovf_block
   begin
   orig_file addr_2to4.vcd ;
   script_format verilog_vcd ;
   INPUTS a1, a2, clk, si, se, reset, scan_mode;
   OUTPUTS so decoded_addr_out[3:0];
   end
 proc_block
   begin
   TEMPLATE_CYCLIZATION
   TERMINATE_ON_DEFAULTS = "-1",{ disable messages }
    MATCH_REPORT = "addr_2to4.matches",
    MATCH_TRACE_START = 1,
    MATCH_TRACE_END = 100;
   TIMESET run
    CYCLE = 50;
    PINTYPE NRZ * @ 0;
    PINTYPE NRZ se @ 20;
    PINTYPE NRZ scan_mode @ 20;
    PINTYPE -PRIMARY RZ clk @ 25, 50;
    PINTYPE STB * @ 35 ;
   ENDTIMESET;
   TIMESET load_unload
    CYCLE = 100;
    PINTYPE NRZ * @ 0;
    PINTYPE NRZ se @ 20;
    PINTYPE NRZ scan_mode @ 20;
    PINTYPE -PRIMARY RZ clk @ 50, 100;
    PINTYPE STB * @ 60 ;
    IDENTIFIER (se=1)&(scan_mode=1);
   ENDTIMESET;
   end
 tvf_block
   begin
   target_file addr_2to4.stil_out;
   simulator stil;
   end
 end
 

Match Report:

    TEMPLATE CYCLIZATION Match Report